hw/gt64xxx.c

   1 /*
   2  * QEMU GT64120 PCI host
   3  *
   4  * Copyright (c) 2006,2007 Aurelien Jarno
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "mips.h"
  27 #include "pci.h"
  28 #include "pc.h"
  29
  30 typedef target_phys_addr_t pci_addr_t;
  31 #include "pci_host.h"
  32
  33 //#define DEBUG
  34
  35 #ifdef DEBUG
  36 #define dprintf(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
  37 #else
  38 #define dprintf(fmt, ...)
  39 #endif
  40
  41 #define GT_REGS                 (0x1000 >> 2)
  42
  43 /* CPU Configuration */
  44 #define GT_CPU                  (0x000 >> 2)
  45 #define GT_MULTI                (0x120 >> 2)
  46
  47 /* CPU Address Decode */
  48 #define GT_SCS10LD              (0x008 >> 2)
  49 #define GT_SCS10HD              (0x010 >> 2)
  50 #define GT_SCS32LD              (0x018 >> 2)
  51 #define GT_SCS32HD              (0x020 >> 2)
  52 #define GT_CS20LD               (0x028 >> 2)
  53 #define GT_CS20HD               (0x030 >> 2)
  54 #define GT_CS3BOOTLD            (0x038 >> 2)
  55 #define GT_CS3BOOTHD            (0x040 >> 2)
  56 #define GT_PCI0IOLD             (0x048 >> 2)
  57 #define GT_PCI0IOHD             (0x050 >> 2)
  58 #define GT_PCI0M0LD             (0x058 >> 2)
  59 #define GT_PCI0M0HD             (0x060 >> 2)
  60 #define GT_PCI0M1LD             (0x080 >> 2)
  61 #define GT_PCI0M1HD             (0x088 >> 2)
  62 #define GT_PCI1IOLD             (0x090 >> 2)
  63 #define GT_PCI1IOHD             (0x098 >> 2)
  64 #define GT_PCI1M0LD             (0x0a0 >> 2)
  65 #define GT_PCI1M0HD             (0x0a8 >> 2)
  66 #define GT_PCI1M1LD             (0x0b0 >> 2)
  67 #define GT_PCI1M1HD             (0x0b8 >> 2)
  68 #define GT_ISD                  (0x068 >> 2)
  69
  70 #define GT_SCS10AR              (0x0d0 >> 2)
  71 #define GT_SCS32AR              (0x0d8 >> 2)
  72 #define GT_CS20R                (0x0e0 >> 2)
  73 #define GT_CS3BOOTR             (0x0e8 >> 2)
  74
  75 #define GT_PCI0IOREMAP          (0x0f0 >> 2)
  76 #define GT_PCI0M0REMAP          (0x0f8 >> 2)
  77 #define GT_PCI0M1REMAP          (0x100 >> 2)
  78 #define GT_PCI1IOREMAP          (0x108 >> 2)
  79 #define GT_PCI1M0REMAP          (0x110 >> 2)
  80 #define GT_PCI1M1REMAP          (0x118 >> 2)
  81
  82 /* CPU Error Report */
  83 #define GT_CPUERR_ADDRLO        (0x070 >> 2)
  84 #define GT_CPUERR_ADDRHI        (0x078 >> 2)
  85 #define GT_CPUERR_DATALO        (0x128 >> 2)            /* GT-64120A only  */
  86 #define GT_CPUERR_DATAHI        (0x130 >> 2)            /* GT-64120A only  */
  87 #define GT_CPUERR_PARITY        (0x138 >> 2)            /* GT-64120A only  */
  88
  89 /* CPU Sync Barrier */
  90 #define GT_PCI0SYNC             (0x0c0 >> 2)
  91 #define GT_PCI1SYNC             (0x0c8 >> 2)
  92
  93 /* SDRAM and Device Address Decode */
  94 #define GT_SCS0LD               (0x400 >> 2)
  95 #define GT_SCS0HD               (0x404 >> 2)
  96 #define GT_SCS1LD               (0x408 >> 2)
  97 #define GT_SCS1HD               (0x40c >> 2)
  98 #define GT_SCS2LD               (0x410 >> 2)
  99 #define GT_SCS2HD               (0x414 >> 2)
 100 #define GT_SCS3LD               (0x418 >> 2)
 101 #define GT_SCS3HD               (0x41c >> 2)
 102 #define GT_CS0LD                (0x420 >> 2)
 103 #define GT_CS0HD                (0x424 >> 2)
 104 #define GT_CS1LD                (0x428 >> 2)
 105 #define GT_CS1HD                (0x42c >> 2)
 106 #define GT_CS2LD                (0x430 >> 2)
 107 #define GT_CS2HD                (0x434 >> 2)
 108 #define GT_CS3LD                (0x438 >> 2)
 109 #define GT_CS3HD                (0x43c >> 2)
 110 #define GT_BOOTLD               (0x440 >> 2)
 111 #define GT_BOOTHD               (0x444 >> 2)
 112 #define GT_ADERR                (0x470 >> 2)
 113
 114 /* SDRAM Configuration */
 115 #define GT_SDRAM_CFG            (0x448 >> 2)
 116 #define GT_SDRAM_OPMODE         (0x474 >> 2)
 117 #define GT_SDRAM_BM             (0x478 >> 2)
 118 #define GT_SDRAM_ADDRDECODE     (0x47c >> 2)
 119
 120 /* SDRAM Parameters */
 121 #define GT_SDRAM_B0             (0x44c >> 2)
 122 #define GT_SDRAM_B1             (0x450 >> 2)
 123 #define GT_SDRAM_B2             (0x454 >> 2)
 124 #define GT_SDRAM_B3             (0x458 >> 2)
 125
 126 /* Device Parameters */
 127 #define GT_DEV_B0               (0x45c >> 2)
 128 #define GT_DEV_B1               (0x460 >> 2)
 129 #define GT_DEV_B2               (0x464 >> 2)
 130 #define GT_DEV_B3               (0x468 >> 2)
 131 #define GT_DEV_BOOT             (0x46c >> 2)
 132
 133 /* ECC */
 134 #define GT_ECC_ERRDATALO        (0x480 >> 2)            /* GT-64120A only  */
 135 #define GT_ECC_ERRDATAHI        (0x484 >> 2)            /* GT-64120A only  */
 136 #define GT_ECC_MEM              (0x488 >> 2)            /* GT-64120A only  */
 137 #define GT_ECC_CALC             (0x48c >> 2)            /* GT-64120A only  */
 138 #define GT_ECC_ERRADDR          (0x490 >> 2)            /* GT-64120A only  */
 139
 140 /* DMA Record */
 141 #define GT_DMA0_CNT             (0x800 >> 2)
 142 #define GT_DMA1_CNT             (0x804 >> 2)
 143 #define GT_DMA2_CNT             (0x808 >> 2)
 144 #define GT_DMA3_CNT             (0x80c >> 2)
 145 #define GT_DMA0_SA              (0x810 >> 2)
 146 #define GT_DMA1_SA              (0x814 >> 2)
 147 #define GT_DMA2_SA              (0x818 >> 2)
 148 #define GT_DMA3_SA              (0x81c >> 2)
 149 #define GT_DMA0_DA              (0x820 >> 2)
 150 #define GT_DMA1_DA              (0x824 >> 2)
 151 #define GT_DMA2_DA              (0x828 >> 2)
 152 #define GT_DMA3_DA              (0x82c >> 2)
 153 #define GT_DMA0_NEXT            (0x830 >> 2)
 154 #define GT_DMA1_NEXT            (0x834 >> 2)
 155 #define GT_DMA2_NEXT            (0x838 >> 2)
 156 #define GT_DMA3_NEXT            (0x83c >> 2)
 157 #define GT_DMA0_CUR             (0x870 >> 2)
 158 #define GT_DMA1_CUR             (0x874 >> 2)
 159 #define GT_DMA2_CUR             (0x878 >> 2)
 160 #define GT_DMA3_CUR             (0x87c >> 2)
 161
 162 /* DMA Channel Control */
 163 #define GT_DMA0_CTRL            (0x840 >> 2)
 164 #define GT_DMA1_CTRL            (0x844 >> 2)
 165 #define GT_DMA2_CTRL            (0x848 >> 2)
 166 #define GT_DMA3_CTRL            (0x84c >> 2)
 167
 168 /* DMA Arbiter */
 169 #define GT_DMA_ARB              (0x860 >> 2)
 170
 171 /* Timer/Counter */
 172 #define GT_TC0                  (0x850 >> 2)
 173 #define GT_TC1                  (0x854 >> 2)
 174 #define GT_TC2                  (0x858 >> 2)
 175 #define GT_TC3                  (0x85c >> 2)
 176 #define GT_TC_CONTROL           (0x864 >> 2)
 177
 178 /* PCI Internal */
 179 #define GT_PCI0_CMD             (0xc00 >> 2)
 180 #define GT_PCI0_TOR             (0xc04 >> 2)
 181 #define GT_PCI0_BS_SCS10        (0xc08 >> 2)
 182 #define GT_PCI0_BS_SCS32        (0xc0c >> 2)
 183 #define GT_PCI0_BS_CS20         (0xc10 >> 2)
 184 #define GT_PCI0_BS_CS3BT        (0xc14 >> 2)
 185 #define GT_PCI1_IACK            (0xc30 >> 2)
 186 #define GT_PCI0_IACK            (0xc34 >> 2)
 187 #define GT_PCI0_BARE            (0xc3c >> 2)
 188 #define GT_PCI0_PREFMBR         (0xc40 >> 2)
 189 #define GT_PCI0_SCS10_BAR       (0xc48 >> 2)
 190 #define GT_PCI0_SCS32_BAR       (0xc4c >> 2)
 191 #define GT_PCI0_CS20_BAR        (0xc50 >> 2)
 192 #define GT_PCI0_CS3BT_BAR       (0xc54 >> 2)
 193 #define GT_PCI0_SSCS10_BAR      (0xc58 >> 2)
 194 #define GT_PCI0_SSCS32_BAR      (0xc5c >> 2)
 195 #define GT_PCI0_SCS3BT_BAR      (0xc64 >> 2)
 196 #define GT_PCI1_CMD             (0xc80 >> 2)
 197 #define GT_PCI1_TOR             (0xc84 >> 2)
 198 #define GT_PCI1_BS_SCS10        (0xc88 >> 2)
 199 #define GT_PCI1_BS_SCS32        (0xc8c >> 2)
 200 #define GT_PCI1_BS_CS20         (0xc90 >> 2)
 201 #define GT_PCI1_BS_CS3BT        (0xc94 >> 2)
 202 #define GT_PCI1_BARE            (0xcbc >> 2)
 203 #define GT_PCI1_PREFMBR         (0xcc0 >> 2)
 204 #define GT_PCI1_SCS10_BAR       (0xcc8 >> 2)
 205 #define GT_PCI1_SCS32_BAR       (0xccc >> 2)
 206 #define GT_PCI1_CS20_BAR        (0xcd0 >> 2)
 207 #define GT_PCI1_CS3BT_BAR       (0xcd4 >> 2)
 208 #define GT_PCI1_SSCS10_BAR      (0xcd8 >> 2)
 209 #define GT_PCI1_SSCS32_BAR      (0xcdc >> 2)
 210 #define GT_PCI1_SCS3BT_BAR      (0xce4 >> 2)
 211 #define GT_PCI1_CFGADDR         (0xcf0 >> 2)
 212 #define GT_PCI1_CFGDATA         (0xcf4 >> 2)
 213 #define GT_PCI0_CFGADDR         (0xcf8 >> 2)
 214 #define GT_PCI0_CFGDATA         (0xcfc >> 2)
 215
 216 /* Interrupts */
 217 #define GT_INTRCAUSE            (0xc18 >> 2)
 218 #define GT_INTRMASK             (0xc1c >> 2)
 219 #define GT_PCI0_ICMASK          (0xc24 >> 2)
 220 #define GT_PCI0_SERR0MASK       (0xc28 >> 2)
 221 #define GT_CPU_INTSEL           (0xc70 >> 2)
 222 #define GT_PCI0_INTSEL          (0xc74 >> 2)
 223 #define GT_HINTRCAUSE           (0xc98 >> 2)
 224 #define GT_HINTRMASK            (0xc9c >> 2)
 225 #define GT_PCI0_HICMASK         (0xca4 >> 2)
 226 #define GT_PCI1_SERR1MASK       (0xca8 >> 2)
 227
 228
 229 typedef PCIHostState GT64120PCIState;
 230
 231 #define PCI_MAPPING_ENTRY(regname)            \
 232     target_phys_addr_t regname ##_start;      \
 233     target_phys_addr_t regname ##_length;     \
 234     int regname ##_handle
 235
 236 typedef struct GT64120State {
 237     GT64120PCIState *pci;
 238     uint32_t regs[GT_REGS];
 239     PCI_MAPPING_ENTRY(PCI0IO);
 240     PCI_MAPPING_ENTRY(ISD);
 241 } GT64120State;
 242
 243 /* Adjust range to avoid touching space which isn't mappable via PCI */
 244 /* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
 245                                     0x1fc00000 - 0x1fd00000  */
 246 static void check_reserved_space (target_phys_addr_t *start,
 247                                   target_phys_addr_t *length)
 248 {
 249     target_phys_addr_t begin = *start;
 250     target_phys_addr_t end = *start + *length;
 251
 252     if (end >= 0x1e000000LL && end < 0x1f100000LL)
 253         end = 0x1e000000LL;
 254     if (begin >= 0x1e000000LL && begin < 0x1f100000LL)
 255         begin = 0x1f100000LL;
 256     if (end >= 0x1fc00000LL && end < 0x1fd00000LL)
 257         end = 0x1fc00000LL;
 258     if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL)
 259         begin = 0x1fd00000LL;
 260     /* XXX: This is broken when a reserved range splits the requested range */
 261     if (end >= 0x1f100000LL && begin < 0x1e000000LL)
 262         end = 0x1e000000LL;
 263     if (end >= 0x1fd00000LL && begin < 0x1fc00000LL)
 264         end = 0x1fc00000LL;
 265
 266     *start = begin;
 267     *length = end - begin;
 268 }
 269
 270 static void gt64120_isd_mapping(GT64120State *s)
 271 {
 272     target_phys_addr_t start = s->regs[GT_ISD] << 21;
 273     target_phys_addr_t length = 0x1000;
 274
 275     if (s->ISD_length)
 276         cpu_register_physical_memory(s->ISD_start, s->ISD_length,
 277                                      IO_MEM_UNASSIGNED);
 278     check_reserved_space(&start, &length);
 279     length = 0x1000;
 280     /* Map new address */
 281     dprintf("ISD: %x@%x -> %x@%x, %x\n", s->ISD_length, s->ISD_start,
 282             length, start, s->ISD_handle);
 283     s->ISD_start = start;
 284     s->ISD_length = length;
 285     cpu_register_physical_memory(s->ISD_start, s->ISD_length, s->ISD_handle);
 286 }
 287
 288 static void gt64120_pci_mapping(GT64120State *s)
 289 {
 290     /* Update IO mapping */
 291     if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD])
 292     {
 293       /* Unmap old IO address */
 294       if (s->PCI0IO_length)
 295       {
 296         cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED);
 297       }
 298       /* Map new IO address */
 299       s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
 300       s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
 301       isa_mem_base = s->PCI0IO_start;
 302       isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length);
 303     }
 304 }
 305
 306 static void gt64120_writel (void *opaque, target_phys_addr_t addr,
 307                             uint32_t val)
 308 {
 309     GT64120State *s = opaque;
 310     uint32_t saddr;
 311
 312     if (!(s->regs[GT_CPU] & 0x00001000))
 313         val = bswap32(val);
 314
 315     saddr = (addr & 0xfff) >> 2;
 316     switch (saddr) {
 317
 318     /* CPU Configuration */
 319     case GT_CPU:
 320         s->regs[GT_CPU] = val;
 321         break;
 322     case GT_MULTI:
 323         /* Read-only register as only one GT64xxx is present on the CPU bus */
 324         break;
 325
 326     /* CPU Address Decode */
 327     case GT_PCI0IOLD:
 328         s->regs[GT_PCI0IOLD]    = val & 0x00007fff;
 329         s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
 330         gt64120_pci_mapping(s);
 331         break;
 332     case GT_PCI0M0LD:
 333         s->regs[GT_PCI0M0LD]    = val & 0x00007fff;
 334         s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
 335         break;
 336     case GT_PCI0M1LD:
 337         s->regs[GT_PCI0M1LD]    = val & 0x00007fff;
 338         s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
 339         break;
 340     case GT_PCI1IOLD:
 341         s->regs[GT_PCI1IOLD]    = val & 0x00007fff;
 342         s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
 343         break;
 344     case GT_PCI1M0LD:
 345         s->regs[GT_PCI1M0LD]    = val & 0x00007fff;
 346         s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
 347         break;
 348     case GT_PCI1M1LD:
 349         s->regs[GT_PCI1M1LD]    = val & 0x00007fff;
 350         s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
 351         break;
 352     case GT_PCI0IOHD:
 353         s->regs[saddr] = val & 0x0000007f;
 354         gt64120_pci_mapping(s);
 355         break;
 356     case GT_PCI0M0HD:
 357     case GT_PCI0M1HD:
 358     case GT_PCI1IOHD:
 359     case GT_PCI1M0HD:
 360     case GT_PCI1M1HD:
 361         s->regs[saddr] = val & 0x0000007f;
 362         break;
 363     case GT_ISD:
 364         s->regs[saddr] = val & 0x00007fff;
 365         gt64120_isd_mapping(s);
 366         break;
 367
 368     case GT_PCI0IOREMAP:
 369     case GT_PCI0M0REMAP:
 370     case GT_PCI0M1REMAP:
 371     case GT_PCI1IOREMAP:
 372     case GT_PCI1M0REMAP:
 373     case GT_PCI1M1REMAP:
 374         s->regs[saddr] = val & 0x000007ff;
 375         break;
 376
 377     /* CPU Error Report */
 378     case GT_CPUERR_ADDRLO:
 379     case GT_CPUERR_ADDRHI:
 380     case GT_CPUERR_DATALO:
 381     case GT_CPUERR_DATAHI:
 382     case GT_CPUERR_PARITY:
 383         /* Read-only registers, do nothing */
 384         break;
 385
 386     /* CPU Sync Barrier */
 387     case GT_PCI0SYNC:
 388     case GT_PCI1SYNC:
 389         /* Read-only registers, do nothing */
 390         break;
 391
 392     /* SDRAM and Device Address Decode */
 393     case GT_SCS0LD:
 394     case GT_SCS0HD:
 395     case GT_SCS1LD:
 396     case GT_SCS1HD:
 397     case GT_SCS2LD:
 398     case GT_SCS2HD:
 399     case GT_SCS3LD:
 400     case GT_SCS3HD:
 401     case GT_CS0LD:
 402     case GT_CS0HD:
 403     case GT_CS1LD:
 404     case GT_CS1HD:
 405     case GT_CS2LD:
 406     case GT_CS2HD:
 407     case GT_CS3LD:
 408     case GT_CS3HD:
 409     case GT_BOOTLD:
 410     case GT_BOOTHD:
 411     case GT_ADERR:
 412     /* SDRAM Configuration */
 413     case GT_SDRAM_CFG:
 414     case GT_SDRAM_OPMODE:
 415     case GT_SDRAM_BM:
 416     case GT_SDRAM_ADDRDECODE:
 417         /* Accept and ignore SDRAM interleave configuration */
 418         s->regs[saddr] = val;
 419         break;
 420
 421     /* Device Parameters */
 422     case GT_DEV_B0:
 423     case GT_DEV_B1:
 424     case GT_DEV_B2:
 425     case GT_DEV_B3:
 426     case GT_DEV_BOOT:
 427         /* Not implemented */
 428         dprintf ("Unimplemented device register offset 0x%x\n", saddr << 2);
 429         break;
 430
 431     /* ECC */
 432     case GT_ECC_ERRDATALO:
 433     case GT_ECC_ERRDATAHI:
 434     case GT_ECC_MEM:
 435     case GT_ECC_CALC:
 436     case GT_ECC_ERRADDR:
 437         /* Read-only registers, do nothing */
 438         break;
 439
 440     /* DMA Record */
 441     case GT_DMA0_CNT:
 442     case GT_DMA1_CNT:
 443     case GT_DMA2_CNT:
 444     case GT_DMA3_CNT:
 445     case GT_DMA0_SA:
 446     case GT_DMA1_SA:
 447     case GT_DMA2_SA:
 448     case GT_DMA3_SA:
 449     case GT_DMA0_DA:
 450     case GT_DMA1_DA:
 451     case GT_DMA2_DA:
 452     case GT_DMA3_DA:
 453     case GT_DMA0_NEXT:
 454     case GT_DMA1_NEXT:
 455     case GT_DMA2_NEXT:
 456     case GT_DMA3_NEXT:
 457     case GT_DMA0_CUR:
 458     case GT_DMA1_CUR:
 459     case GT_DMA2_CUR:
 460     case GT_DMA3_CUR:
 461         /* Not implemented */
 462         dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
 463         break;
 464
 465     /* DMA Channel Control */
 466     case GT_DMA0_CTRL:
 467     case GT_DMA1_CTRL:
 468     case GT_DMA2_CTRL:
 469     case GT_DMA3_CTRL:
 470         /* Not implemented */
 471         dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
 472         break;
 473
 474     /* DMA Arbiter */
 475     case GT_DMA_ARB:
 476         /* Not implemented */
 477         dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
 478         break;
 479
 480     /* Timer/Counter */
 481     case GT_TC0:
 482     case GT_TC1:
 483     case GT_TC2:
 484     case GT_TC3:
 485     case GT_TC_CONTROL:
 486         /* Not implemented */
 487         dprintf ("Unimplemented timer register offset 0x%x\n", saddr << 2);
 488         break;
 489
 490     /* PCI Internal */
 491     case GT_PCI0_CMD:
 492     case GT_PCI1_CMD:
 493         s->regs[saddr] = val & 0x0401fc0f;
 494         break;
 495     case GT_PCI0_TOR:
 496     case GT_PCI0_BS_SCS10:
 497     case GT_PCI0_BS_SCS32:
 498     case GT_PCI0_BS_CS20:
 499     case GT_PCI0_BS_CS3BT:
 500     case GT_PCI1_IACK:
 501     case GT_PCI0_IACK:
 502     case GT_PCI0_BARE:
 503     case GT_PCI0_PREFMBR:
 504     case GT_PCI0_SCS10_BAR:
 505     case GT_PCI0_SCS32_BAR:
 506     case GT_PCI0_CS20_BAR:
 507     case GT_PCI0_CS3BT_BAR:
 508     case GT_PCI0_SSCS10_BAR:
 509     case GT_PCI0_SSCS32_BAR:
 510     case GT_PCI0_SCS3BT_BAR:
 511     case GT_PCI1_TOR:
 512     case GT_PCI1_BS_SCS10:
 513     case GT_PCI1_BS_SCS32:
 514     case GT_PCI1_BS_CS20:
 515     case GT_PCI1_BS_CS3BT:
 516     case GT_PCI1_BARE:
 517     case GT_PCI1_PREFMBR:
 518     case GT_PCI1_SCS10_BAR:
 519     case GT_PCI1_SCS32_BAR:
 520     case GT_PCI1_CS20_BAR:
 521     case GT_PCI1_CS3BT_BAR:
 522     case GT_PCI1_SSCS10_BAR:
 523     case GT_PCI1_SSCS32_BAR:
 524     case GT_PCI1_SCS3BT_BAR:
 525     case GT_PCI1_CFGADDR:
 526     case GT_PCI1_CFGDATA:
 527         /* not implemented */
 528         break;
 529     case GT_PCI0_CFGADDR:
 530         s->pci->config_reg = val & 0x80fffffc;
 531         break;
 532     case GT_PCI0_CFGDATA:
 533         if (!(s->regs[GT_PCI0_CMD] & 1) && (s->pci->config_reg & 0x00fff800))
 534             val = bswap32(val);
 535         if (s->pci->config_reg & (1u << 31))
 536             pci_data_write(s->pci->bus, s->pci->config_reg, val, 4);
 537         break;
 538
 539     /* Interrupts */
 540     case GT_INTRCAUSE:
 541         /* not really implemented */
 542         s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
 543         s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
 544         dprintf("INTRCAUSE %x\n", val);
 545         break;
 546     case GT_INTRMASK:
 547         s->regs[saddr] = val & 0x3c3ffffe;
 548         dprintf("INTRMASK %x\n", val);
 549         break;
 550     case GT_PCI0_ICMASK:
 551         s->regs[saddr] = val & 0x03fffffe;
 552         dprintf("ICMASK %x\n", val);
 553         break;
 554     case GT_PCI0_SERR0MASK:
 555         s->regs[saddr] = val & 0x0000003f;
 556         dprintf("SERR0MASK %x\n", val);
 557         break;
 558
 559     /* Reserved when only PCI_0 is configured. */
 560     case GT_HINTRCAUSE:
 561     case GT_CPU_INTSEL:
 562     case GT_PCI0_INTSEL:
 563     case GT_HINTRMASK:
 564     case GT_PCI0_HICMASK:
 565     case GT_PCI1_SERR1MASK:
 566         /* not implemented */
 567         break;
 568
 569     /* SDRAM Parameters */
 570     case GT_SDRAM_B0:
 571     case GT_SDRAM_B1:
 572     case GT_SDRAM_B2:
 573     case GT_SDRAM_B3:
 574         /* We don't simulate electrical parameters of the SDRAM.
 575            Accept, but ignore the values. */
 576         s->regs[saddr] = val;
 577         break;
 578
 579     default:
 580         dprintf ("Bad register offset 0x%x\n", (int)addr);
 581         break;
 582     }
 583 }
 584
 585 static uint32_t gt64120_readl (void *opaque,
 586                                target_phys_addr_t addr)
 587 {
 588     GT64120State *s = opaque;
 589     uint32_t val;
 590     uint32_t saddr;
 591
 592     saddr = (addr & 0xfff) >> 2;
 593     switch (saddr) {
 594
 595     /* CPU Configuration */
 596     case GT_MULTI:
 597         /* Only one GT64xxx is present on the CPU bus, return
 598            the initial value */
 599         val = s->regs[saddr];
 600         break;
 601
 602     /* CPU Error Report */
 603     case GT_CPUERR_ADDRLO:
 604     case GT_CPUERR_ADDRHI:
 605     case GT_CPUERR_DATALO:
 606     case GT_CPUERR_DATAHI:
 607     case GT_CPUERR_PARITY:
 608         /* Emulated memory has no error, always return the initial
 609            values */
 610         val = s->regs[saddr];
 611         break;
 612
 613     /* CPU Sync Barrier */
 614     case GT_PCI0SYNC:
 615     case GT_PCI1SYNC:
 616         /* Reading those register should empty all FIFO on the PCI
 617            bus, which are not emulated. The return value should be
 618            a random value that should be ignored. */
 619         val = 0xc000ffee;
 620         break;
 621
 622     /* ECC */
 623     case GT_ECC_ERRDATALO:
 624     case GT_ECC_ERRDATAHI:
 625     case GT_ECC_MEM:
 626     case GT_ECC_CALC:
 627     case GT_ECC_ERRADDR:
 628         /* Emulated memory has no error, always return the initial
 629            values */
 630         val = s->regs[saddr];
 631         break;
 632
 633     case GT_CPU:
 634     case GT_SCS10LD:
 635     case GT_SCS10HD:
 636     case GT_SCS32LD:
 637     case GT_SCS32HD:
 638     case GT_CS20LD:
 639     case GT_CS20HD:
 640     case GT_CS3BOOTLD:
 641     case GT_CS3BOOTHD:
 642     case GT_SCS10AR:
 643     case GT_SCS32AR:
 644     case GT_CS20R:
 645     case GT_CS3BOOTR:
 646     case GT_PCI0IOLD:
 647     case GT_PCI0M0LD:
 648     case GT_PCI0M1LD:
 649     case GT_PCI1IOLD:
 650     case GT_PCI1M0LD:
 651     case GT_PCI1M1LD:
 652     case GT_PCI0IOHD:
 653     case GT_PCI0M0HD:
 654     case GT_PCI0M1HD:
 655     case GT_PCI1IOHD:
 656     case GT_PCI1M0HD:
 657     case GT_PCI1M1HD:
 658     case GT_PCI0IOREMAP:
 659     case GT_PCI0M0REMAP:
 660     case GT_PCI0M1REMAP:
 661     case GT_PCI1IOREMAP:
 662     case GT_PCI1M0REMAP:
 663     case GT_PCI1M1REMAP:
 664     case GT_ISD:
 665         val = s->regs[saddr];
 666         break;
 667     case GT_PCI0_IACK:
 668         /* Read the IRQ number */
 669         val = pic_read_irq(isa_pic);
 670         break;
 671
 672     /* SDRAM and Device Address Decode */
 673     case GT_SCS0LD:
 674     case GT_SCS0HD:
 675     case GT_SCS1LD:
 676     case GT_SCS1HD:
 677     case GT_SCS2LD:
 678     case GT_SCS2HD:
 679     case GT_SCS3LD:
 680     case GT_SCS3HD:
 681     case GT_CS0LD:
 682     case GT_CS0HD:
 683     case GT_CS1LD:
 684     case GT_CS1HD:
 685     case GT_CS2LD:
 686     case GT_CS2HD:
 687     case GT_CS3LD:
 688     case GT_CS3HD:
 689     case GT_BOOTLD:
 690     case GT_BOOTHD:
 691     case GT_ADERR:
 692         val = s->regs[saddr];
 693         break;
 694
 695     /* SDRAM Configuration */
 696     case GT_SDRAM_CFG:
 697     case GT_SDRAM_OPMODE:
 698     case GT_SDRAM_BM:
 699     case GT_SDRAM_ADDRDECODE:
 700         val = s->regs[saddr];
 701         break;
 702
 703     /* SDRAM Parameters */
 704     case GT_SDRAM_B0:
 705     case GT_SDRAM_B1:
 706     case GT_SDRAM_B2:
 707     case GT_SDRAM_B3:
 708         /* We don't simulate electrical parameters of the SDRAM.
 709            Just return the last written value. */
 710         val = s->regs[saddr];
 711         break;
 712
 713     /* Device Parameters */
 714     case GT_DEV_B0:
 715     case GT_DEV_B1:
 716     case GT_DEV_B2:
 717     case GT_DEV_B3:
 718     case GT_DEV_BOOT:
 719         val = s->regs[saddr];
 720         break;
 721
 722     /* DMA Record */
 723     case GT_DMA0_CNT:
 724     case GT_DMA1_CNT:
 725     case GT_DMA2_CNT:
 726     case GT_DMA3_CNT:
 727     case GT_DMA0_SA:
 728     case GT_DMA1_SA:
 729     case GT_DMA2_SA:
 730     case GT_DMA3_SA:
 731     case GT_DMA0_DA:
 732     case GT_DMA1_DA:
 733     case GT_DMA2_DA:
 734     case GT_DMA3_DA:
 735     case GT_DMA0_NEXT:
 736     case GT_DMA1_NEXT:
 737     case GT_DMA2_NEXT:
 738     case GT_DMA3_NEXT:
 739     case GT_DMA0_CUR:
 740     case GT_DMA1_CUR:
 741     case GT_DMA2_CUR:
 742     case GT_DMA3_CUR:
 743         val = s->regs[saddr];
 744         break;
 745
 746     /* DMA Channel Control */
 747     case GT_DMA0_CTRL:
 748     case GT_DMA1_CTRL:
 749     case GT_DMA2_CTRL:
 750     case GT_DMA3_CTRL:
 751         val = s->regs[saddr];
 752         break;
 753
 754     /* DMA Arbiter */
 755     case GT_DMA_ARB:
 756         val = s->regs[saddr];
 757         break;
 758
 759     /* Timer/Counter */
 760     case GT_TC0:
 761     case GT_TC1:
 762     case GT_TC2:
 763     case GT_TC3:
 764     case GT_TC_CONTROL:
 765         val = s->regs[saddr];
 766         break;
 767
 768     /* PCI Internal */
 769     case GT_PCI0_CFGADDR:
 770         val = s->pci->config_reg;
 771         break;
 772     case GT_PCI0_CFGDATA:
 773         if (!(s->pci->config_reg & (1 << 31)))
 774             val = 0xffffffff;
 775         else
 776             val = pci_data_read(s->pci->bus, s->pci->config_reg, 4);
 777         if (!(s->regs[GT_PCI0_CMD] & 1) && (s->pci->config_reg & 0x00fff800))
 778             val = bswap32(val);
 779         break;
 780
 781     case GT_PCI0_CMD:
 782     case GT_PCI0_TOR:
 783     case GT_PCI0_BS_SCS10:
 784     case GT_PCI0_BS_SCS32:
 785     case GT_PCI0_BS_CS20:
 786     case GT_PCI0_BS_CS3BT:
 787     case GT_PCI1_IACK:
 788     case GT_PCI0_BARE:
 789     case GT_PCI0_PREFMBR:
 790     case GT_PCI0_SCS10_BAR:
 791     case GT_PCI0_SCS32_BAR:
 792     case GT_PCI0_CS20_BAR:
 793     case GT_PCI0_CS3BT_BAR:
 794     case GT_PCI0_SSCS10_BAR:
 795     case GT_PCI0_SSCS32_BAR:
 796     case GT_PCI0_SCS3BT_BAR:
 797     case GT_PCI1_CMD:
 798     case GT_PCI1_TOR:
 799     case GT_PCI1_BS_SCS10:
 800     case GT_PCI1_BS_SCS32:
 801     case GT_PCI1_BS_CS20:
 802     case GT_PCI1_BS_CS3BT:
 803     case GT_PCI1_BARE:
 804     case GT_PCI1_PREFMBR:
 805     case GT_PCI1_SCS10_BAR:
 806     case GT_PCI1_SCS32_BAR:
 807     case GT_PCI1_CS20_BAR:
 808     case GT_PCI1_CS3BT_BAR:
 809     case GT_PCI1_SSCS10_BAR:
 810     case GT_PCI1_SSCS32_BAR:
 811     case GT_PCI1_SCS3BT_BAR:
 812     case GT_PCI1_CFGADDR:
 813     case GT_PCI1_CFGDATA:
 814         val = s->regs[saddr];
 815         break;
 816
 817     /* Interrupts */
 818     case GT_INTRCAUSE:
 819         val = s->regs[saddr];
 820         dprintf("INTRCAUSE %x\n", val);
 821         break;
 822     case GT_INTRMASK:
 823         val = s->regs[saddr];
 824         dprintf("INTRMASK %x\n", val);
 825         break;
 826     case GT_PCI0_ICMASK:
 827         val = s->regs[saddr];
 828         dprintf("ICMASK %x\n", val);
 829         break;
 830     case GT_PCI0_SERR0MASK:
 831         val = s->regs[saddr];
 832         dprintf("SERR0MASK %x\n", val);
 833         break;
 834
 835     /* Reserved when only PCI_0 is configured. */
 836     case GT_HINTRCAUSE:
 837     case GT_CPU_INTSEL:
 838     case GT_PCI0_INTSEL:
 839     case GT_HINTRMASK:
 840     case GT_PCI0_HICMASK:
 841     case GT_PCI1_SERR1MASK:
 842         val = s->regs[saddr];
 843         break;
 844
 845     default:
 846         val = s->regs[saddr];
 847         dprintf ("Bad register offset 0x%x\n", (int)addr);
 848         break;
 849     }
 850
 851     if (!(s->regs[GT_CPU] & 0x00001000))
 852         val = bswap32(val);
 853
 854     return val;
 855 }
 856
 857 static CPUWriteMemoryFunc *gt64120_write[] = {
 858     &gt64120_writel,
 859     &gt64120_writel,
 860     &gt64120_writel,
 861 };
 862
 863 static CPUReadMemoryFunc *gt64120_read[] = {
 864     &gt64120_readl,
 865     &gt64120_readl,
 866     &gt64120_readl,
 867 };
 868
 869 static int pci_gt64120_map_irq(PCIDevice *pci_dev, int irq_num)
 870 {
 871     int slot;
 872
 873     slot = (pci_dev->devfn >> 3);
 874
 875     switch (slot) {
 876       /* PIIX4 USB */
 877       case 10:
 878         return 3;
 879       /* AMD 79C973 Ethernet */
 880       case 11:
 881         return 1;
 882       /* Crystal 4281 Sound */
 883       case 12:
 884         return 2;
 885       /* PCI slot 1 to 4 */
 886       case 18 ... 21:
 887         return ((slot - 18) + irq_num) & 0x03;
 888       /* Unknown device, don't do any translation */
 889       default:
 890         return irq_num;
 891     }
 892 }
 893
 894 static int pci_irq_levels[4];
 895
 896 static void pci_gt64120_set_irq(qemu_irq *pic, int irq_num, int level)
 897 {
 898     int i, pic_irq, pic_level;
 899
 900     pci_irq_levels[irq_num] = level;
 901
 902     /* now we change the pic irq level according to the piix irq mappings */
 903     /* XXX: optimize */
 904     pic_irq = piix4_dev->config[0x60 + irq_num];
 905     if (pic_irq < 16) {
 906         /* The pic level is the logical OR of all the PCI irqs mapped
 907            to it */
 908         pic_level = 0;
 909         for (i = 0; i < 4; i++) {
 910             if (pic_irq == piix4_dev->config[0x60 + i])
 911                 pic_level |= pci_irq_levels[i];
 912         }
 913         qemu_set_irq(pic[pic_irq], pic_level);
 914     }
 915 }
 916
 917
 918 static void gt64120_reset(void *opaque)
 919 {
 920     GT64120State *s = opaque;
 921
 922     /* FIXME: Malta specific hw assumptions ahead */
 923
 924     /* CPU Configuration */
 925 #ifdef TARGET_WORDS_BIGENDIAN
 926     s->regs[GT_CPU]           = 0x00000000;
 927 #else
 928     s->regs[GT_CPU]           = 0x00001000;
 929 #endif
 930     s->regs[GT_MULTI]         = 0x00000003;
 931
 932     /* CPU Address decode */
 933     s->regs[GT_SCS10LD]       = 0x00000000;
 934     s->regs[GT_SCS10HD]       = 0x00000007;
 935     s->regs[GT_SCS32LD]       = 0x00000008;
 936     s->regs[GT_SCS32HD]       = 0x0000000f;
 937     s->regs[GT_CS20LD]        = 0x000000e0;
 938     s->regs[GT_CS20HD]        = 0x00000070;
 939     s->regs[GT_CS3BOOTLD]     = 0x000000f8;
 940     s->regs[GT_CS3BOOTHD]     = 0x0000007f;
 941
 942     s->regs[GT_PCI0IOLD]      = 0x00000080;
 943     s->regs[GT_PCI0IOHD]      = 0x0000000f;
 944     s->regs[GT_PCI0M0LD]      = 0x00000090;
 945     s->regs[GT_PCI0M0HD]      = 0x0000001f;
 946     s->regs[GT_ISD]           = 0x000000a0;
 947     s->regs[GT_PCI0M1LD]      = 0x00000790;
 948     s->regs[GT_PCI0M1HD]      = 0x0000001f;
 949     s->regs[GT_PCI1IOLD]      = 0x00000100;
 950     s->regs[GT_PCI1IOHD]      = 0x0000000f;
 951     s->regs[GT_PCI1M0LD]      = 0x00000110;
 952     s->regs[GT_PCI1M0HD]      = 0x0000001f;
 953     s->regs[GT_PCI1M1LD]      = 0x00000120;
 954     s->regs[GT_PCI1M1HD]      = 0x0000002f;
 955
 956     s->regs[GT_SCS10AR]       = 0x00000000;
 957     s->regs[GT_SCS32AR]       = 0x00000008;
 958     s->regs[GT_CS20R]         = 0x000000e0;
 959     s->regs[GT_CS3BOOTR]      = 0x000000f8;
 960
 961     s->regs[GT_PCI0IOREMAP]   = 0x00000080;
 962     s->regs[GT_PCI0M0REMAP]   = 0x00000090;
 963     s->regs[GT_PCI0M1REMAP]   = 0x00000790;
 964     s->regs[GT_PCI1IOREMAP]   = 0x00000100;
 965     s->regs[GT_PCI1M0REMAP]   = 0x00000110;
 966     s->regs[GT_PCI1M1REMAP]   = 0x00000120;
 967
 968     /* CPU Error Report */
 969     s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
 970     s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
 971     s->regs[GT_CPUERR_DATALO] = 0xffffffff;
 972     s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
 973     s->regs[GT_CPUERR_PARITY] = 0x000000ff;
 974
 975     /* CPU Sync Barrier */
 976     s->regs[GT_PCI0SYNC]      = 0x00000000;
 977     s->regs[GT_PCI1SYNC]      = 0x00000000;
 978
 979     /* SDRAM and Device Address Decode */
 980     s->regs[GT_SCS0LD]        = 0x00000000;
 981     s->regs[GT_SCS0HD]        = 0x00000007;
 982     s->regs[GT_SCS1LD]        = 0x00000008;
 983     s->regs[GT_SCS1HD]        = 0x0000000f;
 984     s->regs[GT_SCS2LD]        = 0x00000010;
 985     s->regs[GT_SCS2HD]        = 0x00000017;
 986     s->regs[GT_SCS3LD]        = 0x00000018;
 987     s->regs[GT_SCS3HD]        = 0x0000001f;
 988     s->regs[GT_CS0LD]         = 0x000000c0;
 989     s->regs[GT_CS0HD]         = 0x000000c7;
 990     s->regs[GT_CS1LD]         = 0x000000c8;
 991     s->regs[GT_CS1HD]         = 0x000000cf;
 992     s->regs[GT_CS2LD]         = 0x000000d0;
 993     s->regs[GT_CS2HD]         = 0x000000df;
 994     s->regs[GT_CS3LD]         = 0x000000f0;
 995     s->regs[GT_CS3HD]         = 0x000000fb;
 996     s->regs[GT_BOOTLD]        = 0x000000fc;
 997     s->regs[GT_BOOTHD]        = 0x000000ff;
 998     s->regs[GT_ADERR]         = 0xffffffff;
 999
1000     /* SDRAM Configuration */
1001     s->regs[GT_SDRAM_CFG]     = 0x00000200;
1002     s->regs[GT_SDRAM_OPMODE]  = 0x00000000;
1003     s->regs[GT_SDRAM_BM]      = 0x00000007;
1004     s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;
1005
1006     /* SDRAM Parameters */
1007     s->regs[GT_SDRAM_B0]      = 0x00000005;
1008     s->regs[GT_SDRAM_B1]      = 0x00000005;
1009     s->regs[GT_SDRAM_B2]      = 0x00000005;
1010     s->regs[GT_SDRAM_B3]      = 0x00000005;
1011
1012     /* ECC */
1013     s->regs[GT_ECC_ERRDATALO] = 0x00000000;
1014     s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
1015     s->regs[GT_ECC_MEM]       = 0x00000000;
1016     s->regs[GT_ECC_CALC]      = 0x00000000;
1017     s->regs[GT_ECC_ERRADDR]   = 0x00000000;
1018
1019     /* Device Parameters */
1020     s->regs[GT_DEV_B0]        = 0x386fffff;
1021     s->regs[GT_DEV_B1]        = 0x386fffff;
1022     s->regs[GT_DEV_B2]        = 0x386fffff;
1023     s->regs[GT_DEV_B3]        = 0x386fffff;
1024     s->regs[GT_DEV_BOOT]      = 0x146fffff;
1025
1026     /* DMA registers are all zeroed at reset */
1027
1028     /* Timer/Counter */
1029     s->regs[GT_TC0]           = 0xffffffff;
1030     s->regs[GT_TC1]           = 0x00ffffff;
1031     s->regs[GT_TC2]           = 0x00ffffff;
1032     s->regs[GT_TC3]           = 0x00ffffff;
1033     s->regs[GT_TC_CONTROL]    = 0x00000000;
1034
1035     /* PCI Internal */
1036 #ifdef TARGET_WORDS_BIGENDIAN
1037     s->regs[GT_PCI0_CMD]      = 0x00000000;
1038 #else
1039     s->regs[GT_PCI0_CMD]      = 0x00010001;
1040 #endif
1041     s->regs[GT_PCI0_TOR]      = 0x0000070f;
1042     s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
1043     s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
1044     s->regs[GT_PCI0_BS_CS20]  = 0x01fff000;
1045     s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;
1046     s->regs[GT_PCI1_IACK]     = 0x00000000;
1047     s->regs[GT_PCI0_IACK]     = 0x00000000;
1048     s->regs[GT_PCI0_BARE]     = 0x0000000f;
1049     s->regs[GT_PCI0_PREFMBR]  = 0x00000040;
1050     s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;
1051     s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;
1052     s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;
1053     s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;
1054     s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
1055     s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
1056     s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
1057 #ifdef TARGET_WORDS_BIGENDIAN
1058     s->regs[GT_PCI1_CMD]      = 0x00000000;
1059 #else
1060     s->regs[GT_PCI1_CMD]      = 0x00010001;
1061 #endif
1062     s->regs[GT_PCI1_TOR]      = 0x0000070f;
1063     s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
1064     s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
1065     s->regs[GT_PCI1_BS_CS20]  = 0x01fff000;
1066     s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;
1067     s->regs[GT_PCI1_BARE]     = 0x0000000f;
1068     s->regs[GT_PCI1_PREFMBR]  = 0x00000040;
1069     s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;
1070     s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;
1071     s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;
1072     s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;
1073     s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;
1074     s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;
1075     s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;
1076     s->regs[GT_PCI1_CFGADDR]  = 0x00000000;
1077     s->regs[GT_PCI1_CFGDATA]  = 0x00000000;
1078     s->regs[GT_PCI0_CFGADDR]  = 0x00000000;
1079
1080     /* Interrupt registers are all zeroed at reset */
1081
1082     gt64120_isd_mapping(s);
1083     gt64120_pci_mapping(s);
1084 }
1085
1086 static uint32_t gt64120_read_config(PCIDevice *d, uint32_t address, int len)
1087 {
1088     return pci_default_read_config(d, address, len);
1089 }
1090
1091 static void gt64120_write_config(PCIDevice *d, uint32_t address, uint32_t val,
1092                                  int len)
1093 {
1094     pci_default_write_config(d, address, val, len);
1095 }
1096
1097 static void gt64120_save(QEMUFile* f, void *opaque)
1098 {
1099     PCIDevice *d = opaque;
1100     pci_device_save(d, f);
1101 }
1102
1103 static int gt64120_load(QEMUFile* f, void *opaque, int version_id)
1104 {
1105     PCIDevice *d = opaque;
1106     int ret;
1107
1108     if (version_id != 1)
1109         return -EINVAL;
1110     ret = pci_device_load(d, f);
1111     if (ret < 0)
1112         return ret;
1113     return 0;
1114 }
1115
1116 PCIBus *pci_gt64120_init(qemu_irq *pic)
1117 {
1118     GT64120State *s;
1119     PCIDevice *d;
1120
1121     (void)&pci_host_data_writeb; /* avoid warning */
1122     (void)&pci_host_data_writew; /* avoid warning */
1123     (void)&pci_host_data_writel; /* avoid warning */
1124     (void)&pci_host_data_readb; /* avoid warning */
1125     (void)&pci_host_data_readw; /* avoid warning */
1126     (void)&pci_host_data_readl; /* avoid warning */
1127
1128     s = qemu_mallocz(sizeof(GT64120State));
1129     s->pci = qemu_mallocz(sizeof(GT64120PCIState));
1130
1131     s->pci->bus = pci_register_bus(pci_gt64120_set_irq, pci_gt64120_map_irq,
1132                                    pic, 144, 4);
1133     s->ISD_handle = cpu_register_io_memory(0, gt64120_read, gt64120_write, s);
1134     d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice),
1135                             0, gt64120_read_config, gt64120_write_config);
1136
1137     /* FIXME: Malta specific hw assumptions ahead */
1138
1139     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MARVELL);
1140     pci_config_set_device_id(d->config, 0x4620); /* device_id */
1141
1142     d->config[0x04] = 0x00;
1143     d->config[0x05] = 0x00;
1144     d->config[0x06] = 0x80;
1145     d->config[0x07] = 0x02;
1146
1147     d->config[0x08] = 0x10;
1148     d->config[0x09] = 0x00;
1149     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
1150
1151     d->config[0x10] = 0x08;
1152     d->config[0x14] = 0x08;
1153     d->config[0x17] = 0x01;
1154     d->config[0x1B] = 0x1c;
1155     d->config[0x1F] = 0x1f;
1156     d->config[0x23] = 0x14;
1157     d->config[0x24] = 0x01;
1158     d->config[0x27] = 0x14;
1159     d->config[0x3D] = 0x01;
1160
1161     gt64120_reset(s);
1162
1163     register_savevm("GT64120 PCI Bus", 0, 1, gt64120_save, gt64120_load, d);
1164
1165     return s->pci->bus;
1166 }