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[S3C] Fix warnings
[sniper_test.git] / hw / s3c2410.c
blob355b246dabf2c441b00e5c9273ac372a1a96b955
1 /*
2 * Samsung S3C2410A RISC Microprocessor support (ARM920T based SoC).
3 *
4 * Copyright (c) 2007 OpenMoko, Inc.
5 * Author: Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This code is licenced under the GNU GPL v2.
8 */
9
10 #include "s3c.h"
11 #include "qemu-timer.h"
12 #include "qemu-char.h"
13 #include "hw.h"
14 #include "console.h"
15 #include "devices.h"
16 #include "arm-misc.h"
17 #include "i2c.h"
18 #include "pxa.h"
19 #include "sysemu.h"
20
21 /* Interrupt controller */
22 struct s3c_pic_state_s {
23 target_phys_addr_t base;
24 qemu_irq *parent_pic;
25 qemu_irq *irqs;
26
27 uint32_t srcpnd;
28 uint32_t intpnd;
29 uint32_t intmsk;
30 uint32_t intmod;
31 uint32_t priority;
32 int intoffset;
33 uint32_t subsrcpnd;
34 uint32_t intsubmsk;
35 };
36
37 static void s3c_pic_update(struct s3c_pic_state_s *s)
38 {
39 qemu_set_irq(s->parent_pic[ARM_PIC_CPU_FIQ],
40 s->srcpnd & s->intmod);
41 qemu_set_irq(s->parent_pic[ARM_PIC_CPU_IRQ],
42 s->intpnd & ~s->intmsk & ~s->intmod);
43 }
44
45 /*
46 * Performs interrupt arbitration and notifies the CPU.
47 *
48 * Since it's a complex logic which cannot be relied on by the OS
49 * anyway - first because real hardware doesn't do it accurately,
50 * second because it only matters when interrupts occur at the
51 * same time which normally can't be predicted - we use a simpler
52 * version for non-debug runs.
53 */
54 #ifdef DEBUG
55 static const uint32_t s3c_arbmsk[6] = {
56 0x0000000f,
57 0x000003f0,
58 0x0000fc00,
59 0x003f0000,
60 0x0fc00000,
61 0xf0000000,
62 };
63
64 # define S3C_ARB_SEL(i) ((s->priority >> (7 + (i << 1))) & 3)
65 # define S3C_ARB_MODE(i) ((s->priority >> i) & 1)
66 # define S3C_ARB_SEL_SET(i, v) \
67 s->priority &= ~(3 << (7 + (i << 1))); \
68 s->priority |= v << (7 + (i << 1));
69
70 static void s3c_pic_arbitrate(struct s3c_pic_state_s *s)
71 {
72 uint32_t pnd = s->srcpnd & ~s->intmsk & ~s->intmod;
73 int offset, i, arb;
74 if (s->intpnd || !pnd) {
75 s3c_pic_update(s);
76 return;
77 }
78
79 if (pnd & s3c_arbmsk[0]) {
80 offset = 0;
81 arb = 0;
82 } else if (pnd & 0x0ffffff0) {
83 i = S3C_ARB_SEL(6);
84 i ^= i << 1;
85 if (!(pnd & s3c_arbmsk[1 + (i & 3)]))
86 if (!(pnd & s3c_arbmsk[1 + (++ i & 3)]))
87 if (!(pnd & s3c_arbmsk[1 + (++ i & 3)]))
88 i ++;
89
90 if (S3C_ARB_MODE(6))
91 S3C_ARB_SEL_SET(6, ((i + 1) & 3));
92 offset = (i & 3) * 6 + 4;
93 if (pnd & (1 << offset))
94 goto known_offset;
95 else if (!(pnd & (0x1f << offset))) {
96 offset += 5;
97 goto known_offset;
98 }
99 offset ++;
100 arb = (i & 3) + 1;
101 } else {
102 arb = 5;
103 offset = 28;
104 }
105
106 pnd >>= offset;
107 i = S3C_ARB_SEL(arb);
108 i ^= i << 1;
109 if (!(pnd & (1 << (i & 3))))
110 if (!(pnd & (1 << (++ i & 3))))
111 if (!(pnd & (1 << (++ i & 3))))
112 i ++;
113
114 if (S3C_ARB_MODE(arb))
115 S3C_ARB_SEL_SET(arb, ((i + 1) & 3));
116 offset += i & 3;
117 known_offset:
118 s->intoffset = offset;
119 s->intpnd = 1 << offset;
120 s3c_pic_update(s);
121 }
122 #else
123 inline static void s3c_pic_arbitrate(struct s3c_pic_state_s *s)
124 {
125 uint32_t pnd = s->srcpnd & ~s->intmsk & ~s->intmod;
126 if (pnd && !s->intpnd)
127 s->intpnd = 1 << (s->intoffset = ffs(pnd) - 1);
128 s3c_pic_update(s);
129 }
130 #endif
131
132 static const int s3c_sub_src_map[] = {
133 [S3C_PICS_RXD0 & 31] = S3C_PIC_UART0,
134 [S3C_PICS_TXD0 & 31] = S3C_PIC_UART0,
135 [S3C_PICS_ERR0 & 31] = S3C_PIC_UART0,
136 [S3C_PICS_RXD1 & 31] = S3C_PIC_UART1,
137 [S3C_PICS_TXD1 & 31] = S3C_PIC_UART1,
138 [S3C_PICS_ERR1 & 31] = S3C_PIC_UART1,
139 [S3C_PICS_RXD2 & 31] = S3C_PIC_UART2,
140 [S3C_PICS_TXD2 & 31] = S3C_PIC_UART2,
141 [S3C_PICS_ERR2 & 31] = S3C_PIC_UART2,
142 [S3C_PICS_TC & 31] = S3C_PIC_ADC,
143 [S3C_PICS_ADC & 31] = S3C_PIC_ADC,
144 };
145
146 static void s3c_pic_subupdate(struct s3c_pic_state_s *s)
147 {
148 int next;
149 const int *sub = &s3c_sub_src_map[-1];
150 uint32_t pnd = s->subsrcpnd & ~s->intsubmsk;
151 while ((next = ffs(pnd))) {
152 sub += next;
153 pnd >>= next;
154 s->srcpnd |= 1 << *sub;
155 }
156 s3c_pic_arbitrate(s);
157 }
158
159 static void s3c_pic_set_irq(void *opaque, int irq, int req)
160 {
161 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *) opaque;
162 uint32_t mask;
163 /* This interrupt controller doesn't clear any request signals
164 * or register bits automatically. */
165 if (!req)
166 return;
167
168 if (irq & 32) {
169 irq &= 31;
170 s->subsrcpnd |= 1 << irq;
171 if (s->intsubmsk & (1 << irq))
172 return;
173 else
174 irq = s3c_sub_src_map[irq];
175 }
176 s->srcpnd |= (mask = 1 << irq);
177
178 /* A FIQ */
179 if (s->intmod & mask)
180 qemu_irq_raise(s->parent_pic[ARM_PIC_CPU_FIQ]);
181 else if (!s->intpnd && !(s->intmsk & mask)) {
182 #ifdef DEBUG
183 s3c_pic_arbitrate(s);
184 #else
185 s->intpnd = mask;
186 s->intoffset = irq;
187 qemu_irq_raise(s->parent_pic[ARM_PIC_CPU_IRQ]);
188 #endif
189 }
190 }
191
192 static void s3c_pic_reset(struct s3c_pic_state_s *s)
193 {
194 s->srcpnd = 0;
195 s->intpnd = 0;
196 s->intmsk = 0xffffffff;
197 s->intmod = 0;
198 s->priority = 0x7f;
199 s->intoffset = 0;
200 s->subsrcpnd = 0;
201 s->intsubmsk = 0x7ff;
202 s3c_pic_update(s);
203 }
204
205 #define S3C_SRCPND 0x00 /* Source Pending register */
206 #define S3C_INTMOD 0x04 /* Source Mode register */
207 #define S3C_INTMSK 0x08 /* Interrupt Mask register */
208 #define S3C_PRIORITY 0x0c /* Priority register */
209 #define S3C_INTPND 0x10 /* Interrupt Pending register */
210 #define S3C_INTOFFSET 0x14 /* Interrupt Offset register */
211 #define S3C_SUBSRCPND 0x18 /* Sub Source Pending register */
212 #define S3C_INTSUBMSK 0x1c /* Interrupt Sub Mask register */
213
214 static uint32_t s3c_pic_read(void *opaque, target_phys_addr_t addr)
215 {
216 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *) opaque;
217 addr -= s->base;
218
219 switch (addr) {
220 case S3C_SRCPND:
221 return s->srcpnd;
222 case S3C_INTPND:
223 return s->intpnd;
224 case S3C_INTMSK:
225 return s->intmsk;
226 case S3C_INTMOD:
227 return s->intmod;
228 case S3C_PRIORITY:
229 return s->priority;
230 case S3C_INTOFFSET:
231 return s->intoffset;
232 case S3C_SUBSRCPND:
233 return s->subsrcpnd;
234 case S3C_INTSUBMSK:
235 return s->intsubmsk;
236 default:
237 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
238 break;
239 }
240 return 0;
241 }
242
243 static void s3c_pic_write(void *opaque, target_phys_addr_t addr,
244 uint32_t value)
245 {
246 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *) opaque;
247 addr -= s->base;
248
249 switch (addr) {
250 case S3C_SRCPND:
251 s->srcpnd &= ~value;
252 if (value & s->intmod)
253 s3c_pic_update(s);
254 break;
255 case S3C_INTPND:
256 if (s->intpnd & value) {
257 s->intpnd = 0;
258 s->intoffset = 0;
259 s3c_pic_arbitrate(s);
260 }
261 break;
262 case S3C_INTMSK:
263 s->intmsk = value;
264 if (s->intpnd & value) {
265 s->intpnd = 0;
266 s->intoffset = 0;
267 }
268 s3c_pic_arbitrate(s);
269 break;
270 case S3C_INTMOD:
271 s->intmod = value;
272 break;
273 case S3C_PRIORITY:
274 s->priority = value;
275 break;
276 case S3C_SUBSRCPND:
277 s->subsrcpnd &= ~value;
278 break;
279 case S3C_INTSUBMSK:
280 s->intsubmsk = value;
281 s3c_pic_subupdate(s);
282 break;
283 default:
284 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
285 }
286 }
287
288 static CPUReadMemoryFunc *s3c_pic_readfn[] = {
289 s3c_pic_read,
290 s3c_pic_read,
291 s3c_pic_read,
292 };
293
294 static CPUWriteMemoryFunc *s3c_pic_writefn[] = {
295 s3c_pic_write,
296 s3c_pic_write,
297 s3c_pic_write,
298 };
299
300 static void s3c_pic_save(QEMUFile *f, void *opaque)
301 {
302 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *) opaque;
303 qemu_put_be32s(f, &s->srcpnd);
304 qemu_put_be32s(f, &s->intpnd);
305 qemu_put_be32s(f, &s->intmsk);
306 qemu_put_be32s(f, &s->intmod);
307 qemu_put_be32s(f, &s->priority);
308 qemu_put_be32s(f, &s->subsrcpnd);
309 qemu_put_be32s(f, &s->intsubmsk);
310 qemu_put_be32(f, s->intoffset);
311 }
312
313 static int s3c_pic_load(QEMUFile *f, void *opaque, int version_id)
314 {
315 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *) opaque;
316 qemu_get_be32s(f, &s->srcpnd);
317 qemu_get_be32s(f, &s->intpnd);
318 qemu_get_be32s(f, &s->intmsk);
319 qemu_get_be32s(f, &s->intmod);
320 qemu_get_be32s(f, &s->priority);
321 qemu_get_be32s(f, &s->subsrcpnd);
322 qemu_get_be32s(f, &s->intsubmsk);
323 s->intoffset = qemu_get_be32(f);
324 s3c_pic_update(s);
325 return 0;
326 }
327
328 struct s3c_pic_state_s *s3c_pic_init(target_phys_addr_t base,
329 qemu_irq *arm_pic)
330 {
331 int iomemtype;
332 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *)
333 qemu_mallocz(sizeof(struct s3c_pic_state_s));
334
335 s->base = base;
336 s->parent_pic = arm_pic;
337 s->irqs = qemu_allocate_irqs(s3c_pic_set_irq, s, S3C_PIC_MAX);
338
339 s3c_pic_reset(s);
340
341 iomemtype = cpu_register_io_memory(0, s3c_pic_readfn,
342 s3c_pic_writefn, s);
343 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
344
345 register_savevm("s3c24xx_pic", 0, 0, s3c_pic_save, s3c_pic_load, s);
346
347 return s;
348 }
349
350 qemu_irq *s3c_pic_get(struct s3c_pic_state_s *s)
351 {
352 return s->irqs;
353 }
354
355 /* Memory controller */
356 #define S3C_BWSCON 0x00 /* Bus Width & Wait Control register */
357 #define S3C_BANKCON0 0x04 /* Bank 0 Control register */
358 #define S3C_BANKCON1 0x08 /* Bank 1 Control register */
359 #define S3C_BANKCON2 0x0c /* Bank 2 Control register */
360 #define S3C_BANKCON3 0x10 /* Bank 3 Control register */
361 #define S3C_BANKCON4 0x14 /* Bank 4 Control register */
362 #define S3C_BANKCON5 0x18 /* Bank 5 Control register */
363 #define S3C_BANKCON6 0x1c /* Bank 6 Control register */
364 #define S3C_BANKCON7 0x20 /* Bank 7 Control register */
365 #define S3C_REFRESH 0x24 /* SDRAM Refresh Control register */
366 #define S3C_BANKSIZE 0x28 /* Flexible Bank Size register */
367 #define S3C_MRSRB6 0x2c /* Bank 6 Mode Set register */
368 #define S3C_MRSRB7 0x30 /* Bank 6 Mode Set register */
369
370 static void s3c_mc_reset(struct s3c_state_s *s)
371 {
372 s->mc_regs[S3C_BWSCON >> 2] = 0x0000000;
373 s->mc_regs[S3C_BANKCON0 >> 2] = 0x0700;
374 s->mc_regs[S3C_BANKCON1 >> 2] = 0x0700;
375 s->mc_regs[S3C_BANKCON2 >> 2] = 0x0700;
376 s->mc_regs[S3C_BANKCON3 >> 2] = 0x0700;
377 s->mc_regs[S3C_BANKCON4 >> 2] = 0x0700;
378 s->mc_regs[S3C_BANKCON5 >> 2] = 0x0700;
379 s->mc_regs[S3C_BANKCON6 >> 2] = 0x18008;
380 s->mc_regs[S3C_BANKCON7 >> 2] = 0x18008;
381 s->mc_regs[S3C_REFRESH >> 2] = 0xac0000;
382 s->mc_regs[S3C_BANKSIZE >> 2] = 0x2;
383 s->mc_regs[S3C_MRSRB6 >> 2] = 0x00;
384 s->mc_regs[S3C_MRSRB7 >> 2] = 0x00;
385 }
386
387 static uint32_t s3c_mc_read(void *opaque, target_phys_addr_t addr)
388 {
389 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
390 addr -= s->mc_base;
391
392 switch (addr >> 2) {
393 case S3C_BWSCON ... S3C_MRSRB7:
394 return s->mc_regs[addr >> 2];
395 default:
396 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
397 break;
398 }
399 return 0;
400 }
401
402 static void s3c_mc_write(void *opaque, target_phys_addr_t addr,
403 uint32_t value)
404 {
405 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
406 addr -= s->mc_base;
407
408 switch (addr >> 2) {
409 case S3C_BWSCON ... S3C_MRSRB7:
410 s->mc_regs[addr >> 2] = value;
411 break;
412 default:
413 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
414 }
415 }
416
417 static CPUReadMemoryFunc *s3c_mc_readfn[] = {
418 s3c_mc_read,
419 s3c_mc_read,
420 s3c_mc_read,
421 };
422
423 static CPUWriteMemoryFunc *s3c_mc_writefn[] = {
424 s3c_mc_write,
425 s3c_mc_write,
426 s3c_mc_write,
427 };
428
429 static void s3c_mc_save(QEMUFile *f, void *opaque)
430 {
431 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
432 int i;
433 for (i = 0; i < 13; i ++)
434 qemu_put_be32s(f, &s->mc_regs[i]);
435 }
436
437 static int s3c_mc_load(QEMUFile *f, void *opaque, int version_id)
438 {
439 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
440 int i;
441 for (i = 0; i < 13; i ++)
442 qemu_get_be32s(f, &s->mc_regs[i]);
443 return 0;
444 }
445
446 /* NAND Flash controller */
447 #define S3C_NFCONF 0x00 /* NAND Flash Configuration register */
448 #define S3C_NFCMD 0x04 /* NAND Flash Command Set register */
449 #define S3C_NFADDR 0x08 /* NAND Flash Address Set register */
450 #define S3C_NFDATA 0x0c /* NAND Flash Data register */
451 #define S3C_NFSTAT 0x10 /* NAND Flash Operation Status register */
452 #define S3C_NFECC 0x14 /* NAND Flash ECC register */
453
454 static void s3c_nand_reset(struct s3c_state_s *s)
455 {
456 s->nfconf = 0;
457 s->nfcmd = 0;
458 s->nfaddr = 0;
459 ecc_reset(&s->nfecc);
460 }
461
462 static uint32_t s3c_nand_read(void *opaque, target_phys_addr_t addr)
463 {
464 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
465 int rb, shr = 0;
466 if (!s->nand)
467 return 0;
468 addr -= s->nand_base;
469
470 switch (addr) {
471 case S3C_NFCONF:
472 return s->nfconf;
473 case S3C_NFCMD:
474 return s->nfcmd;
475 case S3C_NFADDR:
476 return s->nfaddr;
477 case S3C_NFDATA:
478 if (s->nfconf & (1 << 15))
479 return ecc_digest(&s->nfecc, nand_getio(s->nand));
480 break;
481 case S3C_NFSTAT:
482 nand_getpins(s->nand, &rb);
483 return rb;
484 case S3C_NFECC + 2: shr += 8;
485 case S3C_NFECC + 1: shr += 8;
486 case S3C_NFECC:
487 #define ECC(shr, b, shl) ((s->nfecc.lp[b] << (shl - shr)) & (1 << shl))
488 return (~(
489 ECC(0, 1, 0) | ECC(0, 0, 1) | ECC(1, 1, 2) | ECC(1, 0, 3) |
490 ECC(2, 1, 4) | ECC(2, 0, 5) | ECC(3, 1, 6) | ECC(3, 0, 7) |
491 ECC(4, 1, 8) | ECC(4, 0, 9) | ECC(5, 1, 10) | ECC(5, 0, 11) |
492 ECC(6, 1, 12) | ECC(6, 0, 13) | ECC(7, 1, 14) | ECC(7, 0, 15) |
493 ECC(8, 1, 16) | ECC(8, 0, 17) | (s->nfecc.cp << 18)) >> shr) &
494 0xff;
495 #undef ECC
496 default:
497 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
498 break;
499 }
500 return 0;
501 }
502
503 static void s3c_nand_write(void *opaque, target_phys_addr_t addr,
504 uint32_t value)
505 {
506 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
507 if (!s->nand)
508 return;
509 addr -= s->nand_base;
510
511 switch (addr) {
512 case S3C_NFCONF:
513 s->nfconf = value & 0x9fff;
514 if (value & (1 << 12))
515 ecc_reset(&s->nfecc);
516 break;
517 case S3C_NFCMD:
518 s->nfcmd = value & 0xff;
519 if (s->nfconf & (1 << 15)) {
520 nand_setpins(s->nand, 1, 0, (s->nfconf >> 11) & 1, s->nfwp, 0);
521 nand_setio(s->nand, s->nfcmd);
522 nand_setpins(s->nand, 0, 0, (s->nfconf >> 11) & 1, s->nfwp, 0);
523 }
524 break;
525 case S3C_NFADDR:
526 s->nfaddr = value & 0xff;
527 if (s->nfconf & (1 << 15)) {
528 nand_setpins(s->nand, 0, 1, (s->nfconf >> 11) & 1, s->nfwp, 0);
529 nand_setio(s->nand, s->nfaddr);
530 nand_setpins(s->nand, 0, 0, (s->nfconf >> 11) & 1, s->nfwp, 0);
531 }
532 break;
533 case S3C_NFDATA:
534 if (s->nfconf & (1 << 15))
535 nand_setio(s->nand, ecc_digest(&s->nfecc, value & 0xff));
536 break;
537 default:
538 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
539 }
540 }
541
542 void s3c_nand_register(struct s3c_state_s *s, struct nand_flash_s *chip)
543 {
544 s->nand = chip;
545 }
546
547 void s3c_nand_setwp(struct s3c_state_s *s, int wp)
548 {
549 s->nfwp = wp;
550 }
551
552 static CPUReadMemoryFunc *s3c_nand_readfn[] = {
553 s3c_nand_read,
554 s3c_nand_read,
555 s3c_nand_read,
556 };
557
558 static CPUWriteMemoryFunc *s3c_nand_writefn[] = {
559 s3c_nand_write,
560 s3c_nand_write,
561 s3c_nand_write,
562 };
563
564 static void s3c_nand_save(QEMUFile *f, void *opaque)
565 {
566 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
567 qemu_put_be16s(f, &s->nfconf);
568 qemu_put_8s(f, &s->nfcmd);
569 qemu_put_8s(f, &s->nfaddr);
570 qemu_put_be32(f, s->nfwp);
571 ecc_put(f, &s->nfecc);
572 }
573
574 static int s3c_nand_load(QEMUFile *f, void *opaque, int version_id)
575 {
576 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
577 qemu_get_be16s(f, &s->nfconf);
578 qemu_get_8s(f, &s->nfcmd);
579 qemu_get_8s(f, &s->nfaddr);
580 s->nfwp = qemu_get_be32(f);
581 ecc_get(f, &s->nfecc);
582 return 0;
583 }
584
585 /* Clock & power management */
586 #define S3C_LOCKTIME 0x00 /* PLL Lock Time Count register */
587 #define S3C_MPLLCON 0x04 /* MPLL Configuration register */
588 #define S3C_UPLLCON 0x08 /* UPLL Configuration register */
589 #define S3C_CLKCON 0x0c /* Clock Generator Control register */
590 #define S3C_CLKSLOW 0x10 /* Slow Clock Control register */
591 #define S3C_CLKDIVN 0x14 /* Clock Divider Control register */
592
593 static void s3c_clkpwr_reset(struct s3c_state_s *s)
594 {
595 s->clkpwr_regs[S3C_LOCKTIME >> 2] = 0x00ffffff;
596 s->clkpwr_regs[S3C_MPLLCON >> 2] = 0x0005c080;
597 s->clkpwr_regs[S3C_UPLLCON >> 2] = 0x00028080;
598 s->clkpwr_regs[S3C_CLKCON >> 2] = 0x0007fff0;
599 s->clkpwr_regs[S3C_CLKSLOW >> 2] = 0x00000004;
600 s->clkpwr_regs[S3C_CLKDIVN >> 2] = 0x00000000;
601 }
602
603 static uint32_t s3c_clkpwr_read(void *opaque, target_phys_addr_t addr)
604 {
605 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
606 addr -= s->clkpwr_base;
607
608 switch (addr) {
609 case S3C_LOCKTIME ... S3C_CLKDIVN:
610 return s->clkpwr_regs[addr >> 2];
611 default:
612 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
613 break;
614 }
615 return 0;
616 }
617
618 static void s3c_clkpwr_write(void *opaque, target_phys_addr_t addr,
619 uint32_t value)
620 {
621 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
622 addr -= s->clkpwr_base;
623
624 switch (addr) {
625 case S3C_LOCKTIME:
626 case S3C_MPLLCON:
627 case S3C_UPLLCON:
628 case S3C_CLKDIVN:
629 s->clkpwr_regs[addr >> 2] = value;
630 break;
631 case S3C_CLKCON:
632 if (value & (1 << 3)) {
633 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
634 printf("%s: processor powered off\n", __FUNCTION__);
635 s3c_gpio_setpwrstat(s->io, 2);
636 #if 0
637 cpu_reset(s->env);
638 s->env->regs[15] = 0; /* XXX */
639 #endif
640 } else
641 if (value & (1 << 2)) /* Normal IDLE mode */
642 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
643 if ((s->clkpwr_regs[addr >> 2] ^ value) & 1)
644 printf("%s: SPECIAL mode %s\n", __FUNCTION__,
645 (value & 1) ? "on" : "off");
646 s->clkpwr_regs[addr >> 2] = value;
647 break;
648 case S3C_CLKSLOW:
649 if ((s->clkpwr_regs[addr >> 2] ^ value) & (1 << 4))
650 printf("%s: SLOW mode %s\n", __FUNCTION__,
651 (value & (1 << 4)) ? "on" : "off");
652 s->clkpwr_regs[addr >> 2] = value;
653 break;
654 default:
655 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
656 }
657 }
658
659 static CPUReadMemoryFunc *s3c_clkpwr_readfn[] = {
660 s3c_clkpwr_read,
661 s3c_clkpwr_read,
662 s3c_clkpwr_read,
663 };
664
665 static CPUWriteMemoryFunc *s3c_clkpwr_writefn[] = {
666 s3c_clkpwr_write,
667 s3c_clkpwr_write,
668 s3c_clkpwr_write,
669 };
670
671 static void s3c_clkpwr_save(QEMUFile *f, void *opaque)
672 {
673 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
674 int i;
675 for (i = 0; i < 6; i ++)
676 qemu_put_be32s(f, &s->clkpwr_regs[i]);
677 }
678
679 static int s3c_clkpwr_load(QEMUFile *f, void *opaque, int version_id)
680 {
681 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
682 int i;
683 for (i = 0; i < 6; i ++)
684 qemu_get_be32s(f, &s->clkpwr_regs[i]);
685 return 0;
686 }
687
688 /* DMA controller */
689 #define S3C_DMA_CH_N 4
690
691 struct s3c_dma_ch_state_s;
692 struct s3c_dma_state_s { /* Modelled as an interrupt controller */
693 target_phys_addr_t base;
694 qemu_irq *drqs;
695 struct s3c_dma_ch_state_s {
696 qemu_irq intr;
697 int curr_tc;
698 int req;
699 int running;
700 uint32_t con;
701 uint32_t isrc;
702 uint32_t isrcc;
703 uint32_t idst;
704 uint32_t idstc;
705 uint32_t csrc;
706 uint32_t cdst;
707 uint32_t mask;
708 } ch[S3C_DMA_CH_N];
709 };
710
711 static inline void s3c_dma_ch_run(struct s3c_dma_state_s *s,
712 struct s3c_dma_ch_state_s *ch)
713 {
714 int width, burst, t;
715 uint8_t buffer[4];
716 width = 1 << ((ch->con >> 20) & 3); /* DSZ */
717 burst = (ch->con & (1 << 28)) ? 4 : 1; /* TSZ */
718
719 while (!ch->running && ch->curr_tc > 0 && ch->req &&
720 (ch->mask & (1 << 1))) { /* ON_OFF */
721 if (width > sizeof(buffer)) {
722 printf("%s: wrong access width\n", __FUNCTION__);
723 return;
724 }
725 ch->running = 1;
726 while (ch->curr_tc --) {
727 for (t = 0; t < burst; t ++) {
728 cpu_physical_memory_read(ch->csrc, buffer, width);
729 cpu_physical_memory_write(ch->cdst, buffer, width);
730
731 if (!(ch->isrcc & 1)) /* INT */
732 ch->csrc += width;
733 if (!(ch->idstc & 1)) /* INT */
734 ch->cdst += width;
735 }
736
737 if (!(ch->con & (1 << 27)) && !ch->req) /* SERVMODE */
738 break;
739 }
740 ch->running = 0;
741
742 if (!(ch->con & (1 << 23))) { /* SWHW_SEL */
743 ch->req = 0;
744 }
745
746 if (ch->curr_tc <= 0) {
747 if (ch->con & (1 << 22)) /* RELOAD */
748 ch->mask &= ~(1 << 1); /* ON_OFF */
749 else {
750 if (!(ch->con & (1 << 23))) { /* SWHW_SEL */
751 printf("%s: auto-reload software controlled transfer\n",
752 __FUNCTION__);
753 break;
754 }
755 ch->csrc = ch->isrc; /* S_ADDR */
756 ch->cdst = ch->idst; /* D_ADDR */
757 ch->curr_tc = ch->con & 0xfffff; /* TC */
758 ch->con |= 1 << 22; /* ON_OFF */
759 }
760
761 if (ch->con & (1 << 31)) /* DMD_HS */
762 ch->req = 0;
763
764 if (ch->con & (1 << 29)) { /* INT */
765 qemu_irq_raise(ch->intr);
766 /* Give the system a chance to respond. */
767 break;
768 }
769 }
770 }
771 }
772
773 static void s3c_dma_reset(struct s3c_dma_state_s *s)
774 {
775 int i;
776 for (i = 0; i < S3C_DMA_CH_N; i ++) {
777 s->ch[i].curr_tc = 0;
778 s->ch[i].csrc = 0;
779 s->ch[i].isrc = 0;
780 s->ch[i].isrcc = 0;
781 s->ch[i].cdst = 0;
782 s->ch[i].idst = 0;
783 s->ch[i].idstc = 0;
784 s->ch[i].con = 0;
785 s->ch[i].csrc = 0;
786 s->ch[i].cdst = 0;
787 s->ch[i].mask = 0;
788 }
789 }
790
791 static void s3c_dma_dreq(void *opaque, int line, int req)
792 {
793 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *) opaque;
794 struct s3c_dma_ch_state_s *ch = &s->ch[line >> 4];
795
796 if (ch->con & (1 << 23)) /* SWHW_SEL */
797 if (((ch->con >> 24) & 7) == (line & 7)) { /* HWSRCSEL */
798 ch->req = req;
799 s3c_dma_ch_run(s, ch);
800 }
801 }
802
803 #define S3C_DISRC 0x00 /* DMA Initial Source register */
804 #define S3C_DISRCC 0x04 /* DMA Initial Source Control register */
805 #define S3C_DIDST 0x08 /* DMA Initial Destination register */
806 #define S3C_DIDSTC 0x0c /* DMA Initial Destination Control register */
807 #define S3C_DCON 0x10 /* DMA Control register */
808 #define S3C_DSTAT 0x14 /* DMA Count register */
809 #define S3C_DCSRC 0x18 /* DMA Current Source register */
810 #define S3C_DCDST 0x1c /* DMA Current Destination register */
811 #define S3C_DMASKTRIG 0x20 /* DMA Mask Trigger register */
812
813 static uint32_t s3c_dma_read(void *opaque, target_phys_addr_t addr)
814 {
815 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *) opaque;
816 struct s3c_dma_ch_state_s *ch = 0;
817 addr -= s->base;
818 if (addr >= 0 && addr <= (S3C_DMA_CH_N << 6)) {
819 ch = &s->ch[addr >> 6];
820 addr &= 0x3f;
821 }
822
823 switch (addr) {
824 case S3C_DISRC:
825 return ch->isrc;
826 case S3C_DISRCC:
827 return ch->isrcc;
828 case S3C_DIDST:
829 return ch->idst;
830 case S3C_DIDSTC:
831 return ch->idstc;
832 case S3C_DCON:
833 return ch->con;
834 case S3C_DSTAT:
835 return ch->curr_tc;
836 case S3C_DCSRC:
837 return ch->csrc;
838 case S3C_DCDST:
839 return ch->cdst;
840 case S3C_DMASKTRIG:
841 return ch->mask;
842 default:
843 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
844 break;
845 }
846 return 0;
847 }
848
849 static void s3c_dma_write(void *opaque, target_phys_addr_t addr,
850 uint32_t value)
851 {
852 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *) opaque;
853 struct s3c_dma_ch_state_s *ch = 0;
854 addr -= s->base;
855 if (addr >= 0 && addr <= (S3C_DMA_CH_N << 6)) {
856 ch = &s->ch[addr >> 6];
857 addr &= 0x3f;
858 }
859
860 switch (addr) {
861 case S3C_DCON:
862 ch->con = value;
863 break;
864 case S3C_DISRC:
865 ch->isrc = value;
866 break;
867 case S3C_DISRCC:
868 ch->isrcc = value;
869 break;
870 case S3C_DIDST:
871 ch->idst = value;
872 break;
873 case S3C_DIDSTC:
874 ch->idstc = value;
875 break;
876 case S3C_DMASKTRIG:
877 if (~ch->mask & value & (1 << 1)) { /* ON_OFF */
878 ch->curr_tc = ch->con & 0xfffff; /* TC */
879 ch->csrc = ch->isrc; /* S_ADDR */
880 ch->cdst = ch->idst; /* D_ADDR */
881 }
882
883 ch->mask = value;
884 if (value & (1 << 2)) { /* STOP */
885 ch->mask &= ~(3 << 1); /* ON_OFF */
886 } else if (!(ch->con & (1 << 23))) { /* SWHW_SEL */
887 ch->req = value & 1; /* SW_TRIG */
888 s3c_dma_ch_run(s, ch);
889 }
890 break;
891 default:
892 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
893 }
894 }
895
896 static CPUReadMemoryFunc *s3c_dma_readfn[] = {
897 s3c_dma_read,
898 s3c_dma_read,
899 s3c_dma_read,
900 };
901
902 static CPUWriteMemoryFunc *s3c_dma_writefn[] = {
903 s3c_dma_write,
904 s3c_dma_write,
905 s3c_dma_write,
906 };
907
908 static void s3c_dma_save(QEMUFile *f, void *opaque)
909 {
910 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *) opaque;
911 int i;
912 for (i = 0; i < S3C_DMA_CH_N; i ++) {
913 qemu_put_be32(f, s->ch[i].curr_tc);
914 qemu_put_be32(f, s->ch[i].req);
915 qemu_put_be32s(f, &s->ch[i].con);
916 qemu_put_be32s(f, &s->ch[i].isrc);
917 qemu_put_be32s(f, &s->ch[i].isrcc);
918 qemu_put_be32s(f, &s->ch[i].idst);
919 qemu_put_be32s(f, &s->ch[i].idstc);
920 qemu_put_be32s(f, &s->ch[i].csrc);
921 qemu_put_be32s(f, &s->ch[i].cdst);
922 qemu_put_be32s(f, &s->ch[i].mask);
923 }
924 }
925
926 static int s3c_dma_load(QEMUFile *f, void *opaque, int version_id)
927 {
928 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *) opaque;
929 int i;
930 for (i = 0; i < S3C_DMA_CH_N; i ++) {
931 s->ch[i].curr_tc = qemu_get_be32(f);
932 s->ch[i].req = qemu_get_be32(f);
933 qemu_get_be32s(f, &s->ch[i].con);
934 qemu_get_be32s(f, &s->ch[i].isrc);
935 qemu_get_be32s(f, &s->ch[i].isrcc);
936 qemu_get_be32s(f, &s->ch[i].idst);
937 qemu_get_be32s(f, &s->ch[i].idstc);
938 qemu_get_be32s(f, &s->ch[i].csrc);
939 qemu_get_be32s(f, &s->ch[i].cdst);
940 qemu_get_be32s(f, &s->ch[i].mask);
941 }
942 return 0;
943 }
944
945 struct s3c_dma_state_s *s3c_dma_init(target_phys_addr_t base, qemu_irq *pic)
946 {
947 int iomemtype;
948 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *)
949 qemu_mallocz(sizeof(struct s3c_dma_state_s));
950
951 s->base = base;
952 s->ch[0].intr = pic[0];
953 s->ch[1].intr = pic[1];
954 s->ch[2].intr = pic[2];
955 s->ch[3].intr = pic[3];
956 s->drqs = qemu_allocate_irqs(s3c_dma_dreq, s, S3C_RQ_MAX);
957
958 s3c_dma_reset(s);
959
960 iomemtype = cpu_register_io_memory(0, s3c_dma_readfn,
961 s3c_dma_writefn, s);
962 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
963
964 register_savevm("s3c24xx_dma", 0, 0, s3c_dma_save, s3c_dma_load, s);
965
966 return s;
967 }
968
969 qemu_irq *s3c_dma_get(struct s3c_dma_state_s *s)
970 {
971 return s->drqs;
972 }
973
974 /* PWM timers controller */
975 struct s3c_timer_state_s;
976 struct s3c_timers_state_s {
977 target_phys_addr_t base;
978 qemu_irq *dma;
979 DisplayState *ds;
980 struct s3c_timer_state_s {
981 QEMUTimer *t;
982 struct s3c_timers_state_s *s;
983 int n;
984 int running;
985 uint32_t divider;
986 uint16_t count;
987 int64_t reload;
988 qemu_irq irq;
989 gpio_handler_t cmp_cb;
990 void *cmp_opaque;
991 } timer[5];
992
993 uint16_t compareb[4];
994 uint16_t countb[5];
995 uint32_t config[2];
996 uint32_t control;
997 };
998
999 static const int s3c_tm_bits[] = { 0, 8, 12, 16, 20 };
1000
1001 static uint16_t s3c_timers_get(struct s3c_timers_state_s *s, int tm)
1002 {
1003 uint16_t elapsed;
1004 if (!s->timer[tm].running)
1005 return s->timer[tm].count;
1006
1007 elapsed = muldiv64(qemu_get_clock(vm_clock) - s->timer[tm].reload,
1008 s->timer[tm].divider, ticks_per_sec);
1009 if (unlikely(elapsed > s->timer[tm].count))
1010 return s->timer[tm].count;
1011
1012 return s->timer[tm].count - elapsed;
1013 }
1014
1015 static void s3c_timers_stop(struct s3c_timers_state_s *s, int tm)
1016 {
1017 s->timer[tm].count = s3c_timers_get(s, tm);
1018 s->timer[tm].running = 0;
1019 }
1020
1021 static void s3c_timers_start(struct s3c_timers_state_s *s, int tm)
1022 {
1023 if (s->timer[tm].running)
1024 return;
1025
1026 s->timer[tm].divider = S3C_PCLK_FREQ >>
1027 (((s->config[1] >> (tm * 4)) & 3) + 1);
1028 if (tm < 2)
1029 s->timer[tm].divider /= ((s->config[0] >> 0) & 0xff) + 1;
1030 else
1031 s->timer[tm].divider /= ((s->config[0] >> 8) & 0xff) + 1;
1032 s->timer[tm].running = 1;
1033 s->timer[tm].reload = qemu_get_clock(vm_clock);
1034 qemu_mod_timer(s->timer[tm].t,
1035 s->timer[tm].reload + muldiv64(s->timer[tm].count,
1036 ticks_per_sec, s->timer[tm].divider));
1037 }
1038
1039 static void s3c_timers_reset(struct s3c_timers_state_s *s)
1040 {
1041 int i;
1042 s->config[0] = 0x00000000;
1043 s->config[1] = 0x00000000;
1044 s->control = 0x00000000;
1045
1046 for (i = 0; i < 5; i ++) {
1047 if (s->timer[i].running)
1048 s3c_timers_stop(s, i);
1049 s->countb[i] = 0x0000;
1050 s->timer[i].count = 0;
1051 }
1052 for (i = 0; i < 4; i ++)
1053 s->compareb[i] = 0x0000;
1054 }
1055
1056 static void s3c_timers_tick(void *opaque)
1057 {
1058 struct s3c_timer_state_s *t = (struct s3c_timer_state_s *) opaque;
1059 struct s3c_timers_state_s *s = t->s;
1060 if (!t->running)
1061 return;
1062
1063 if (((s->config[1] >> 20) & 0xf) == t->n + 1) {
1064 qemu_irq_raise(s->dma[S3C_RQ_TIMER0]); /* TODO */
1065 qemu_irq_raise(s->dma[S3C_RQ_TIMER1]);
1066 qemu_irq_raise(s->dma[S3C_RQ_TIMER2]);
1067 } else
1068 qemu_irq_raise(t->irq);
1069
1070 t->running = 0;
1071 t->count = 0;
1072
1073 if (s->control & (1 << ((t->n == 4) ? 22 : (s3c_tm_bits[t->n] + 3)))) {
1074 /* Auto-reload */
1075 t->count = s->countb[t->n];
1076 s3c_timers_start(s, t->n);
1077 } else
1078 s->control &= ~(1 << s3c_tm_bits[t->n]);
1079 }
1080
1081 #define S3C_TCFG0 0x00 /* Timer Configuration register 0 */
1082 #define S3C_TCFG1 0x04 /* Timer Configuration register 1 */
1083 #define S3C_TCON 0x08 /* Timer Control register */
1084 #define S3C_TCNTB0 0x0c /* Timer 0 Count Buffer register */
1085 #define S3C_TCMPB0 0x10 /* Timer 0 Compare Buffer register */
1086 #define S3C_TCNTO0 0x14 /* Timer 0 Count Observation register */
1087 #define S3C_TCNTB1 0x18 /* Timer 1 Count Buffer register */
1088 #define S3C_TCMPB1 0x1c /* Timer 1 Compare Buffer register */
1089 #define S3C_TCNTO1 0x20 /* Timer 1 Count Observation register */
1090 #define S3C_TCNTB2 0x24 /* Timer 2 Count Buffer register */
1091 #define S3C_TCMPB2 0x28 /* Timer 2 Compare Buffer register */
1092 #define S3C_TCNTO2 0x2c /* Timer 2 Count Observation register */
1093 #define S3C_TCNTB3 0x30 /* Timer 3 Count Buffer register */
1094 #define S3C_TCMPB3 0x34 /* Timer 3 Compare Buffer register */
1095 #define S3C_TCNTO3 0x38 /* Timer 3 Count Observation register */
1096 #define S3C_TCNTB4 0x3c /* Timer 4 Count Buffer register */
1097 #define S3C_TCNTO4 0x40 /* Timer 4 Count Observation register */
1098
1099 static uint32_t s3c_timers_read(void *opaque, target_phys_addr_t addr)
1100 {
1101 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *) opaque;
1102 int tm = 0;
1103 addr -= s->base;
1104
1105 switch (addr) {
1106 case S3C_TCFG0:
1107 return s->config[0];
1108 case S3C_TCFG1:
1109 return s->config[1];
1110 case S3C_TCON:
1111 return s->control;
1112 case S3C_TCMPB3: tm ++;
1113 case S3C_TCMPB2: tm ++;
1114 case S3C_TCMPB1: tm ++;
1115 case S3C_TCMPB0:
1116 return s->compareb[tm];
1117 case S3C_TCNTB4: tm ++;
1118 case S3C_TCNTB3: tm ++;
1119 case S3C_TCNTB2: tm ++;
1120 case S3C_TCNTB1: tm ++;
1121 case S3C_TCNTB0:
1122 return s->countb[tm];
1123 case S3C_TCNTO4: tm ++;
1124 case S3C_TCNTO3: tm ++;
1125 case S3C_TCNTO2: tm ++;
1126 case S3C_TCNTO1: tm ++;
1127 case S3C_TCNTO0:
1128 return s3c_timers_get(s, tm);
1129 default:
1130 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1131 break;
1132 }
1133 return 0;
1134 }
1135
1136 static void s3c_timers_write(void *opaque, target_phys_addr_t addr,
1137 uint32_t value)
1138 {
1139 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *) opaque;
1140 int tm = 0;
1141 addr -= s->base;
1142
1143 switch (addr) {
1144 case S3C_TCFG0:
1145 s->config[0] = value & 0x00ffffff;
1146 break;
1147 case S3C_TCFG1:
1148 s->config[1] = value & 0x00ffffff;
1149 break;
1150 case S3C_TCON:
1151 for (tm = 0; tm < 5; tm ++) {
1152 if (value & (2 << (s3c_tm_bits[tm]))) {
1153 if (s->timer[tm].running) {
1154 s3c_timers_stop(s, tm);
1155 s->timer[tm].count = s->countb[tm];
1156 s3c_timers_start(s, tm);
1157 } else
1158 s->timer[tm].count = s->countb[tm];
1159 }
1160 if (((value >> s3c_tm_bits[tm]) & 1) ^ s->timer[tm].running) {
1161 if (s->timer[tm].running)
1162 s3c_timers_stop(s, tm);
1163 else
1164 s3c_timers_start(s, tm);
1165 }
1166 }
1167
1168 s->control = value & 0x007fff1f;
1169 break;
1170 case S3C_TCMPB3: tm ++;
1171 case S3C_TCMPB2: tm ++;
1172 case S3C_TCMPB1: tm ++;
1173 case S3C_TCMPB0:
1174 s->compareb[tm] = value & 0xffff;
1175 if (s->timer[tm].cmp_cb)
1176 s->timer[tm].cmp_cb(tm, s->compareb[tm], s->timer[tm].cmp_opaque);
1177 break;
1178 case S3C_TCNTB4: tm ++;
1179 case S3C_TCNTB3: tm ++;
1180 case S3C_TCNTB2: tm ++;
1181 case S3C_TCNTB1: tm ++;
1182 case S3C_TCNTB0:
1183 s->countb[tm] = value & 0xffff;
1184 break;
1185 default:
1186 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1187 }
1188 }
1189
1190 static CPUReadMemoryFunc *s3c_timers_readfn[] = {
1191 s3c_timers_read,
1192 s3c_timers_read,
1193 s3c_timers_read,
1194 };
1195
1196 static CPUWriteMemoryFunc *s3c_timers_writefn[] = {
1197 s3c_timers_write,
1198 s3c_timers_write,
1199 s3c_timers_write,
1200 };
1201
1202 static void s3c_timers_save(QEMUFile *f, void *opaque)
1203 {
1204 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *) opaque;
1205 int i;
1206 for (i = 0; i < 5; i ++) {
1207 qemu_put_be32(f, s->timer[i].running);
1208 qemu_put_be32s(f, &s->timer[i].divider);
1209 qemu_put_be16(f, s3c_timers_get(s, i));
1210 qemu_put_be64s(f, &s->timer[i].reload);
1211 }
1212
1213 for (i = 0; i < 4; i ++)
1214 qemu_put_be16s(f, &s->compareb[i]);
1215 for (i = 0; i < 5; i ++)
1216 qemu_put_be16s(f, &s->countb[i]);
1217 for (i = 0; i < 2; i ++)
1218 qemu_put_be32s(f, &s->config[i]);
1219 qemu_put_be32s(f, &s->control);
1220 }
1221
1222 static int s3c_timers_load(QEMUFile *f, void *opaque, int version_id)
1223 {
1224 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *) opaque;
1225 int i, running[5];
1226 for (i = 0; i < 5; i ++) {
1227 s->timer[i].running = 0;
1228 running[i] = qemu_get_be32(f);
1229 qemu_get_be32s(f, &s->timer[i].divider);
1230 qemu_get_be16s(f, &s->timer[i].count);
1231 qemu_get_be64s(f, &s->timer[i].reload);
1232 }
1233
1234 for (i = 0; i < 4; i ++)
1235 qemu_get_be16s(f, &s->compareb[i]);
1236 for (i = 0; i < 5; i ++)
1237 qemu_get_be16s(f, &s->countb[i]);
1238 for (i = 0; i < 2; i ++)
1239 qemu_get_be32s(f, &s->config[i]);
1240 qemu_get_be32s(f, &s->control);
1241
1242 for (i = 0; i < 5; i ++)
1243 if (running[i])
1244 s3c_timers_start(s, i);
1245
1246 return 0;
1247 }
1248
1249 struct s3c_timers_state_s *s3c_timers_init(target_phys_addr_t base,
1250 qemu_irq *pic, qemu_irq *dma)
1251 {
1252 int i, iomemtype;
1253 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *)
1254 qemu_mallocz(sizeof(struct s3c_timers_state_s));
1255
1256 s->base = base;
1257 s->dma = dma;
1258
1259 s3c_timers_reset(s);
1260
1261 for (i = 0; i < 5; i ++) {
1262 s->timer[i].t = qemu_new_timer(vm_clock,
1263 s3c_timers_tick, &s->timer[i]);
1264 s->timer[i].s = s;
1265 s->timer[i].n = i;
1266 s->timer[i].cmp_cb = 0;
1267 s->timer[i].irq = pic[i];
1268 }
1269
1270 iomemtype = cpu_register_io_memory(0, s3c_timers_readfn,
1271 s3c_timers_writefn, s);
1272 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
1273
1274 register_savevm("s3c24xx_timers", 0, 0,
1275 s3c_timers_save, s3c_timers_load, s);
1276
1277 return s;
1278 }
1279
1280 void s3c_timers_cmp_handler_set(void *opaque, int line,
1281 gpio_handler_t handler, void *cmp_opaque)
1282 {
1283 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *) opaque;
1284 if (line > 4 || line < 0) {
1285 printf("%s: Bad timer number %i.\n", __FUNCTION__, line);
1286 exit(-1);
1287 }
1288 s->timer[line].cmp_cb = handler;
1289 s->timer[line].cmp_opaque = cmp_opaque;
1290 }
1291
1292 /* UART */
1293 struct s3c_uart_state_s {
1294 target_phys_addr_t base;
1295 qemu_irq *irq;
1296 qemu_irq *dma;
1297 uint8_t data;
1298 uint8_t rxfifo[16];
1299 int rxstart;
1300 int rxlen;
1301 #define UART_MAX_CHR 4
1302 int chr_num;
1303 CharDriverState *chr[UART_MAX_CHR];
1304
1305 uint8_t lcontrol;
1306 uint8_t fcontrol;
1307 uint8_t mcontrol;
1308 uint16_t control;
1309 uint16_t brdiv;
1310 uint8_t errstat;
1311 };
1312
1313 static void s3c_uart_reset(struct s3c_uart_state_s *s)
1314 {
1315 s->lcontrol = 0x00;
1316 s->fcontrol = 0x00;
1317 s->mcontrol = 0x00;
1318 s->control = 0x0000;
1319 s->errstat = 0;
1320
1321 s->rxstart = 0;
1322 s->rxlen = 0;
1323 }
1324
1325 static void s3c_uart_err(struct s3c_uart_state_s *s, int err)
1326 {
1327 s->errstat |= err;
1328 if (s->control & (1 << 6))
1329 qemu_irq_raise(s->irq[2]);
1330 }
1331
1332 inline static void s3c_uart_full(struct s3c_uart_state_s *s, int pulse)
1333 {
1334 if (s->fcontrol & 1) /* FIFOEnable */
1335 if (s->rxlen < (((s->fcontrol >> 4) & 3) + 1) * 4) {
1336 if (((s->control >> 0) & 3) != 1 || /* ReceiveMode */
1337 !s->rxlen)
1338 return;
1339 if (!(s->control & (1 << 7))) /* RxTimeOutEnable */
1340 return;
1341 /* When the Rx FIFO trigger level is not reached, the interrupt
1342 * is generated anyway, just after a small timeout instead of
1343 * immediately. */
1344 }
1345
1346 switch ((s->control >> 0) & 3) { /* ReceiveMode */
1347 case 1:
1348 if ((s->control & (1 << 8)) || pulse) /* RxInterruptType */
1349 qemu_irq_raise(s->irq[0]);
1350 break;
1351 case 2:
1352 case 3:
1353 qemu_irq_raise(s->dma[0]);
1354 break;
1355 }
1356 }
1357
1358 inline static void s3c_uart_empty(struct s3c_uart_state_s *s, int pulse)
1359 {
1360 switch ((s->control >> 2) & 3) { /* TransmitMode */
1361 case 1:
1362 if ((s->control & (1 << 9)) || pulse) /* TxInterruptType */
1363 qemu_irq_raise(s->irq[1]);
1364 break;
1365 case 2:
1366 case 3:
1367 qemu_irq_raise(s->dma[0]);
1368 break;
1369 }
1370 }
1371
1372 inline static void s3c_uart_update(struct s3c_uart_state_s *s)
1373 {
1374 s3c_uart_empty(s, 0);
1375 s3c_uart_full(s, 0);
1376 }
1377
1378 static void s3c_uart_params_update(struct s3c_uart_state_s *s)
1379 {
1380 QEMUSerialSetParams ssp;
1381 int i;
1382 if (!s->chr)
1383 return;
1384
1385 /* XXX Calculate PCLK frequency from clock manager registers */
1386 ssp.speed = (S3C_PCLK_FREQ >> 4) / (s->brdiv + 1);
1387
1388 switch ((s->lcontrol >> 3) & 7) {
1389 case 4:
1390 case 6:
1391 ssp.parity = 'O';
1392 break;
1393 case 5:
1394 case 7:
1395 ssp.parity = 'E';
1396 break;
1397 default:
1398 ssp.parity = 'N';
1399 }
1400
1401 ssp.data_bits = 5 + (s->lcontrol & 3);
1402
1403 ssp.stop_bits = (s->lcontrol & (1 << 2)) ? 2 : 1;
1404
1405 for (i = 0; i < s->chr_num; i ++)
1406 qemu_chr_ioctl(s->chr[i], CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
1407 }
1408
1409 static int s3c_uart_is_empty(void *opaque)
1410 {
1411 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1412 if (s->fcontrol & 1) /* FIFOEnable */
1413 return 16 - s->rxlen;
1414 else
1415 return 1 - s->rxlen;
1416 }
1417
1418 static void s3c_uart_rx(void *opaque, const uint8_t *buf, int size)
1419 {
1420 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1421 int left;
1422 if (s->fcontrol & 1) { /* FIFOEnable */
1423 if (s->rxlen + size > 16) {
1424 size = 16 - s->rxlen;
1425 s3c_uart_err(s, 1);
1426 }
1427
1428 left = 16 - ((s->rxstart + s->rxlen) & 15);
1429 if (size > left) {
1430 memcpy(s->rxfifo + ((s->rxstart + s->rxlen) & 15), buf, left);
1431 memcpy(s->rxfifo, buf + left, size - left);
1432 } else
1433 memcpy(s->rxfifo + ((s->rxstart + s->rxlen) & 15), buf, size);
1434 s->rxlen += size;
1435 } else {
1436 if (s->rxlen + size > 1)
1437 s3c_uart_err(s, 1);
1438 s->rxlen = 1;
1439 s->data = buf[0];
1440 }
1441 s3c_uart_full(s, 1);
1442 }
1443
1444 /* S3C2410 UART doesn't seem to understand break conditions. */
1445 static void s3c_uart_event(void *opaque, int event)
1446 {
1447 }
1448
1449 #define S3C_ULCON 0x00 /* UART Line Control register */
1450 #define S3C_UCON 0x04 /* UART Control register */
1451 #define S3C_UFCON 0x08 /* UART FIFO Control register */
1452 #define S3C_UMCON 0x0c /* UART Modem Control register */
1453 #define S3C_UTRSTAT 0x10 /* UART Tx/Rx Status register */
1454 #define S3C_UERSTAT 0x14 /* UART Error Status register */
1455 #define S3C_UFSTAT 0x18 /* UART FIFO Status register */
1456 #define S3C_UMSTAT 0x1c /* UART Modem Status register */
1457 #define S3C_UTXH 0x20 /* UART Transmit Buffer register */
1458 #define S3C_URXH 0x24 /* UART Receive Buffer register */
1459 #define S3C_UBRDIV 0x28 /* UART Baud Rate Divisor register */
1460
1461 static uint32_t s3c_uart_read(void *opaque, target_phys_addr_t addr)
1462 {
1463 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1464 uint8_t ret;
1465 addr -= s->base;
1466
1467 switch (addr) {
1468 case S3C_ULCON:
1469 return s->lcontrol;
1470 case S3C_UCON:
1471 return s->control;
1472 case S3C_UFCON:
1473 return s->fcontrol;
1474 case S3C_UMCON:
1475 return s->mcontrol;
1476 case S3C_UTRSTAT:
1477 return 6 | !!s->rxlen;
1478 case S3C_UERSTAT:
1479 /* XXX: UERSTAT[3] is Reserved but Linux thinks it is BREAK */
1480 ret = s->errstat;
1481 s->errstat = 0;
1482 s3c_uart_update(s);
1483 return ret;
1484 case S3C_UFSTAT:
1485 s3c_uart_update(s);
1486 return s->rxlen ? s->rxlen | (1 << 8) : 0;
1487 case S3C_UMSTAT:
1488 s3c_uart_update(s);
1489 return 0x11;
1490 case S3C_URXH:
1491 s3c_uart_update(s);
1492 if (s->rxlen) {
1493 s->rxlen --;
1494 if (s->fcontrol & 1) { /* FIFOEnable */
1495 ret = s->rxfifo[s->rxstart ++];
1496 s->rxstart &= 15;
1497 } else
1498 ret = s->data;
1499 return ret;
1500 }
1501 return 0;
1502 case S3C_UBRDIV:
1503 return s->brdiv;
1504 default:
1505 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1506 break;
1507 }
1508 return 0;
1509 }
1510
1511 static void s3c_uart_write(void *opaque, target_phys_addr_t addr,
1512 uint32_t value)
1513 {
1514 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1515 uint8_t ch;
1516 int i, afc;
1517 addr -= s->base;
1518
1519 switch (addr) {
1520 case S3C_ULCON:
1521 if ((s->lcontrol ^ value) & (1 << 6))
1522 printf("%s: UART Infra-red mode %s\n", __FUNCTION__,
1523 (value & (1 << 6)) ? "on" : "off");
1524 s->lcontrol = value;
1525 s3c_uart_params_update(s);
1526 s3c_uart_update(s);
1527 break;
1528 case S3C_UCON:
1529 /* XXX: UCON[4] is Reserved but Linux thinks it is BREAK */
1530 if ((s->control ^ value) & (1 << 5))
1531 printf("%s: UART loopback test mode %s\n", __FUNCTION__,
1532 (value & (1 << 5)) ? "on" : "off");
1533 s->control = value & 0x7ef;
1534 s3c_uart_update(s);
1535 break;
1536 case S3C_UFCON:
1537 if (value & (1 << 1)) /* RxReset */
1538 s->rxlen = 0;
1539 s->fcontrol = value & 0xf1;
1540 s3c_uart_update(s);
1541 break;
1542 case S3C_UMCON:
1543 #ifdef CONFIG_S3C_MODEM /* not handled, openmoko modem.c not imported */
1544 if ((s->mcontrol ^ value) & (1 << 4)) {
1545 afc = (value >> 4) & 1;
1546 for (i = 0; i < s->chr_num; i ++)
1547 qemu_chr_ioctl(s->chr[i], CHR_IOCTL_MODEM_HANDSHAKE, &afc);
1548 }
1549 #endif
1550 s->mcontrol = value & 0x11;
1551 s3c_uart_update(s);
1552 break;
1553 case S3C_UTXH:
1554 ch = value & 0xff;
1555 for (i = 0; i < s->chr_num; i ++)
1556 qemu_chr_write(s->chr[i], &ch, 1);
1557 s3c_uart_empty(s, 1);
1558 s3c_uart_update(s);
1559 break;
1560 case S3C_UBRDIV:
1561 s->brdiv = value & 0xffff;
1562 s3c_uart_params_update(s);
1563 s3c_uart_update(s);
1564 break;
1565 default:
1566 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1567 }
1568 }
1569
1570 static CPUReadMemoryFunc *s3c_uart_readfn[] = {
1571 s3c_uart_read,
1572 s3c_uart_read,
1573 s3c_uart_read,
1574 };
1575
1576 static CPUWriteMemoryFunc *s3c_uart_writefn[] = {
1577 s3c_uart_write,
1578 s3c_uart_write,
1579 s3c_uart_write,
1580 };
1581
1582 static void s3c_uart_save(QEMUFile *f, void *opaque)
1583 {
1584 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1585 qemu_put_8s(f, &s->data);
1586 qemu_put_buffer(f, s->rxfifo, sizeof(s->rxfifo));
1587 qemu_put_be32(f, s->rxstart);
1588 qemu_put_be32(f, s->rxlen);
1589 qemu_put_8s(f, &s->lcontrol);
1590 qemu_put_8s(f, &s->fcontrol);
1591 qemu_put_8s(f, &s->mcontrol);
1592 qemu_put_be16s(f, &s->control);
1593 qemu_put_be16s(f, &s->brdiv);
1594 qemu_put_8s(f, &s->errstat);
1595 }
1596
1597 static int s3c_uart_load(QEMUFile *f, void *opaque, int version_id)
1598 {
1599 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1600 qemu_get_8s(f, &s->data);
1601 qemu_get_buffer(f, s->rxfifo, sizeof(s->rxfifo));
1602 s->rxstart = qemu_get_be32(f);
1603 s->rxlen = qemu_get_be32(f);
1604 qemu_get_8s(f, &s->lcontrol);
1605 qemu_get_8s(f, &s->fcontrol);
1606 qemu_get_8s(f, &s->mcontrol);
1607 qemu_get_be16s(f, &s->control);
1608 qemu_get_be16s(f, &s->brdiv);
1609 qemu_get_8s(f, &s->errstat);
1610
1611 return 0;
1612 }
1613
1614 struct s3c_uart_state_s *s3c_uart_init(target_phys_addr_t base,
1615 qemu_irq *irqs, qemu_irq *dma)
1616 {
1617 int iomemtype;
1618 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *)
1619 qemu_mallocz(sizeof(struct s3c_uart_state_s));
1620
1621 s->base = base;
1622 s->irq = irqs;
1623 s->dma = dma;
1624
1625 s3c_uart_reset(s);
1626
1627 iomemtype = cpu_register_io_memory(0, s3c_uart_readfn,
1628 s3c_uart_writefn, s);
1629 cpu_register_physical_memory(s->base, 0xfff, iomemtype);
1630
1631 register_savevm("s3c24xx_uart", base, 0, s3c_uart_save, s3c_uart_load, s);
1632
1633 return s;
1634 }
1635
1636 void s3c_uart_attach(struct s3c_uart_state_s *s, CharDriverState *chr)
1637 {
1638 if (s->chr_num >= UART_MAX_CHR)
1639 cpu_abort(cpu_single_env, "%s: Too many devices\n", __FUNCTION__);
1640 s->chr[s->chr_num ++] = chr;
1641
1642 qemu_chr_add_handlers(chr, s3c_uart_is_empty,
1643 s3c_uart_rx, s3c_uart_event, s);
1644 }
1645
1646 /* ADC & Touchscreen interface */
1647 struct s3c_adc_state_s {
1648 target_phys_addr_t base;
1649 qemu_irq irq;
1650 qemu_irq tcirq;
1651 QEMUTimer *convt;
1652 QEMUTimer *tst;
1653 int x;
1654 int y;
1655 int down;
1656 int enable;
1657 int input[8];
1658 int in_idx;
1659 int noise;
1660 int scale[6];
1661
1662 uint16_t control;
1663 uint16_t ts;
1664 uint16_t delay;
1665 int16_t xdata;
1666 int16_t ydata;
1667 };
1668
1669 static void s3c_adc_reset(struct s3c_adc_state_s *s)
1670 {
1671 s->down = 0;
1672 s->control = 0x3fc4;
1673 s->ts = 0x58;
1674 s->delay = 0xff;
1675 s->enable = 1;
1676 }
1677
1678 static void s3c_adc_start(struct s3c_adc_state_s *s)
1679 {
1680 if (!s->enable || (s->ts & 7) == 0)
1681 return;
1682 s->control &= ~(1 << 15);
1683 s->in_idx = (s->control >> 3) & 7;
1684 qemu_mod_timer(s->convt, qemu_get_clock(vm_clock) + (ticks_per_sec >> 5));
1685 }
1686
1687 static void s3c_adc_done(void *opaque)
1688 {
1689 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1690 s->xdata = s->input[s->in_idx] & 0x3ff;
1691 s->control |= 1 << 15;
1692 qemu_irq_raise(s->irq);
1693 }
1694
1695 static void s3c_adc_tick(void *opaque)
1696 {
1697 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1698 int sx, sy;
1699
1700 if (s->down) {
1701 if ((s->ts & 3) == 3 && s->enable)
1702 qemu_irq_raise(s->tcirq);
1703 else if (s->enable && ((s->ts & (1 << 2)) || (s->ts & 3))) {
1704 sx = s->x * s->scale[0] + s->y * s->scale[1] + s->scale[2];
1705 sy = s->x * s->scale[3] + s->y * s->scale[4] + s->scale[5];
1706 s->xdata = ((sx >> 13) & 0xfff) | (1 << 14) | ((s->ts & 3) << 12);
1707 s->ydata = ((sy >> 13) & 0xfff) | (1 << 14) | ((s->ts & 3) << 12);
1708 s->xdata ^= s->noise >> 1;
1709 s->ydata ^= s->noise >> 2;
1710 qemu_irq_raise(s->irq);
1711 s->noise ++;
1712 s->noise &= 7;
1713 }
1714 qemu_mod_timer(s->tst, qemu_get_clock(vm_clock) +
1715 (ticks_per_sec >> 5));
1716 }
1717 }
1718
1719 static void s3c_adc_event(void *opaque,
1720 int x, int y, int z, int buttons_state)
1721 {
1722 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1723 s->down = !!buttons_state;
1724 s->x = x;
1725 s->y = y;
1726 s3c_adc_tick(s);
1727 }
1728
1729 #define S3C_ADCCON 0x00 /* ADC Control register */
1730 #define S3C_ADCTSC 0x04 /* ADC Touchscreen Control register */
1731 #define S3C_ADCDLY 0x08 /* ADC Start or Interval Delay register */
1732 #define S3C_ADCDAT0 0x0c /* ADC Conversion Data register 0 */
1733 #define S3C_ADCDAT1 0x10 /* ADC Conversion Data register 1 */
1734
1735 static uint32_t s3c_adc_read(void *opaque, target_phys_addr_t addr)
1736 {
1737 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1738 addr -= s->base;
1739
1740 switch (addr) {
1741 case S3C_ADCCON:
1742 return s->control;
1743 case S3C_ADCTSC:
1744 return s->ts;
1745 case S3C_ADCDLY:
1746 return s->delay;
1747 case S3C_ADCDAT0:
1748 if (s->control & 2)
1749 s3c_adc_start(s);
1750 return ((!s->down) << 15) | s->xdata;
1751 case S3C_ADCDAT1:
1752 return ((!s->down) << 15) | s->ydata;
1753 default:
1754 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1755 break;
1756 }
1757 return 0;
1758 }
1759
1760 static void s3c_adc_write(void *opaque, target_phys_addr_t addr,
1761 uint32_t value)
1762 {
1763 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1764 addr -= s->base;
1765
1766 switch (addr) {
1767 case S3C_ADCCON:
1768 s->control = (s->control & 0x8000) | (value & 0x7ffe);
1769 s->enable = !(value & 4);
1770 if ((value & 1) && !(value & 2))
1771 s3c_adc_start(s);
1772 if (!s->enable)
1773 qemu_del_timer(s->convt);
1774 s3c_adc_tick(s);
1775 break;
1776
1777 case S3C_ADCTSC:
1778 s->ts = value & 0xff;
1779 break;
1780
1781 case S3C_ADCDLY:
1782 s->delay = value & 0xffff;
1783
1784 default:
1785 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1786 }
1787 }
1788
1789 static CPUReadMemoryFunc *s3c_adc_readfn[] = {
1790 s3c_adc_read,
1791 s3c_adc_read,
1792 s3c_adc_read,
1793 };
1794
1795 static CPUWriteMemoryFunc *s3c_adc_writefn[] = {
1796 s3c_adc_write,
1797 s3c_adc_write,
1798 s3c_adc_write,
1799 };
1800
1801 static void s3c_adc_save(QEMUFile *f, void *opaque)
1802 {
1803 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1804 int i;
1805 qemu_put_be32(f, s->enable);
1806 for (i = 0; i < 8; i ++)
1807 qemu_put_be32(f, s->input[i]);
1808 qemu_put_be32(f, s->in_idx);
1809 qemu_put_be32(f, s->noise);
1810
1811 qemu_put_be16s(f, &s->control);
1812 qemu_put_be16s(f, &s->ts);
1813 qemu_put_be16s(f, &s->delay);
1814 qemu_put_be16s(f, &s->xdata);
1815 qemu_put_be16s(f, &s->ydata);
1816 }
1817
1818 static int s3c_adc_load(QEMUFile *f, void *opaque, int version_id)
1819 {
1820 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1821 int i;
1822 s->enable = qemu_get_be32(f);
1823 for (i = 0; i < 8; i ++)
1824 s->input[i] = qemu_get_be32(f);
1825 s->in_idx = qemu_get_be32(f);
1826 s->noise = qemu_get_be32(f);
1827
1828 qemu_get_be16s(f, &s->control);
1829 qemu_get_be16s(f, &s->ts);
1830 qemu_get_be16s(f, &s->delay);
1831 qemu_get_be16s(f, &s->xdata);
1832 qemu_get_be16s(f, &s->ydata);
1833
1834 if (s->enable && (s->ts & 7) && !(s->control & (1 << 15)))
1835 s3c_adc_start(s);
1836
1837 return 0;
1838 }
1839
1840 struct s3c_adc_state_s *s3c_adc_init(target_phys_addr_t base, qemu_irq irq,
1841 qemu_irq tcirq)
1842 {
1843 int iomemtype;
1844 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *)
1845 qemu_mallocz(sizeof(struct s3c_adc_state_s));
1846
1847 s->base = base;
1848 s->irq = irq;
1849 s->tcirq = tcirq;
1850 s->convt = qemu_new_timer(vm_clock, s3c_adc_done, s);
1851 s->tst = qemu_new_timer(vm_clock, s3c_adc_tick, s);
1852
1853 s3c_adc_reset(s);
1854
1855 iomemtype = cpu_register_io_memory(0, s3c_adc_readfn,
1856 s3c_adc_writefn, s);
1857 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
1858
1859 /* We want absolute coordinates */
1860 qemu_add_mouse_event_handler(s3c_adc_event, s, 1,
1861 "QEMU S3C2410-driven Touchscreen");
1862
1863 register_savevm("s3c24xx_adc", 0, 0, s3c_adc_save, s3c_adc_load, s);
1864
1865 return s;
1866 }
1867
1868 void s3c_adc_setscale(struct s3c_adc_state_s *adc, const int m[])
1869 {
1870 memcpy(adc->scale, m, 6 * sizeof(int));
1871 }
1872
1873 /* IIC-bus serial interface */
1874 struct s3c_i2c_state_s {
1875 i2c_slave slave;
1876 i2c_bus *bus;
1877 target_phys_addr_t base;
1878 qemu_irq irq;
1879
1880 uint8_t control;
1881 uint8_t status;
1882 uint8_t data;
1883 uint8_t addy;
1884 int busy;
1885 int newstart;
1886 };
1887
1888 static void s3c_i2c_irq(struct s3c_i2c_state_s *s)
1889 {
1890 s->control |= 1 << 4;
1891 if (s->control & (1 << 5))
1892 qemu_irq_raise(s->irq);
1893 }
1894
1895 static void s3c_i2c_reset(struct s3c_i2c_state_s *s)
1896 {
1897 s->control = 0x00;
1898 s->status = 0x00;
1899 s->busy = 0;
1900 s->newstart = 0;
1901 }
1902
1903 static void s3c_i2c_event(i2c_slave *i2c, enum i2c_event event)
1904 {
1905 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) i2c;
1906 if (!(s->status & (1 << 4)))
1907 return;
1908
1909 switch (event) {
1910 case I2C_START_RECV:
1911 case I2C_START_SEND:
1912 s->status |= 1 << 2;
1913 s3c_i2c_irq(s);
1914 break;
1915 case I2C_FINISH:
1916 s->status &= ~6;
1917 break;
1918 case I2C_NACK:
1919 s->status |= 1 << 0;
1920 break;
1921 default:
1922 break;
1923 }
1924 }
1925
1926 static int s3c_i2c_tx(i2c_slave *i2c, uint8_t data)
1927 {
1928 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) i2c;
1929 if (!(s->status & (1 << 4)))
1930 return 1;
1931
1932 if ((s->status >> 6) == 0)
1933 s->data = data; /* TODO */
1934 s->status &= ~(1 << 0);
1935 s3c_i2c_irq(s);
1936
1937 return !(s->control & (1 << 7));
1938 }
1939
1940 static int s3c_i2c_rx(i2c_slave *i2c)
1941 {
1942 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) i2c;
1943 if (!(s->status & (1 << 4)))
1944 return 1;
1945
1946 if ((s->status >> 6) == 1) {
1947 s->status &= ~(1 << 0);
1948 s3c_i2c_irq(s);
1949 return s->data;
1950 }
1951
1952 return 0x00;
1953 }
1954
1955 static void s3c_master_work(void *opaque)
1956 {
1957 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) opaque;
1958 int start = 0, stop = 0, ack = 1;
1959 if (s->control & (1 << 4)) /* Interrupt pending */
1960 return;
1961 if ((s->status & 0x90) != 0x90) /* Master */
1962 return;
1963 stop = ~s->status & (1 << 5);
1964 if (s->newstart && s->status & (1 << 5)) { /* START */
1965 s->busy = 1;
1966 start = 1;
1967 }
1968 s->newstart = 0;
1969 if (!s->busy)
1970 return;
1971
1972 if (start)
1973 ack = !i2c_start_transfer(s->bus, s->data >> 1, (~s->status >> 6) & 1);
1974 else if (stop)
1975 i2c_end_transfer(s->bus);
1976 else if (s->status & (1 << 6))
1977 ack = !i2c_send(s->bus, s->data);
1978 else {
1979 s->data = i2c_recv(s->bus);
1980
1981 if (!(s->control & (1 << 7))) /* ACK */
1982 i2c_nack(s->bus);
1983 }
1984
1985 if (!(s->status & (1 << 5))) {
1986 s->busy = 0;
1987 return;
1988 }
1989 s->status &= ~1;
1990 s->status |= !ack;
1991 if (!ack)
1992 s->busy = 0;
1993 s3c_i2c_irq(s);
1994 }
1995
1996 #define S3C_IICCON 0x00 /* IIC-Bus Control register */
1997 #define S3C_IICSTAT 0x04 /* IIC-Bus Control / Status register */
1998 #define S3C_IICADD 0x08 /* IIC-Bus Address register */
1999 #define S3C_IICDS 0x0c /* IIC-Bus Tx / Rx Data Shift register */
2000
2001 static uint32_t s3c_i2c_read(void *opaque, target_phys_addr_t addr)
2002 {
2003 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) opaque;
2004 addr -= s->base;
2005
2006 switch (addr) {
2007 case S3C_IICCON:
2008 return s->control;
2009 case S3C_IICSTAT:
2010 return s->status & ~(1 << 5); /* Busy signal */
2011 case S3C_IICADD:
2012 return s->addy;
2013 case S3C_IICDS:
2014 return s->data;
2015 default:
2016 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2017 break;
2018 }
2019 return 0;
2020 }
2021
2022 static void s3c_i2c_write(void *opaque, target_phys_addr_t addr,
2023 uint32_t value)
2024 {
2025 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) opaque;
2026 addr -= s->base;
2027
2028 switch (addr) {
2029 case S3C_IICCON:
2030 s->control = (s->control | 0xef) & value;
2031 if (s->busy)
2032 s3c_master_work(s);
2033 break;
2034
2035 case S3C_IICSTAT:
2036 s->status &= 0x0f;
2037 s->status |= value & 0xf0;
2038 if (s->status & (1 << 5))
2039 s->newstart = 1;
2040 s3c_master_work(s);
2041 break;
2042
2043 case S3C_IICADD:
2044 s->addy = value & 0x7f;
2045 i2c_set_slave_address(&s->slave, s->addy);
2046 break;
2047
2048 case S3C_IICDS:
2049 s->data = value & 0xff;
2050 break;
2051
2052 default:
2053 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2054 }
2055 }
2056
2057 static CPUReadMemoryFunc *s3c_i2c_readfn[] = {
2058 s3c_i2c_read,
2059 s3c_i2c_read,
2060 s3c_i2c_read,
2061 };
2062
2063 static CPUWriteMemoryFunc *s3c_i2c_writefn[] = {
2064 s3c_i2c_write,
2065 s3c_i2c_write,
2066 s3c_i2c_write,
2067 };
2068
2069 static void s3c_i2c_save(QEMUFile *f, void *opaque)
2070 {
2071 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) opaque;
2072 qemu_put_8s(f, &s->control);
2073 qemu_put_8s(f, &s->status);
2074 qemu_put_8s(f, &s->data);
2075 qemu_put_8s(f, &s->addy);
2076
2077 qemu_put_be32(f, s->busy);
2078 qemu_put_be32(f, s->newstart);
2079
2080 // i2c_bus_save(f, s->bus);
2081 i2c_slave_save(f, &s->slave);
2082 }
2083
2084 static int s3c_i2c_load(QEMUFile *f, void *opaque, int version_id)
2085 {
2086 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) opaque;
2087 qemu_get_8s(f, &s->control);
2088 qemu_get_8s(f, &s->status);
2089 qemu_get_8s(f, &s->data);
2090 qemu_get_8s(f, &s->addy);
2091
2092 s->busy = qemu_get_be32(f);
2093 s->newstart = qemu_get_be32(f);
2094
2095 // i2c_bus_load(f, s->bus);
2096 i2c_slave_load(f, &s->slave);
2097 return 0;
2098 }
2099
2100 struct s3c_i2c_state_s *s3c_i2c_init(target_phys_addr_t base, qemu_irq irq)
2101 {
2102 int iomemtype;
2103 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *)
2104 qemu_mallocz(sizeof(struct s3c_i2c_state_s));
2105
2106 s->base = base;
2107 s->irq = irq;
2108 s->slave.event = s3c_i2c_event;
2109 s->slave.send = s3c_i2c_tx;
2110 s->slave.recv = s3c_i2c_rx;
2111 s->bus = i2c_init_bus();
2112
2113 s3c_i2c_reset(s);
2114
2115 iomemtype = cpu_register_io_memory(0, s3c_i2c_readfn,
2116 s3c_i2c_writefn, s);
2117 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
2118
2119 register_savevm("s3c24xx_i2c", 0, 0, s3c_i2c_save, s3c_i2c_load, s);
2120
2121 return s;
2122 }
2123
2124 i2c_bus *s3c_i2c_bus(struct s3c_i2c_state_s *s)
2125 {
2126 return s->bus;
2127 }
2128
2129 /* Serial Peripheral Interface */
2130 struct s3c_spi_state_s {
2131 target_phys_addr_t base;
2132
2133 struct {
2134 qemu_irq irq;
2135 qemu_irq drq;
2136 qemu_irq miso;
2137
2138 uint8_t control;
2139 uint8_t pin;
2140 uint8_t pre;
2141
2142 int cs_pin;
2143 int clk_pin;
2144 int mosi_pin;
2145 uint8_t txbuf;
2146 uint8_t rxbuf;
2147 int bit;
2148 } chan[2];
2149
2150 uint8_t (*txrx[2])(void *opaque, uint8_t value);
2151 uint8_t (*btxrx[2])(void *opaque, uint8_t value);
2152 void *opaque[2];
2153 };
2154
2155 static void s3c_spi_update(struct s3c_spi_state_s *s)
2156 {
2157 int i;
2158 for (i = 0; i < 2; i ++) {
2159 switch ((s->chan[i].control >> 5) & 3) { /* SMOD */
2160 case 1:
2161 qemu_irq_raise(s->chan[i].irq);
2162 break;
2163 case 2:
2164 qemu_irq_raise(s->chan[i].drq);
2165 break;
2166 }
2167 }
2168 }
2169
2170 static void s3c_spi_reset(struct s3c_spi_state_s *s)
2171 {
2172 memset(s->chan, 0, sizeof(s->chan));
2173 s->chan[0].pin = 0x02;
2174 s->chan[1].pin = 0x02;
2175 s3c_spi_update(s);
2176 }
2177
2178 #define S3C_SPCON0 0x00 /* SPI channel 0 control register */
2179 #define S3C_SPSTA0 0x04 /* SPI channel 0 status register */
2180 #define S3C_SPPIN0 0x08 /* SPI channel 0 pin control register */
2181 #define S3C_SPPRE0 0x0c /* SPI channel 0 baudrate prescaler register */
2182 #define S3C_SPTDAT0 0x10 /* SPI channel 0 Tx data register */
2183 #define S3C_SPRDAT0 0x14 /* SPI channel 0 Rx data register */
2184 #define S3C_SPCON1 0x20 /* SPI channel 1 control register */
2185 #define S3C_SPSTA1 0x24 /* SPI channel 1 status register */
2186 #define S3C_SPPIN1 0x28 /* SPI channel 1 pin control register */
2187 #define S3C_SPPRE1 0x2c /* SPI channel 1 baudrate prescaler register */
2188 #define S3C_SPTDAT1 0x30 /* SPI channel 1 Tx data register */
2189 #define S3C_SPRDAT1 0x34 /* SPI channel 1 Rx data register */
2190
2191 static uint32_t s3c_spi_read(void *opaque, target_phys_addr_t addr)
2192 {
2193 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2194 int ch;
2195 addr -= s->base;
2196 ch = addr >> 5;
2197
2198 switch (addr) {
2199 case S3C_SPCON0:
2200 case S3C_SPCON1:
2201 return s->chan[ch].control;
2202
2203 case S3C_SPSTA0:
2204 case S3C_SPSTA1:
2205 return 0x01;
2206
2207 case S3C_SPPIN0:
2208 case S3C_SPPIN1:
2209 return s->chan[ch].pin;
2210
2211 case S3C_SPPRE0:
2212 case S3C_SPPRE1:
2213 return s->chan[ch].pre;
2214
2215 case S3C_SPTDAT0:
2216 case S3C_SPTDAT1:
2217 return s->chan[ch + 2].txbuf;
2218
2219 case S3C_SPRDAT0:
2220 case S3C_SPRDAT1:
2221 if (s->txrx[ch] && (s->chan[ch].control & 0x19) == 0x19)
2222 s->chan[ch].rxbuf = s->txrx[ch](s->opaque[ch], 'Q');
2223 s3c_spi_update(s);
2224 return s->chan[ch].rxbuf;
2225
2226 default:
2227 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2228 break;
2229 }
2230 return 0;
2231 }
2232
2233 static void s3c_spi_write(void *opaque, target_phys_addr_t addr,
2234 uint32_t value)
2235 {
2236 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2237 int ch;
2238 addr -= s->base;
2239 ch = addr >> 5;
2240
2241 switch (addr) {
2242 case S3C_SPCON0:
2243 case S3C_SPCON1:
2244 s->chan[ch].control = value & 0x7f;
2245 s3c_spi_update(s);
2246 break;
2247
2248 case S3C_SPPIN0:
2249 case S3C_SPPIN1:
2250 s->chan[ch].pin = value & 0x07;
2251 break;
2252
2253 case S3C_SPPRE0:
2254 case S3C_SPPRE1:
2255 s->chan[ch].pre = value & 0xff;
2256 break;
2257
2258 case S3C_SPTDAT0:
2259 case S3C_SPTDAT1:
2260 s->chan[ch].txbuf = value & 0xff;
2261 if (s->txrx[ch] && (s->chan[ch].control & 0x19) == 0x18)
2262 s->chan[ch].rxbuf = s->txrx[ch](s->opaque[ch], value & 0xff);
2263 s3c_spi_update(s);
2264 break;
2265
2266 default:
2267 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2268 }
2269 }
2270
2271 static CPUReadMemoryFunc *s3c_spi_readfn[] = {
2272 s3c_spi_read,
2273 s3c_spi_read,
2274 s3c_spi_read,
2275 };
2276
2277 static CPUWriteMemoryFunc *s3c_spi_writefn[] = {
2278 s3c_spi_write,
2279 s3c_spi_write,
2280 s3c_spi_write,
2281 };
2282
2283 static void s3c_spi_save(QEMUFile *f, void *opaque)
2284 {
2285 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2286 int i;
2287 for (i = 0; i < 2; i ++) {
2288 qemu_put_8s(f, &s->chan[i].control);
2289 qemu_put_8s(f, &s->chan[i].pin);
2290 qemu_put_8s(f, &s->chan[i].pre);
2291
2292 qemu_put_8s(f, &s->chan[i].txbuf);
2293 qemu_put_8s(f, &s->chan[i].rxbuf);
2294 qemu_put_be32(f, s->chan[i].cs_pin);
2295 qemu_put_be32(f, s->chan[i].clk_pin);
2296 qemu_put_be32(f, s->chan[i].mosi_pin);
2297 qemu_put_be32(f, s->chan[i].bit);
2298 }
2299 }
2300
2301 static int s3c_spi_load(QEMUFile *f, void *opaque, int version_id)
2302 {
2303 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2304 int i;
2305 for (i = 0; i < 2; i ++) {
2306 qemu_get_8s(f, &s->chan[i].control);
2307 qemu_get_8s(f, &s->chan[i].pin);
2308 qemu_get_8s(f, &s->chan[i].pre);
2309
2310 qemu_get_8s(f, &s->chan[i].txbuf);
2311 qemu_get_8s(f, &s->chan[i].rxbuf);
2312 s->chan[i].cs_pin = qemu_get_be32(f);
2313 s->chan[i].clk_pin = qemu_get_be32(f);
2314 s->chan[i].mosi_pin = qemu_get_be32(f);
2315 s->chan[i].bit = qemu_get_be32(f);
2316 }
2317
2318 return 0;
2319 }
2320
2321 static void s3c_spi_bitbang_cs(void *opaque, int line, int level)
2322 {
2323 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2324 int ch = line;
2325 if (s->chan[ch].cs_pin || level) {
2326 if (s->chan[ch].bit && s->txrx[ch] && !s->btxrx[ch]) {
2327 s->chan[ch].txbuf <<= 8 - s->chan[ch].bit;
2328 s->chan[ch].rxbuf = s->txrx[ch](s->opaque[ch], s->chan[ch].txbuf);
2329 }
2330 } else if (!s->chan[ch].cs_pin || !level)
2331 s->chan[ch].bit = 0;
2332
2333 /* SSn is active low. */
2334 s->chan[ch].cs_pin = !level;
2335 }
2336
2337 static void s3c_spi_bitbang_clk(void *opaque, int line, int level)
2338 {
2339 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2340 int ch = line;
2341 if (!s->chan[ch].cs_pin)
2342 goto done;
2343
2344 /* Detect CLK rising edge */
2345 if (s->chan[ch].clk_pin || !level)
2346 goto done;
2347
2348 if (s->btxrx[ch]) {
2349 qemu_set_irq(s->chan[ch].miso,
2350 s->btxrx[ch](s->opaque[ch], s->chan[ch].mosi_pin));
2351 goto done;
2352 }
2353
2354 s->chan[ch].txbuf <<= 1;
2355 s->chan[ch].txbuf |= s->chan[ch].mosi_pin;
2356
2357 qemu_set_irq(s->chan[ch].miso, (s->chan[ch].rxbuf >> 7) & 1);
2358 s->chan[ch].rxbuf <<= 1;
2359
2360 if (++ s->chan[ch].bit == 8) {
2361 if (s->txrx[ch])
2362 s->chan[ch].rxbuf = s->txrx[ch](s->opaque[ch], s->chan[ch].txbuf);
2363 s->chan[ch].bit = 0;
2364 }
2365
2366 done:
2367 s->chan[ch].clk_pin = level;
2368 }
2369
2370 static void s3c_spi_bitbang_mosi(void *opaque, int line, int level)
2371 {
2372 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2373 int ch = line;
2374 s->chan[ch].mosi_pin = level;
2375 }
2376
2377 static const struct {
2378 int cs, clk, miso, mosi;
2379 } s3c_spi_pins[2] = {
2380 { S3C_GPG(2), S3C_GPE(13), S3C_GPE(11), S3C_GPE(12) },
2381 { S3C_GPG(3), S3C_GPG(7), S3C_GPG(5), S3C_GPG(6) },
2382 };
2383
2384 static void s3c_spi_bitbang_init(struct s3c_spi_state_s *s,
2385 struct s3c_gpio_state_s *gpio)
2386 {
2387 int i;
2388 qemu_irq *cs = qemu_allocate_irqs(s3c_spi_bitbang_cs, s, 2);
2389 qemu_irq *clk = qemu_allocate_irqs(s3c_spi_bitbang_clk, s, 2);
2390 qemu_irq *mosi = qemu_allocate_irqs(s3c_spi_bitbang_mosi, s, 2);
2391
2392 for (i = 0; i < 2; i ++) {
2393 s3c_gpio_out_set(gpio, s3c_spi_pins[i].cs, cs[i]);
2394 s3c_gpio_out_set(gpio, s3c_spi_pins[i].clk, clk[i]);
2395 s->chan[i].miso = s3c_gpio_in_get(gpio)[s3c_spi_pins[i].miso];
2396 s3c_gpio_out_set(gpio, s3c_spi_pins[i].mosi, mosi[i]);
2397 }
2398 }
2399
2400 struct s3c_spi_state_s *s3c_spi_init(target_phys_addr_t base,
2401 qemu_irq irq0, qemu_irq drq0, qemu_irq irq1, qemu_irq drq1,
2402 struct s3c_gpio_state_s *gpio)
2403 {
2404 int iomemtype;
2405 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *)
2406 qemu_mallocz(sizeof(struct s3c_spi_state_s));
2407
2408 s->base = base;
2409 s->chan[0].irq = irq0;
2410 s->chan[0].drq = drq0;
2411 s->chan[1].irq = irq1;
2412 s->chan[1].drq = drq1;
2413
2414 s3c_spi_reset(s);
2415
2416 iomemtype = cpu_register_io_memory(0, s3c_spi_readfn,
2417 s3c_spi_writefn, s);
2418 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
2419
2420 s3c_spi_bitbang_init(s, gpio);
2421
2422 register_savevm("s3c24xx_spi", 0, 0, s3c_spi_save, s3c_spi_load, s);
2423
2424 return s;
2425 }
2426
2427 void s3c_spi_attach(struct s3c_spi_state_s *s, int ch,
2428 uint8_t (*txrx)(void *opaque, uint8_t value),
2429 uint8_t (*btxrx)(void *opaque, uint8_t value), void *opaque)
2430 {
2431 if (ch & ~1)
2432 cpu_abort(cpu_single_env, "%s: No channel %i\n", __FUNCTION__, ch);
2433 s->txrx[ch] = txrx;
2434 s->btxrx[ch] = btxrx;
2435 s->opaque[ch] = opaque;
2436 }
2437
2438 /* IIS-BUS interface */
2439 static inline void s3c_i2s_update(struct s3c_i2s_state_s *s)
2440 {
2441 s->tx_en =
2442 (s->control & (1 << 0)) && !(s->control & (1 << 3)) &&
2443 (s->mode & (1 << 7)) && (s->fcontrol & (1 << 13));
2444 s->rx_en =
2445 (s->control & (1 << 0)) && !(s->control & (1 << 2)) &&
2446 (s->mode & (1 << 6)) && (s->fcontrol & (1 << 12));
2447 s->control &= ~0xc0;
2448 /* The specs are unclear about the FIFO-ready flags logic.
2449 * Implement semantics that make most sense. */
2450 if (s->tx_en && s->tx_len)
2451 s->control |= (1 << 7);
2452 if (s->rx_en && s->rx_len)
2453 s->control |= (1 << 6);
2454
2455 qemu_set_irq(s->dma[S3C_RQ_I2SSDO], (s->control >> 5) &
2456 (s->control >> 7) & (s->fcontrol >> 15) & 1);
2457 qemu_set_irq(s->dma[S3C_RQ_I2SSDI0], (s->control >> 4) &
2458 (s->control >> 6) & (s->fcontrol >> 14) & 1);
2459 qemu_set_irq(s->dma[S3C_RQ_I2SSDI1], (s->control >> 4) &
2460 (s->control >> 6) & (s->fcontrol >> 14) & 1);
2461 }
2462
2463 static void s3c_i2s_reset(struct s3c_i2s_state_s *s)
2464 {
2465 s->control = 0x100;
2466 s->mode = 0x000;
2467 s->prescaler = 0x000;
2468 s->fcontrol = 0x0000;
2469 s->tx_len = 0;
2470 s->rx_len = 0;
2471 s3c_i2s_update(s);
2472 }
2473
2474 #define S3C_IISCON 0x00 /* IIS Control register */
2475 #define S3C_IISMOD 0x04 /* IIS Mode register */
2476 #define S3C_IISPSR 0x08 /* IIS Prescaler register */
2477 #define S3C_IISFCON 0x0c /* IIS FIFO Interface register */
2478 #define S3C_IISFIFO 0x10 /* IIS FIFO register */
2479
2480 static uint32_t s3c_i2s_read(void *opaque, target_phys_addr_t addr)
2481 {
2482 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *) opaque;
2483 uint32_t ret;
2484 addr -= s->base;
2485
2486 switch (addr) {
2487 case S3C_IISCON:
2488 return s->control;
2489 case S3C_IISMOD:
2490 return s->mode;
2491 case S3C_IISPSR:
2492 return s->prescaler;
2493 case S3C_IISFCON:
2494 return s->fcontrol |
2495 (MAX(32 - s->tx_len, 0) << 6) |
2496 MIN(s->rx_len, 32);
2497 case S3C_IISFIFO:
2498 if (s->rx_len > 0) {
2499 s->rx_len --;
2500 s3c_i2s_update(s);
2501 s->cycle ^= 1;
2502 if (s->cycle) {
2503 s->buffer = (uint16_t) (ret = s->codec_in(s->opaque));
2504 return ret >> 16;
2505 } else
2506 return s->buffer;
2507 }
2508 default:
2509 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2510 break;
2511 }
2512 return 0;
2513 }
2514
2515 static void s3c_i2s_write(void *opaque, target_phys_addr_t addr,
2516 uint32_t value)
2517 {
2518 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *) opaque;
2519 addr -= s->base;
2520
2521 switch (addr) {
2522 case S3C_IISCON:
2523 s->control = (s->control & 0x100) | (value & 0x03f);
2524 s3c_i2s_update(s);
2525 break;
2526 case S3C_IISMOD:
2527 s->mode = value & 0x1ff;
2528 s3c_i2s_update(s);
2529 break;
2530 case S3C_IISPSR:
2531 s->prescaler = value & 0x3ff;
2532 break;
2533 case S3C_IISFCON:
2534 s->fcontrol = value & 0xf000;
2535 s3c_i2s_update(s);
2536 break;
2537 case S3C_IISFIFO:
2538 if (s->tx_len && s->tx_en) {
2539 s->tx_len --;
2540 s3c_i2s_update(s);
2541 if (s->cycle)
2542 s->codec_out(s->opaque, value | ((uint32_t) s->buffer << 16));
2543 else
2544 s->buffer = (uint16_t) value;
2545 s->cycle ^= 1;
2546 }
2547 break;
2548 default:
2549 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2550 }
2551 }
2552
2553 static CPUReadMemoryFunc *s3c_i2s_readfn[] = {
2554 s3c_i2s_read,
2555 s3c_i2s_read,
2556 s3c_i2s_read,
2557 };
2558
2559 static CPUWriteMemoryFunc *s3c_i2s_writefn[] = {
2560 s3c_i2s_write,
2561 s3c_i2s_write,
2562 s3c_i2s_write,
2563 };
2564
2565 static void s3c_i2s_save(QEMUFile *f, void *opaque)
2566 {
2567 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *) opaque;
2568 qemu_put_be16s(f, &s->control);
2569 qemu_put_be16s(f, &s->mode);
2570 qemu_put_be16s(f, &s->prescaler);
2571 qemu_put_be16s(f, &s->fcontrol);
2572
2573 qemu_put_be32(f, s->tx_en);
2574 qemu_put_be32(f, s->rx_en);
2575 qemu_put_be32(f, s->tx_len);
2576 qemu_put_be32(f, s->rx_len);
2577 qemu_put_be16(f, s->buffer);
2578 qemu_put_be32(f, s->cycle);
2579 }
2580
2581 static int s3c_i2s_load(QEMUFile *f, void *opaque, int version_id)
2582 {
2583 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *) opaque;
2584 qemu_get_be16s(f, &s->control);
2585 qemu_get_be16s(f, &s->mode);
2586 qemu_get_be16s(f, &s->prescaler);
2587 qemu_get_be16s(f, &s->fcontrol);
2588
2589 s->tx_en = qemu_get_be32(f);
2590 s->rx_en = qemu_get_be32(f);
2591 s->tx_len = qemu_get_be32(f);
2592 s->rx_len = qemu_get_be32(f);
2593 s->buffer = qemu_get_be16(f);
2594 s->cycle = qemu_get_be32(f);
2595
2596 return 0;
2597 }
2598
2599 static void s3c_i2s_data_req(void *opaque, int tx, int rx)
2600 {
2601 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *) opaque;
2602 s->tx_len = tx;
2603 s->rx_len = rx;
2604 s3c_i2s_update(s);
2605 }
2606
2607 struct s3c_i2s_state_s *s3c_i2s_init(target_phys_addr_t base, qemu_irq *dma)
2608 {
2609 int iomemtype;
2610 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *)
2611 qemu_mallocz(sizeof(struct s3c_i2s_state_s));
2612
2613 s->base = base;
2614 s->dma = dma;
2615 s->data_req = s3c_i2s_data_req;
2616
2617 s3c_i2s_reset(s);
2618
2619 iomemtype = cpu_register_io_memory(0, s3c_i2s_readfn,
2620 s3c_i2s_writefn, s);
2621 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
2622
2623 register_savevm("s3c24xx_iis", 0, 0, s3c_i2s_save, s3c_i2s_load, s);
2624
2625 return s;
2626 }
2627
2628 /* Watchdog Timer */
2629 struct s3c_wdt_state_s {
2630 target_phys_addr_t base;
2631 qemu_irq irq;
2632 uint16_t control;
2633 uint16_t data;
2634 uint16_t count;
2635 QEMUTimer *tm;
2636 int64_t timestamp;
2637 };
2638
2639 static void s3c_wdt_start(struct s3c_wdt_state_s *s)
2640 {
2641 int enable = s->control & (1 << 5);
2642 int prescaler = (s->control >> 8) + 1;
2643 int divider = prescaler << (((s->control >> 3) & 3) + 4);
2644 if (enable) {
2645 s->timestamp = qemu_get_clock(vm_clock);
2646 qemu_mod_timer(s->tm, s->timestamp + muldiv64(divider * s->count,
2647 ticks_per_sec, S3C_PCLK_FREQ));
2648 } else
2649 qemu_del_timer(s->tm);
2650 }
2651
2652 static void s3c_wdt_stop(struct s3c_wdt_state_s *s)
2653 {
2654 int prescaler = (s->control >> 8) + 1;
2655 int divider = prescaler << (((s->control >> 3) & 3) + 4);
2656 int diff;
2657
2658 diff = muldiv64(qemu_get_clock(vm_clock) - s->timestamp, S3C_PCLK_FREQ,
2659 ticks_per_sec) / divider;
2660 s->count -= MIN(s->count, diff);
2661 s->timestamp = qemu_get_clock(vm_clock);
2662 }
2663
2664 static void s3c_wdt_reset(struct s3c_wdt_state_s *s)
2665 {
2666 s->control = 0x8021;
2667 s->data = 0x8000;
2668 s->count = 0x8000;
2669 s3c_wdt_start(s);
2670 }
2671
2672 static void s3c_wdt_timeout(void *opaque)
2673 {
2674 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *) opaque;
2675 if (s->control & (1 << 0)) {
2676 qemu_system_reset_request();
2677 return;
2678 }
2679 if (s->control & (1 << 2))
2680 qemu_irq_raise(s->irq);
2681 s->count = s->data;
2682 s3c_wdt_start(s);
2683 }
2684
2685 #define S3C_WTCON 0x00 /* Watchdog timer control register */
2686 #define S3C_WTDAT 0x04 /* Watchdog timer data register */
2687 #define S3C_WTCNT 0x08 /* Watchdog timer count register */
2688
2689 static uint32_t s3c_wdt_read(void *opaque, target_phys_addr_t addr)
2690 {
2691 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *) opaque;
2692 addr -= s->base;
2693
2694 switch (addr) {
2695 case S3C_WTCON:
2696 return s->control;
2697 case S3C_WTDAT:
2698 return s->data;
2699 case S3C_WTCNT:
2700 s3c_wdt_stop(s);
2701 return s->count;
2702 default:
2703 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2704 break;
2705 }
2706 return 0;
2707 }
2708
2709 static void s3c_wdt_write(void *opaque, target_phys_addr_t addr,
2710 uint32_t value)
2711 {
2712 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *) opaque;
2713 addr -= s->base;
2714
2715 switch (addr) {
2716 case S3C_WTCON:
2717 s3c_wdt_stop(s);
2718 s->control = value;
2719 s3c_wdt_start(s);
2720 break;
2721 case S3C_WTDAT:
2722 s->data = value;
2723 break;
2724 case S3C_WTCNT:
2725 s->count = value;
2726 s3c_wdt_start(s);
2727 break;
2728 default:
2729 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2730 }
2731 }
2732
2733 static CPUReadMemoryFunc *s3c_wdt_readfn[] = {
2734 s3c_wdt_read,
2735 s3c_wdt_read,
2736 s3c_wdt_read,
2737 };
2738
2739 static CPUWriteMemoryFunc *s3c_wdt_writefn[] = {
2740 s3c_wdt_write,
2741 s3c_wdt_write,
2742 s3c_wdt_write,
2743 };
2744
2745 static void s3c_wdt_save(QEMUFile *f, void *opaque)
2746 {
2747 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *) opaque;
2748
2749 s3c_wdt_stop(s);
2750 qemu_put_be16s(f, &s->control);
2751 qemu_put_be16s(f, &s->data);
2752 qemu_put_be16s(f, &s->count);
2753 qemu_put_be64s(f, &s->timestamp);
2754 }
2755
2756 static int s3c_wdt_load(QEMUFile *f, void *opaque, int version_id)
2757 {
2758 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *) opaque;
2759
2760 qemu_get_be16s(f, &s->control);
2761 qemu_get_be16s(f, &s->data);
2762 qemu_get_be16s(f, &s->count);
2763 qemu_get_be64s(f, &s->timestamp);
2764 s3c_wdt_start(s);
2765
2766 return 0;
2767 }
2768
2769 struct s3c_wdt_state_s *s3c_wdt_init(target_phys_addr_t base, qemu_irq irq)
2770 {
2771 int iomemtype;
2772 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *)
2773 qemu_mallocz(sizeof(struct s3c_wdt_state_s));
2774
2775 s->base = base;
2776 s->irq = irq;
2777 s->tm = qemu_new_timer(vm_clock, s3c_wdt_timeout, s);
2778
2779 s3c_wdt_reset(s);
2780
2781 iomemtype = cpu_register_io_memory(0, s3c_wdt_readfn,
2782 s3c_wdt_writefn, s);
2783 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
2784
2785 register_savevm("s3c24xx_wdt", 0, 0, s3c_wdt_save, s3c_wdt_load, s);
2786
2787 return s;
2788 }
2789
2790 /* On-chip UARTs */
2791 static struct {
2792 target_phys_addr_t base;
2793 int irq[3];
2794 int dma[1];
2795 } s3c2410_uart[] = {
2796 {
2797 0x50000000,
2798 { S3C_PICS_RXD0, S3C_PICS_TXD0, S3C_PICS_ERR0 },
2799 { S3C_RQ_UART0 },
2800 },
2801 {
2802 0x50004000,
2803 { S3C_PICS_RXD1, S3C_PICS_TXD1, S3C_PICS_ERR1 },
2804 { S3C_RQ_UART1 },
2805 },
2806 {
2807 0x50008000,
2808 { S3C_PICS_RXD2, S3C_PICS_TXD2, S3C_PICS_ERR2 },
2809 { S3C_RQ_UART2 },
2810 },
2811 { 0, { 0, 0, 0 }, { 0 } }
2812 };
2813
2814 /* General CPU reset */
2815 static void s3c2410_reset(void *opaque)
2816 {
2817 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
2818 int i;
2819 s3c_mc_reset(s);
2820 s3c_pic_reset(s->pic);
2821 s3c_dma_reset(s->dma);
2822 s3c_gpio_reset(s->io);
2823 s3c_lcd_reset(s->lcd);
2824 s3c_timers_reset(s->timers);
2825 s3c_mmci_reset(s->mmci);
2826 s3c_adc_reset(s->adc);
2827 s3c_i2c_reset(s->i2c);
2828 s3c_i2s_reset(s->i2s);
2829 s3c_rtc_reset(s->rtc);
2830 s3c_spi_reset(s->spi);
2831 s3c_udc_reset(s->udc);
2832 s3c_wdt_reset(s->wdt);
2833 s3c_clkpwr_reset(s);
2834 s3c_nand_reset(s);
2835 for (i = 0; s3c2410_uart[i].base; i ++)
2836 s3c_uart_reset(s->uart[i]);
2837 cpu_reset(s->env);
2838 }
2839
2840 /* Initialise an S3C2410A microprocessor. */
2841 struct s3c_state_s *s3c24xx_init(uint32_t cpu_id, unsigned int sdram_size, DisplayState *ds,
2842 SDState *mmc)
2843 {
2844 struct s3c_state_s *s;
2845 int iomemtype, i;
2846 s = (struct s3c_state_s *) qemu_mallocz(sizeof(struct s3c_state_s));
2847
2848 s->cpu_id = cpu_id;
2849
2850 s->env = cpu_init("arm920t");
2851 register_savevm("s3c24xx", 0, 0,
2852 cpu_save, cpu_load, s->env);
2853
2854 cpu_register_physical_memory(S3C_RAM_BASE, sdram_size,
2855 qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
2856
2857 /* If OM pins are 00, SRAM is mapped at 0x0 instead. */
2858 cpu_register_physical_memory(S3C_SRAM_BASE, S3C_SRAM_SIZE,
2859 qemu_ram_alloc(S3C_SRAM_SIZE) | IO_MEM_RAM);
2860
2861 s->mc_base = 0x48000000;
2862 s3c_mc_reset(s);
2863 iomemtype = cpu_register_io_memory(0, s3c_mc_readfn, s3c_mc_writefn, s);
2864 cpu_register_physical_memory(s->mc_base, 0xffffff, iomemtype);
2865 register_savevm("s3c24xx_mc", 0, 0, s3c_mc_save, s3c_mc_load, s);
2866
2867 s->pic = s3c_pic_init(0x4a000000, arm_pic_init_cpu(s->env));
2868 s->irq = s3c_pic_get(s->pic);
2869
2870 s->dma = s3c_dma_init(0x4b000000, &s->irq[S3C_PIC_DMA0]);
2871 s->drq = s3c_dma_get(s->dma);
2872
2873 s->clkpwr_base = 0x4c000000;
2874 s3c_clkpwr_reset(s);
2875 iomemtype = cpu_register_io_memory(0, s3c_clkpwr_readfn,
2876 s3c_clkpwr_writefn, s);
2877 cpu_register_physical_memory(s->clkpwr_base, 0xffffff, iomemtype);
2878 register_savevm("s3c24xx_clkpwr", 0, 0,
2879 s3c_clkpwr_save, s3c_clkpwr_load, s);
2880
2881 s->lcd = s3c_lcd_init(0x4d000000, ds, s->irq[S3C_PIC_LCD]);
2882
2883 s->nand_base = 0x4e000000;
2884 s3c_nand_reset(s);
2885 iomemtype = cpu_register_io_memory(0, s3c_nand_readfn,
2886 s3c_nand_writefn, s);
2887 cpu_register_physical_memory(s->nand_base, 0xffffff, iomemtype);
2888 register_savevm("s3c24xx_nand", 0, 0, s3c_nand_save, s3c_nand_load, s);
2889
2890 for (i = 0; s3c2410_uart[i].base; i ++) {
2891 s->uart[i] = s3c_uart_init(s3c2410_uart[i].base,
2892 &s->irq[s3c2410_uart[i].irq[0]],
2893 &s->drq[s3c2410_uart[i].dma[0]]);
2894 if (serial_hds[i])
2895 s3c_uart_attach(s->uart[i], serial_hds[i]);
2896 }
2897
2898 s->timers = s3c_timers_init(0x51000000, &s->irq[S3C_PIC_TIMER0], s->drq);
2899
2900 s->udc = s3c_udc_init(0x52000000, s->irq[S3C_PIC_USBD], s->drq);
2901
2902 s->wdt = s3c_wdt_init(0x53000000, s->irq[S3C_PIC_WDT]);
2903
2904 s->i2c = s3c_i2c_init(0x54000000, s->irq[S3C_PIC_IIC]);
2905
2906 s->i2s = s3c_i2s_init(0x55000000, s->drq);
2907
2908 s->io = s3c_gpio_init(0x56000000, s->irq, s->cpu_id);
2909
2910 s->rtc = s3c_rtc_init(0x57000000, s->irq[S3C_PIC_RTC]);
2911
2912 s->adc = s3c_adc_init(0x58000000, s->irq[S3C_PICS_ADC],
2913 s->irq[S3C_PICS_TC]);
2914
2915 s->spi = s3c_spi_init(0x59000000,
2916 s->irq[S3C_PIC_SPI0], s->drq[S3C_RQ_SPI0],
2917 s->irq[S3C_PIC_SPI1], s->drq[S3C_RQ_SPI1], s->io);
2918
2919 s->mmci = s3c_mmci_init(0x5a000000, 0x2410, mmc,
2920 s->irq[S3C_PIC_SDI], s->drq);
2921
2922 if (usb_enabled) {
2923 usb_ohci_init_pxa(0x49000000, 3, -1, s->irq[S3C_PIC_USBH]);
2924 }
2925
2926 qemu_register_reset(s3c2410_reset, s);
2927
2928 s3c_nand_setwp(s, 1);
2929
2930 /* Power on reset */
2931 s3c_gpio_setpwrstat(s->io, 1);
2932 return s;
2933 }