hw/ppc_oldworld.c

   1 /*
   2  * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
   3  *
   4  * Copyright (c) 2004-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "ppc.h"
  27 #include "ppc_mac.h"
  28 #include "mac_dbdma.h"
  29 #include "nvram.h"
  30 #include "pc.h"
  31 #include "sysemu.h"
  32 #include "net.h"
  33 #include "isa.h"
  34 #include "pci.h"
  35 #include "boards.h"
  36 #include "fw_cfg.h"
  37 #include "escc.h"
  38
  39 #define MAX_IDE_BUS 2
  40 #define VGA_BIOS_SIZE 65536
  41 #define CFG_ADDR 0xf0000510
  42
  43 /* temporary frame buffer OSI calls for the video.x driver. The right
  44    solution is to modify the driver to use VGA PCI I/Os */
  45 /* XXX: to be removed. This is no way related to emulation */
  46 static int vga_osi_call (CPUState *env)
  47 {
  48     static int vga_vbl_enabled;
  49     int linesize;
  50
  51     //    printf("osi_call R5=" REGX "\n", ppc_dump_gpr(env, 5));
  52
  53     /* same handler as PearPC, coming from the original MOL video
  54        driver. */
  55     switch(env->gpr[5]) {
  56     case 4:
  57         break;
  58     case 28: /* set_vmode */
  59         if (env->gpr[6] != 1 || env->gpr[7] != 0)
  60             env->gpr[3] = 1;
  61         else
  62             env->gpr[3] = 0;
  63         break;
  64     case 29: /* get_vmode_info */
  65         if (env->gpr[6] != 0) {
  66             if (env->gpr[6] != 1 || env->gpr[7] != 0) {
  67                 env->gpr[3] = 1;
  68                 break;
  69             }
  70         }
  71         env->gpr[3] = 0;
  72         env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
  73         env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
  74         env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
  75         env->gpr[7] = 85 << 16; /* refresh rate */
  76         env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
  77         linesize = ((graphic_depth + 7) >> 3) * graphic_width;
  78         linesize = (linesize + 3) & ~3;
  79         env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
  80         break;
  81     case 31: /* set_video power */
  82         env->gpr[3] = 0;
  83         break;
  84     case 39: /* video_ctrl */
  85         if (env->gpr[6] == 0 || env->gpr[6] == 1)
  86             vga_vbl_enabled = env->gpr[6];
  87         env->gpr[3] = 0;
  88         break;
  89     case 47:
  90         break;
  91     case 59: /* set_color */
  92         /* R6 = index, R7 = RGB */
  93         env->gpr[3] = 0;
  94         break;
  95     case 64: /* get color */
  96         /* R6 = index */
  97         env->gpr[3] = 0;
  98         break;
  99     case 116: /* set hwcursor */
 100         /* R6 = x, R7 = y, R8 = visible, R9 = data */
 101         break;
 102     default:
 103         fprintf(stderr, "unsupported OSI call R5=" REGX "\n",
 104                 ppc_dump_gpr(env, 5));
 105         break;
 106     }
 107
 108     return 1; /* osi_call handled */
 109 }
 110
 111 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
 112 {
 113     fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 114     return 0;
 115 }
 116
 117 static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
 118                                const char *boot_device,
 119                                const char *kernel_filename,
 120                                const char *kernel_cmdline,
 121                                const char *initrd_filename,
 122                                const char *cpu_model)
 123 {
 124     CPUState *env = NULL, *envs[MAX_CPUS];
 125     char buf[1024];
 126     qemu_irq *pic, **heathrow_irqs;
 127     int linux_boot, i;
 128     ram_addr_t ram_offset, vga_ram_offset, bios_offset, vga_bios_offset;
 129     uint32_t kernel_base, initrd_base;
 130     int32_t kernel_size, initrd_size;
 131     PCIBus *pci_bus;
 132     MacIONVRAMState *nvr;
 133     int vga_bios_size, bios_size;
 134     int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
 135     int escc_mem_index, ide_mem_index[2];
 136     uint16_t ppc_boot_device;
 137     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 138     int index;
 139     void *fw_cfg;
 140     void *dbdma;
 141
 142     linux_boot = (kernel_filename != NULL);
 143
 144     /* init CPUs */
 145     if (cpu_model == NULL)
 146         cpu_model = "G3";
 147     for (i = 0; i < smp_cpus; i++) {
 148         env = cpu_init(cpu_model);
 149         if (!env) {
 150             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 151             exit(1);
 152         }
 153         /* Set time-base frequency to 16.6 Mhz */
 154         cpu_ppc_tb_init(env,  16600000UL);
 155         env->osi_call = vga_osi_call;
 156         qemu_register_reset(&cpu_ppc_reset, env);
 157         envs[i] = env;
 158     }
 159
 160     /* allocate RAM */
 161     if (ram_size > (2047 << 20)) {
 162         fprintf(stderr,
 163                 "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n",
 164                 ((unsigned int)ram_size / (1 << 20)));
 165         exit(1);
 166     }
 167
 168     ram_offset = qemu_ram_alloc(ram_size);
 169     cpu_register_physical_memory(0, ram_size, ram_offset);
 170
 171     /* allocate VGA RAM */
 172     vga_ram_offset = qemu_ram_alloc(vga_ram_size);
 173
 174     /* allocate and load BIOS */
 175     bios_offset = qemu_ram_alloc(BIOS_SIZE);
 176     if (bios_name == NULL)
 177         bios_name = PROM_FILENAME;
 178     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 179     cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM);
 180
 181     /* Load OpenBIOS (ELF) */
 182     bios_size = load_elf(buf, 0, NULL, NULL, NULL);
 183     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 184         cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
 185         exit(1);
 186     }
 187
 188     /* allocate and load VGA BIOS */
 189     vga_bios_offset = qemu_ram_alloc(VGA_BIOS_SIZE);
 190     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
 191     vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);
 192     if (vga_bios_size < 0) {
 193         /* if no bios is present, we can still work */
 194         fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);
 195         vga_bios_size = 0;
 196     } else {
 197         /* set a specific header (XXX: find real Apple format for NDRV
 198            drivers) */
 199         phys_ram_base[vga_bios_offset] = 'N';
 200         phys_ram_base[vga_bios_offset + 1] = 'D';
 201         phys_ram_base[vga_bios_offset + 2] = 'R';
 202         phys_ram_base[vga_bios_offset + 3] = 'V';
 203         cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
 204                      vga_bios_size);
 205         vga_bios_size += 8;
 206     }
 207
 208     if (linux_boot) {
 209         uint64_t lowaddr = 0;
 210         kernel_base = KERNEL_LOAD_ADDR;
 211         /* Now we can load the kernel. The first step tries to load the kernel
 212            supposing PhysAddr = 0x00000000. If that was wrong the kernel is
 213            loaded again, the new PhysAddr being computed from lowaddr. */
 214         kernel_size = load_elf(kernel_filename, kernel_base, NULL, &lowaddr, NULL);
 215         if (kernel_size > 0 && lowaddr != KERNEL_LOAD_ADDR) {
 216             kernel_size = load_elf(kernel_filename, (2 * kernel_base) - lowaddr,
 217                                    NULL, 0, NULL);
 218         }
 219         if (kernel_size < 0)
 220             kernel_size = load_aout(kernel_filename, kernel_base,
 221                                     ram_size - kernel_base);
 222         if (kernel_size < 0)
 223             kernel_size = load_image_targphys(kernel_filename,
 224                                               kernel_base,
 225                                               ram_size - kernel_base);
 226         if (kernel_size < 0) {
 227             cpu_abort(env, "qemu: could not load kernel '%s'\n",
 228                       kernel_filename);
 229             exit(1);
 230         }
 231         /* load initrd */
 232         if (initrd_filename) {
 233             initrd_base = INITRD_LOAD_ADDR;
 234             initrd_size = load_image(initrd_filename,
 235                                      phys_ram_base + initrd_base);
 236             if (initrd_size < 0) {
 237                 cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
 238                           initrd_filename);
 239                 exit(1);
 240             }
 241         } else {
 242             initrd_base = 0;
 243             initrd_size = 0;
 244         }
 245         ppc_boot_device = 'm';
 246     } else {
 247         kernel_base = 0;
 248         kernel_size = 0;
 249         initrd_base = 0;
 250         initrd_size = 0;
 251         ppc_boot_device = '\0';
 252         for (i = 0; boot_device[i] != '\0'; i++) {
 253             /* TOFIX: for now, the second IDE channel is not properly
 254              *        used by OHW. The Mac floppy disk are not emulated.
 255              *        For now, OHW cannot boot from the network.
 256              */
 257 #if 0
 258             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 259                 ppc_boot_device = boot_device[i];
 260                 break;
 261             }
 262 #else
 263             if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
 264                 ppc_boot_device = boot_device[i];
 265                 break;
 266             }
 267 #endif
 268         }
 269         if (ppc_boot_device == '\0') {
 270             fprintf(stderr, "No valid boot device for G3 Beige machine\n");
 271             exit(1);
 272         }
 273     }
 274
 275     isa_mem_base = 0x80000000;
 276
 277     /* Register 2 MB of ISA IO space */
 278     isa_mmio_init(0xfe000000, 0x00200000);
 279
 280     /* XXX: we register only 1 output pin for heathrow PIC */
 281     heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
 282     heathrow_irqs[0] =
 283         qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1);
 284     /* Connect the heathrow PIC outputs to the 6xx bus */
 285     for (i = 0; i < smp_cpus; i++) {
 286         switch (PPC_INPUT(env)) {
 287         case PPC_FLAGS_INPUT_6xx:
 288             heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
 289             heathrow_irqs[i][0] =
 290                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
 291             break;
 292         default:
 293             cpu_abort(env, "Bus model not supported on OldWorld Mac machine\n");
 294             exit(1);
 295         }
 296     }
 297
 298     /* init basic PC hardware */
 299     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 300         cpu_abort(env, "Only 6xx bus is supported on heathrow machine\n");
 301         exit(1);
 302     }
 303     pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
 304     pci_bus = pci_grackle_init(0xfec00000, pic);
 305     pci_vga_init(pci_bus, phys_ram_base + vga_ram_offset,
 306                  vga_ram_offset, vga_ram_size,
 307                  vga_bios_offset, vga_bios_size);
 308
 309     escc_mem_index = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0],
 310                                serial_hds[1], ESCC_CLOCK, 4);
 311
 312     for(i = 0; i < nb_nics; i++)
 313         pci_nic_init(pci_bus, &nd_table[i], -1, "ne2k_pci");
 314
 315
 316     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 317         fprintf(stderr, "qemu: too many IDE bus\n");
 318         exit(1);
 319     }
 320
 321     /* First IDE channel is a MAC IDE on the MacIO bus */
 322     index = drive_get_index(IF_IDE, 0, 0);
 323     if (index == -1)
 324         hd[0] = NULL;
 325     else
 326         hd[0] =  drives_table[index].bdrv;
 327     index = drive_get_index(IF_IDE, 0, 1);
 328     if (index == -1)
 329         hd[1] = NULL;
 330     else
 331         hd[1] =  drives_table[index].bdrv;
 332     dbdma = DBDMA_init(&dbdma_mem_index);
 333     ide_mem_index[0] = -1;
 334     ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D], dbdma, 0x16, pic[0x02]);
 335
 336     /* Second IDE channel is a CMD646 on the PCI bus */
 337     index = drive_get_index(IF_IDE, 1, 0);
 338     if (index == -1)
 339         hd[0] = NULL;
 340     else
 341         hd[0] =  drives_table[index].bdrv;
 342     index = drive_get_index(IF_IDE, 1, 1);
 343     if (index == -1)
 344         hd[1] = NULL;
 345     else
 346         hd[1] =  drives_table[index].bdrv;
 347     hd[3] = hd[2] = NULL;
 348     pci_cmd646_ide_init(pci_bus, hd, 0);
 349
 350     /* cuda also initialize ADB */
 351     cuda_init(&cuda_mem_index, pic[0x12]);
 352
 353     adb_kbd_init(&adb_bus);
 354     adb_mouse_init(&adb_bus);
 355
 356     nvr = macio_nvram_init(&nvram_mem_index, 0x2000, 4);
 357     pmac_format_nvram_partition(nvr, 0x2000);
 358
 359     macio_init(pci_bus, PCI_DEVICE_ID_APPLE_343S1201, 1, pic_mem_index,
 360                dbdma_mem_index, cuda_mem_index, nvr, 2, ide_mem_index,
 361                escc_mem_index);
 362
 363     if (usb_enabled) {
 364         usb_ohci_init_pci(pci_bus, 3, -1);
 365     }
 366
 367     if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
 368         graphic_depth = 15;
 369
 370     /* No PCI init: the BIOS will do it */
 371
 372     fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
 373     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 374     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 375     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
 376     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
 377     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 378     if (kernel_cmdline) {
 379         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
 380         pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
 381     } else {
 382         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
 383     }
 384     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
 385     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 386     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
 387     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 388 }
 389
 390 QEMUMachine heathrow_machine = {
 391     .name = "g3beige",
 392     .desc = "Heathrow based PowerMAC",
 393     .init = ppc_heathrow_init,
 394     .ram_require = BIOS_SIZE + VGA_BIOS_SIZE + VGA_RAM_SIZE,
 395     .max_cpus = MAX_CPUS,
 396 };