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[MINI2440] Added the board to qemu proper
[sniper_test.git] / exec.c
blobc6490ff0747162eca49ae50994a5bd116c98e26e
1 /*
2 * virtual page mapping and translated block handling
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
19 */
20 #include "config.h"
21 #ifdef _WIN32
22 #define WIN32_LEAN_AND_MEAN
23 #include <windows.h>
24 #else
25 #include <sys/types.h>
26 #include <sys/mman.h>
27 #endif
28 #include <stdlib.h>
29 #include <stdio.h>
30 #include <stdarg.h>
31 #include <string.h>
32 #include <errno.h>
33 #include <unistd.h>
34 #include <inttypes.h>
35
36 #include "cpu.h"
37 #include "exec-all.h"
38 #include "qemu-common.h"
39 #include "tcg.h"
40 #include "hw/hw.h"
41 #include "osdep.h"
42 #include "kvm.h"
43 #if defined(CONFIG_USER_ONLY)
44 #include <qemu.h>
45 #endif
46
47 //#define DEBUG_TB_INVALIDATE
48 //#define DEBUG_FLUSH
49 //#define DEBUG_TLB
50 //#define DEBUG_UNASSIGNED
51
52 /* make various TB consistency checks */
53 //#define DEBUG_TB_CHECK
54 //#define DEBUG_TLB_CHECK
55
56 //#define DEBUG_IOPORT
57 //#define DEBUG_SUBPAGE
58
59 #if !defined(CONFIG_USER_ONLY)
60 /* TB consistency checks only implemented for usermode emulation. */
61 #undef DEBUG_TB_CHECK
62 #endif
63
64 #define SMC_BITMAP_USE_THRESHOLD 10
65
66 #define MMAP_AREA_START 0x00000000
67 #define MMAP_AREA_END 0xa8000000
68
69 #if defined(TARGET_SPARC64)
70 #define TARGET_PHYS_ADDR_SPACE_BITS 41
71 #elif defined(TARGET_SPARC)
72 #define TARGET_PHYS_ADDR_SPACE_BITS 36
73 #elif defined(TARGET_ALPHA)
74 #define TARGET_PHYS_ADDR_SPACE_BITS 42
75 #define TARGET_VIRT_ADDR_SPACE_BITS 42
76 #elif defined(TARGET_PPC64)
77 #define TARGET_PHYS_ADDR_SPACE_BITS 42
78 #elif defined(TARGET_X86_64) && !defined(USE_KQEMU)
79 #define TARGET_PHYS_ADDR_SPACE_BITS 42
80 #elif defined(TARGET_I386) && !defined(USE_KQEMU)
81 #define TARGET_PHYS_ADDR_SPACE_BITS 36
82 #else
83 /* Note: for compatibility with kqemu, we use 32 bits for x86_64 */
84 #define TARGET_PHYS_ADDR_SPACE_BITS 32
85 #endif
86
87 static TranslationBlock *tbs;
88 int code_gen_max_blocks;
89 TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
90 static int nb_tbs;
91 /* any access to the tbs or the page table must use this lock */
92 spinlock_t tb_lock = SPIN_LOCK_UNLOCKED;
93
94 #if defined(__arm__) || defined(__sparc_v9__)
95 /* The prologue must be reachable with a direct jump. ARM and Sparc64
96 have limited branch ranges (possibly also PPC) so place it in a
97 section close to code segment. */
98 #define code_gen_section \
99 __attribute__((__section__(".gen_code"))) \
100 __attribute__((aligned (32)))
101 #else
102 #define code_gen_section \
103 __attribute__((aligned (32)))
104 #endif
105
106 uint8_t code_gen_prologue[1024] code_gen_section;
107 static uint8_t *code_gen_buffer;
108 static unsigned long code_gen_buffer_size;
109 /* threshold to flush the translated code buffer */
110 static unsigned long code_gen_buffer_max_size;
111 uint8_t *code_gen_ptr;
112
113 #if !defined(CONFIG_USER_ONLY)
114 ram_addr_t phys_ram_size;
115 int phys_ram_fd;
116 uint8_t *phys_ram_base;
117 uint8_t *phys_ram_dirty;
118 static int in_migration;
119 static ram_addr_t phys_ram_alloc_offset = 0;
120 #endif
121
122 CPUState *first_cpu;
123 /* current CPU in the current thread. It is only valid inside
124 cpu_exec() */
125 CPUState *cpu_single_env;
126 /* 0 = Do not count executed instructions.
127 1 = Precise instruction counting.
128 2 = Adaptive rate instruction counting. */
129 int use_icount = 0;
130 /* Current instruction counter. While executing translated code this may
131 include some instructions that have not yet been executed. */
132 int64_t qemu_icount;
133
134 typedef struct PageDesc {
135 /* list of TBs intersecting this ram page */
136 TranslationBlock *first_tb;
137 /* in order to optimize self modifying code, we count the number
138 of lookups we do to a given page to use a bitmap */
139 unsigned int code_write_count;
140 uint8_t *code_bitmap;
141 #if defined(CONFIG_USER_ONLY)
142 unsigned long flags;
143 #endif
144 } PageDesc;
145
146 typedef struct PhysPageDesc {
147 /* offset in host memory of the page + io_index in the low bits */
148 ram_addr_t phys_offset;
149 ram_addr_t region_offset;
150 } PhysPageDesc;
151
152 #define L2_BITS 10
153 #if defined(CONFIG_USER_ONLY) && defined(TARGET_VIRT_ADDR_SPACE_BITS)
154 /* XXX: this is a temporary hack for alpha target.
155 * In the future, this is to be replaced by a multi-level table
156 * to actually be able to handle the complete 64 bits address space.
157 */
158 #define L1_BITS (TARGET_VIRT_ADDR_SPACE_BITS - L2_BITS - TARGET_PAGE_BITS)
159 #else
160 #define L1_BITS (32 - L2_BITS - TARGET_PAGE_BITS)
161 #endif
162
163 #define L1_SIZE (1 << L1_BITS)
164 #define L2_SIZE (1 << L2_BITS)
165
166 unsigned long qemu_real_host_page_size;
167 unsigned long qemu_host_page_bits;
168 unsigned long qemu_host_page_size;
169 unsigned long qemu_host_page_mask;
170
171 /* XXX: for system emulation, it could just be an array */
172 static PageDesc *l1_map[L1_SIZE];
173 static PhysPageDesc **l1_phys_map;
174
175 #if !defined(CONFIG_USER_ONLY)
176 static void io_mem_init(void);
177
178 /* io memory support */
179 CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
180 CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
181 void *io_mem_opaque[IO_MEM_NB_ENTRIES];
182 static char io_mem_used[IO_MEM_NB_ENTRIES];
183 static int io_mem_watch;
184 #endif
185
186 /* log support */
187 static const char *logfilename = "/tmp/qemu.log";
188 FILE *logfile;
189 int loglevel;
190 static int log_append = 0;
191
192 /* statistics */
193 static int tlb_flush_count;
194 static int tb_flush_count;
195 static int tb_phys_invalidate_count;
196
197 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
198 typedef struct subpage_t {
199 target_phys_addr_t base;
200 CPUReadMemoryFunc **mem_read[TARGET_PAGE_SIZE][4];
201 CPUWriteMemoryFunc **mem_write[TARGET_PAGE_SIZE][4];
202 void *opaque[TARGET_PAGE_SIZE][2][4];
203 ram_addr_t region_offset[TARGET_PAGE_SIZE][2][4];
204 } subpage_t;
205
206 #ifdef _WIN32
207 static void map_exec(void *addr, long size)
208 {
209 DWORD old_protect;
210 VirtualProtect(addr, size,
211 PAGE_EXECUTE_READWRITE, &old_protect);
212
213 }
214 #else
215 static void map_exec(void *addr, long size)
216 {
217 unsigned long start, end, page_size;
218
219 page_size = getpagesize();
220 start = (unsigned long)addr;
221 start &= ~(page_size - 1);
222
223 end = (unsigned long)addr + size;
224 end += page_size - 1;
225 end &= ~(page_size - 1);
226
227 mprotect((void *)start, end - start,
228 PROT_READ | PROT_WRITE | PROT_EXEC);
229 }
230 #endif
231
232 static void page_init(void)
233 {
234 /* NOTE: we can always suppose that qemu_host_page_size >=
235 TARGET_PAGE_SIZE */
236 #ifdef _WIN32
237 {
238 SYSTEM_INFO system_info;
239
240 GetSystemInfo(&system_info);
241 qemu_real_host_page_size = system_info.dwPageSize;
242 }
243 #else
244 qemu_real_host_page_size = getpagesize();
245 #endif
246 if (qemu_host_page_size == 0)
247 qemu_host_page_size = qemu_real_host_page_size;
248 if (qemu_host_page_size < TARGET_PAGE_SIZE)
249 qemu_host_page_size = TARGET_PAGE_SIZE;
250 qemu_host_page_bits = 0;
251 while ((1 << qemu_host_page_bits) < qemu_host_page_size)
252 qemu_host_page_bits++;
253 qemu_host_page_mask = ~(qemu_host_page_size - 1);
254 l1_phys_map = qemu_vmalloc(L1_SIZE * sizeof(void *));
255 memset(l1_phys_map, 0, L1_SIZE * sizeof(void *));
256
257 #if !defined(_WIN32) && defined(CONFIG_USER_ONLY)
258 {
259 long long startaddr, endaddr;
260 FILE *f;
261 int n;
262
263 mmap_lock();
264 last_brk = (unsigned long)sbrk(0);
265 f = fopen("/proc/self/maps", "r");
266 if (f) {
267 do {
268 n = fscanf (f, "%llx-%llx %*[^\n]\n", &startaddr, &endaddr);
269 if (n == 2) {
270 startaddr = MIN(startaddr,
271 (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1);
272 endaddr = MIN(endaddr,
273 (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1);
274 page_set_flags(startaddr & TARGET_PAGE_MASK,
275 TARGET_PAGE_ALIGN(endaddr),
276 PAGE_RESERVED);
277 }
278 } while (!feof(f));
279 fclose(f);
280 }
281 mmap_unlock();
282 }
283 #endif
284 }
285
286 static inline PageDesc **page_l1_map(target_ulong index)
287 {
288 #if TARGET_LONG_BITS > 32
289 /* Host memory outside guest VM. For 32-bit targets we have already
290 excluded high addresses. */
291 if (index > ((target_ulong)L2_SIZE * L1_SIZE))
292 return NULL;
293 #endif
294 return &l1_map[index >> L2_BITS];
295 }
296
297 static inline PageDesc *page_find_alloc(target_ulong index)
298 {
299 PageDesc **lp, *p;
300 lp = page_l1_map(index);
301 if (!lp)
302 return NULL;
303
304 p = *lp;
305 if (!p) {
306 /* allocate if not found */
307 #if defined(CONFIG_USER_ONLY)
308 size_t len = sizeof(PageDesc) * L2_SIZE;
309 /* Don't use qemu_malloc because it may recurse. */
310 p = mmap(0, len, PROT_READ | PROT_WRITE,
311 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
312 *lp = p;
313 if (h2g_valid(p)) {
314 unsigned long addr = h2g(p);
315 page_set_flags(addr & TARGET_PAGE_MASK,
316 TARGET_PAGE_ALIGN(addr + len),
317 PAGE_RESERVED);
318 }
319 #else
320 p = qemu_mallocz(sizeof(PageDesc) * L2_SIZE);
321 *lp = p;
322 #endif
323 }
324 return p + (index & (L2_SIZE - 1));
325 }
326
327 static inline PageDesc *page_find(target_ulong index)
328 {
329 PageDesc **lp, *p;
330 lp = page_l1_map(index);
331 if (!lp)
332 return NULL;
333
334 p = *lp;
335 if (!p)
336 return 0;
337 return p + (index & (L2_SIZE - 1));
338 }
339
340 static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc)
341 {
342 void **lp, **p;
343 PhysPageDesc *pd;
344
345 p = (void **)l1_phys_map;
346 #if TARGET_PHYS_ADDR_SPACE_BITS > 32
347
348 #if TARGET_PHYS_ADDR_SPACE_BITS > (32 + L1_BITS)
349 #error unsupported TARGET_PHYS_ADDR_SPACE_BITS
350 #endif
351 lp = p + ((index >> (L1_BITS + L2_BITS)) & (L1_SIZE - 1));
352 p = *lp;
353 if (!p) {
354 /* allocate if not found */
355 if (!alloc)
356 return NULL;
357 p = qemu_vmalloc(sizeof(void *) * L1_SIZE);
358 memset(p, 0, sizeof(void *) * L1_SIZE);
359 *lp = p;
360 }
361 #endif
362 lp = p + ((index >> L2_BITS) & (L1_SIZE - 1));
363 pd = *lp;
364 if (!pd) {
365 int i;
366 /* allocate if not found */
367 if (!alloc)
368 return NULL;
369 pd = qemu_vmalloc(sizeof(PhysPageDesc) * L2_SIZE);
370 *lp = pd;
371 for (i = 0; i < L2_SIZE; i++) {
372 pd[i].phys_offset = IO_MEM_UNASSIGNED;
373 pd[i].region_offset = (index + i) << TARGET_PAGE_BITS;
374 }
375 }
376 return ((PhysPageDesc *)pd) + (index & (L2_SIZE - 1));
377 }
378
379 static inline PhysPageDesc *phys_page_find(target_phys_addr_t index)
380 {
381 return phys_page_find_alloc(index, 0);
382 }
383
384 #if !defined(CONFIG_USER_ONLY)
385 static void tlb_protect_code(ram_addr_t ram_addr);
386 static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
387 target_ulong vaddr);
388 #define mmap_lock() do { } while(0)
389 #define mmap_unlock() do { } while(0)
390 #endif
391
392 #define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024)
393
394 #if defined(CONFIG_USER_ONLY)
395 /* Currently it is not recommanded to allocate big chunks of data in
396 user mode. It will change when a dedicated libc will be used */
397 #define USE_STATIC_CODE_GEN_BUFFER
398 #endif
399
400 #ifdef USE_STATIC_CODE_GEN_BUFFER
401 static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE];
402 #endif
403
404 static void code_gen_alloc(unsigned long tb_size)
405 {
406 #ifdef USE_STATIC_CODE_GEN_BUFFER
407 code_gen_buffer = static_code_gen_buffer;
408 code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
409 map_exec(code_gen_buffer, code_gen_buffer_size);
410 #else
411 code_gen_buffer_size = tb_size;
412 if (code_gen_buffer_size == 0) {
413 #if defined(CONFIG_USER_ONLY)
414 /* in user mode, phys_ram_size is not meaningful */
415 code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
416 #else
417 /* XXX: needs ajustments */
418 code_gen_buffer_size = (unsigned long)(phys_ram_size / 4);
419 #endif
420 }
421 if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE)
422 code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE;
423 /* The code gen buffer location may have constraints depending on
424 the host cpu and OS */
425 #if defined(__linux__)
426 {
427 int flags;
428 void *start = NULL;
429
430 flags = MAP_PRIVATE | MAP_ANONYMOUS;
431 #if defined(__x86_64__)
432 flags |= MAP_32BIT;
433 /* Cannot map more than that */
434 if (code_gen_buffer_size > (800 * 1024 * 1024))
435 code_gen_buffer_size = (800 * 1024 * 1024);
436 #elif defined(__sparc_v9__)
437 // Map the buffer below 2G, so we can use direct calls and branches
438 flags |= MAP_FIXED;
439 start = (void *) 0x60000000UL;
440 if (code_gen_buffer_size > (512 * 1024 * 1024))
441 code_gen_buffer_size = (512 * 1024 * 1024);
442 #elif defined(__arm__)
443 /* Map the buffer below 32M, so we can use direct calls and branches */
444 flags |= MAP_FIXED;
445 start = (void *) 0x01000000UL;
446 if (code_gen_buffer_size > 16 * 1024 * 1024)
447 code_gen_buffer_size = 16 * 1024 * 1024;
448 #endif
449 code_gen_buffer = mmap(start, code_gen_buffer_size,
450 PROT_WRITE | PROT_READ | PROT_EXEC,
451 flags, -1, 0);
452 if (code_gen_buffer == MAP_FAILED) {
453 fprintf(stderr, "Could not allocate dynamic translator buffer\n");
454 exit(1);
455 }
456 }
457 #elif defined(__FreeBSD__) || defined(__DragonFly__)
458 {
459 int flags;
460 void *addr = NULL;
461 flags = MAP_PRIVATE | MAP_ANONYMOUS;
462 #if defined(__x86_64__)
463 /* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume
464 * 0x40000000 is free */
465 flags |= MAP_FIXED;
466 addr = (void *)0x40000000;
467 /* Cannot map more than that */
468 if (code_gen_buffer_size > (800 * 1024 * 1024))
469 code_gen_buffer_size = (800 * 1024 * 1024);
470 #endif
471 code_gen_buffer = mmap(addr, code_gen_buffer_size,
472 PROT_WRITE | PROT_READ | PROT_EXEC,
473 flags, -1, 0);
474 if (code_gen_buffer == MAP_FAILED) {
475 fprintf(stderr, "Could not allocate dynamic translator buffer\n");
476 exit(1);
477 }
478 }
479 #else
480 code_gen_buffer = qemu_malloc(code_gen_buffer_size);
481 map_exec(code_gen_buffer, code_gen_buffer_size);
482 #endif
483 #endif /* !USE_STATIC_CODE_GEN_BUFFER */
484 map_exec(code_gen_prologue, sizeof(code_gen_prologue));
485 code_gen_buffer_max_size = code_gen_buffer_size -
486 code_gen_max_block_size();
487 code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE;
488 tbs = qemu_malloc(code_gen_max_blocks * sizeof(TranslationBlock));
489 }
490
491 /* Must be called before using the QEMU cpus. 'tb_size' is the size
492 (in bytes) allocated to the translation buffer. Zero means default
493 size. */
494 void cpu_exec_init_all(unsigned long tb_size)
495 {
496 cpu_gen_init();
497 code_gen_alloc(tb_size);
498 code_gen_ptr = code_gen_buffer;
499 page_init();
500 #if !defined(CONFIG_USER_ONLY)
501 io_mem_init();
502 #endif
503 }
504
505 #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
506
507 #define CPU_COMMON_SAVE_VERSION 1
508
509 static void cpu_common_save(QEMUFile *f, void *opaque)
510 {
511 CPUState *env = opaque;
512
513 qemu_put_be32s(f, &env->halted);
514 qemu_put_be32s(f, &env->interrupt_request);
515 }
516
517 static int cpu_common_load(QEMUFile *f, void *opaque, int version_id)
518 {
519 CPUState *env = opaque;
520
521 if (version_id != CPU_COMMON_SAVE_VERSION)
522 return -EINVAL;
523
524 qemu_get_be32s(f, &env->halted);
525 qemu_get_be32s(f, &env->interrupt_request);
526 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
527 version_id is increased. */
528 env->interrupt_request &= ~0x01;
529 tlb_flush(env, 1);
530
531 return 0;
532 }
533 #endif
534
535 void cpu_exec_init(CPUState *env)
536 {
537 CPUState **penv;
538 int cpu_index;
539
540 #if defined(CONFIG_USER_ONLY)
541 cpu_list_lock();
542 #endif
543 env->next_cpu = NULL;
544 penv = &first_cpu;
545 cpu_index = 0;
546 while (*penv != NULL) {
547 penv = (CPUState **)&(*penv)->next_cpu;
548 cpu_index++;
549 }
550 env->cpu_index = cpu_index;
551 TAILQ_INIT(&env->breakpoints);
552 TAILQ_INIT(&env->watchpoints);
553 *penv = env;
554 #if defined(CONFIG_USER_ONLY)
555 cpu_list_unlock();
556 #endif
557 #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
558 register_savevm("cpu_common", cpu_index, CPU_COMMON_SAVE_VERSION,
559 cpu_common_save, cpu_common_load, env);
560 register_savevm("cpu", cpu_index, CPU_SAVE_VERSION,
561 cpu_save, cpu_load, env);
562 #endif
563 }
564
565 static inline void invalidate_page_bitmap(PageDesc *p)
566 {
567 if (p->code_bitmap) {
568 qemu_free(p->code_bitmap);
569 p->code_bitmap = NULL;
570 }
571 p->code_write_count = 0;
572 }
573
574 /* set to NULL all the 'first_tb' fields in all PageDescs */
575 static void page_flush_tb(void)
576 {
577 int i, j;
578 PageDesc *p;
579
580 for(i = 0; i < L1_SIZE; i++) {
581 p = l1_map[i];
582 if (p) {
583 for(j = 0; j < L2_SIZE; j++) {
584 p->first_tb = NULL;
585 invalidate_page_bitmap(p);
586 p++;
587 }
588 }
589 }
590 }
591
592 /* flush all the translation blocks */
593 /* XXX: tb_flush is currently not thread safe */
594 void tb_flush(CPUState *env1)
595 {
596 CPUState *env;
597 #if defined(DEBUG_FLUSH)
598 printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n",
599 (unsigned long)(code_gen_ptr - code_gen_buffer),
600 nb_tbs, nb_tbs > 0 ?
601 ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0);
602 #endif
603 if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size)
604 cpu_abort(env1, "Internal error: code buffer overflow\n");
605
606 nb_tbs = 0;
607
608 for(env = first_cpu; env != NULL; env = env->next_cpu) {
609 memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
610 }
611
612 memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *));
613 page_flush_tb();
614
615 code_gen_ptr = code_gen_buffer;
616 /* XXX: flush processor icache at this point if cache flush is
617 expensive */
618 tb_flush_count++;
619 }
620
621 #ifdef DEBUG_TB_CHECK
622
623 static void tb_invalidate_check(target_ulong address)
624 {
625 TranslationBlock *tb;
626 int i;
627 address &= TARGET_PAGE_MASK;
628 for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
629 for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
630 if (!(address + TARGET_PAGE_SIZE <= tb->pc ||
631 address >= tb->pc + tb->size)) {
632 printf("ERROR invalidate: address=%08lx PC=%08lx size=%04x\n",
633 address, (long)tb->pc, tb->size);
634 }
635 }
636 }
637 }
638
639 /* verify that all the pages have correct rights for code */
640 static void tb_page_check(void)
641 {
642 TranslationBlock *tb;
643 int i, flags1, flags2;
644
645 for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
646 for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
647 flags1 = page_get_flags(tb->pc);
648 flags2 = page_get_flags(tb->pc + tb->size - 1);
649 if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) {
650 printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n",
651 (long)tb->pc, tb->size, flags1, flags2);
652 }
653 }
654 }
655 }
656
657 static void tb_jmp_check(TranslationBlock *tb)
658 {
659 TranslationBlock *tb1;
660 unsigned int n1;
661
662 /* suppress any remaining jumps to this TB */
663 tb1 = tb->jmp_first;
664 for(;;) {
665 n1 = (long)tb1 & 3;
666 tb1 = (TranslationBlock *)((long)tb1 & ~3);
667 if (n1 == 2)
668 break;
669 tb1 = tb1->jmp_next[n1];
670 }
671 /* check end of list */
672 if (tb1 != tb) {
673 printf("ERROR: jmp_list from 0x%08lx\n", (long)tb);
674 }
675 }
676
677 #endif
678
679 /* invalidate one TB */
680 static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb,
681 int next_offset)
682 {
683 TranslationBlock *tb1;
684 for(;;) {
685 tb1 = *ptb;
686 if (tb1 == tb) {
687 *ptb = *(TranslationBlock **)((char *)tb1 + next_offset);
688 break;
689 }
690 ptb = (TranslationBlock **)((char *)tb1 + next_offset);
691 }
692 }
693
694 static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb)
695 {
696 TranslationBlock *tb1;
697 unsigned int n1;
698
699 for(;;) {
700 tb1 = *ptb;
701 n1 = (long)tb1 & 3;
702 tb1 = (TranslationBlock *)((long)tb1 & ~3);
703 if (tb1 == tb) {
704 *ptb = tb1->page_next[n1];
705 break;
706 }
707 ptb = &tb1->page_next[n1];
708 }
709 }
710
711 static inline void tb_jmp_remove(TranslationBlock *tb, int n)
712 {
713 TranslationBlock *tb1, **ptb;
714 unsigned int n1;
715
716 ptb = &tb->jmp_next[n];
717 tb1 = *ptb;
718 if (tb1) {
719 /* find tb(n) in circular list */
720 for(;;) {
721 tb1 = *ptb;
722 n1 = (long)tb1 & 3;
723 tb1 = (TranslationBlock *)((long)tb1 & ~3);
724 if (n1 == n && tb1 == tb)
725 break;
726 if (n1 == 2) {
727 ptb = &tb1->jmp_first;
728 } else {
729 ptb = &tb1->jmp_next[n1];
730 }
731 }
732 /* now we can suppress tb(n) from the list */
733 *ptb = tb->jmp_next[n];
734
735 tb->jmp_next[n] = NULL;
736 }
737 }
738
739 /* reset the jump entry 'n' of a TB so that it is not chained to
740 another TB */
741 static inline void tb_reset_jump(TranslationBlock *tb, int n)
742 {
743 tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n]));
744 }
745
746 void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr)
747 {
748 CPUState *env;
749 PageDesc *p;
750 unsigned int h, n1;
751 target_phys_addr_t phys_pc;
752 TranslationBlock *tb1, *tb2;
753
754 /* remove the TB from the hash list */
755 phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
756 h = tb_phys_hash_func(phys_pc);
757 tb_remove(&tb_phys_hash[h], tb,
758 offsetof(TranslationBlock, phys_hash_next));
759
760 /* remove the TB from the page list */
761 if (tb->page_addr[0] != page_addr) {
762 p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS);
763 tb_page_remove(&p->first_tb, tb);
764 invalidate_page_bitmap(p);
765 }
766 if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) {
767 p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS);
768 tb_page_remove(&p->first_tb, tb);
769 invalidate_page_bitmap(p);
770 }
771
772 tb_invalidated_flag = 1;
773
774 /* remove the TB from the hash list */
775 h = tb_jmp_cache_hash_func(tb->pc);
776 for(env = first_cpu; env != NULL; env = env->next_cpu) {
777 if (env->tb_jmp_cache[h] == tb)
778 env->tb_jmp_cache[h] = NULL;
779 }
780
781 /* suppress this TB from the two jump lists */
782 tb_jmp_remove(tb, 0);
783 tb_jmp_remove(tb, 1);
784
785 /* suppress any remaining jumps to this TB */
786 tb1 = tb->jmp_first;
787 for(;;) {
788 n1 = (long)tb1 & 3;
789 if (n1 == 2)
790 break;
791 tb1 = (TranslationBlock *)((long)tb1 & ~3);
792 tb2 = tb1->jmp_next[n1];
793 tb_reset_jump(tb1, n1);
794 tb1->jmp_next[n1] = NULL;
795 tb1 = tb2;
796 }
797 tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */
798
799 tb_phys_invalidate_count++;
800 }
801
802 static inline void set_bits(uint8_t *tab, int start, int len)
803 {
804 int end, mask, end1;
805
806 end = start + len;
807 tab += start >> 3;
808 mask = 0xff << (start & 7);
809 if ((start & ~7) == (end & ~7)) {
810 if (start < end) {
811 mask &= ~(0xff << (end & 7));
812 *tab |= mask;
813 }
814 } else {
815 *tab++ |= mask;
816 start = (start + 8) & ~7;
817 end1 = end & ~7;
818 while (start < end1) {
819 *tab++ = 0xff;
820 start += 8;
821 }
822 if (start < end) {
823 mask = ~(0xff << (end & 7));
824 *tab |= mask;
825 }
826 }
827 }
828
829 static void build_page_bitmap(PageDesc *p)
830 {
831 int n, tb_start, tb_end;
832 TranslationBlock *tb;
833
834 p->code_bitmap = qemu_mallocz(TARGET_PAGE_SIZE / 8);
835
836 tb = p->first_tb;
837 while (tb != NULL) {
838 n = (long)tb & 3;
839 tb = (TranslationBlock *)((long)tb & ~3);
840 /* NOTE: this is subtle as a TB may span two physical pages */
841 if (n == 0) {
842 /* NOTE: tb_end may be after the end of the page, but
843 it is not a problem */
844 tb_start = tb->pc & ~TARGET_PAGE_MASK;
845 tb_end = tb_start + tb->size;
846 if (tb_end > TARGET_PAGE_SIZE)
847 tb_end = TARGET_PAGE_SIZE;
848 } else {
849 tb_start = 0;
850 tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
851 }
852 set_bits(p->code_bitmap, tb_start, tb_end - tb_start);
853 tb = tb->page_next[n];
854 }
855 }
856
857 TranslationBlock *tb_gen_code(CPUState *env,
858 target_ulong pc, target_ulong cs_base,
859 int flags, int cflags)
860 {
861 TranslationBlock *tb;
862 uint8_t *tc_ptr;
863 target_ulong phys_pc, phys_page2, virt_page2;
864 int code_gen_size;
865
866 phys_pc = get_phys_addr_code(env, pc);
867 tb = tb_alloc(pc);
868 if (!tb) {
869 /* flush must be done */
870 tb_flush(env);
871 /* cannot fail at this point */
872 tb = tb_alloc(pc);
873 /* Don't forget to invalidate previous TB info. */
874 tb_invalidated_flag = 1;
875 }
876 tc_ptr = code_gen_ptr;
877 tb->tc_ptr = tc_ptr;
878 tb->cs_base = cs_base;
879 tb->flags = flags;
880 tb->cflags = cflags;
881 cpu_gen_code(env, tb, &code_gen_size);
882 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
883
884 /* check next page if needed */
885 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
886 phys_page2 = -1;
887 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
888 phys_page2 = get_phys_addr_code(env, virt_page2);
889 }
890 tb_link_phys(tb, phys_pc, phys_page2);
891 return tb;
892 }
893
894 /* invalidate all TBs which intersect with the target physical page
895 starting in range [start;end[. NOTE: start and end must refer to
896 the same physical page. 'is_cpu_write_access' should be true if called
897 from a real cpu write access: the virtual CPU will exit the current
898 TB if code is modified inside this TB. */
899 void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
900 int is_cpu_write_access)
901 {
902 TranslationBlock *tb, *tb_next, *saved_tb;
903 CPUState *env = cpu_single_env;
904 target_ulong tb_start, tb_end;
905 PageDesc *p;
906 int n;
907 #ifdef TARGET_HAS_PRECISE_SMC
908 int current_tb_not_found = is_cpu_write_access;
909 TranslationBlock *current_tb = NULL;
910 int current_tb_modified = 0;
911 target_ulong current_pc = 0;
912 target_ulong current_cs_base = 0;
913 int current_flags = 0;
914 #endif /* TARGET_HAS_PRECISE_SMC */
915
916 p = page_find(start >> TARGET_PAGE_BITS);
917 if (!p)
918 return;
919 if (!p->code_bitmap &&
920 ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD &&
921 is_cpu_write_access) {
922 /* build code bitmap */
923 build_page_bitmap(p);
924 }
925
926 /* we remove all the TBs in the range [start, end[ */
927 /* XXX: see if in some cases it could be faster to invalidate all the code */
928 tb = p->first_tb;
929 while (tb != NULL) {
930 n = (long)tb & 3;
931 tb = (TranslationBlock *)((long)tb & ~3);
932 tb_next = tb->page_next[n];
933 /* NOTE: this is subtle as a TB may span two physical pages */
934 if (n == 0) {
935 /* NOTE: tb_end may be after the end of the page, but
936 it is not a problem */
937 tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
938 tb_end = tb_start + tb->size;
939 } else {
940 tb_start = tb->page_addr[1];
941 tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
942 }
943 if (!(tb_end <= start || tb_start >= end)) {
944 #ifdef TARGET_HAS_PRECISE_SMC
945 if (current_tb_not_found) {
946 current_tb_not_found = 0;
947 current_tb = NULL;
948 if (env->mem_io_pc) {
949 /* now we have a real cpu fault */
950 current_tb = tb_find_pc(env->mem_io_pc);
951 }
952 }
953 if (current_tb == tb &&
954 (current_tb->cflags & CF_COUNT_MASK) != 1) {
955 /* If we are modifying the current TB, we must stop
956 its execution. We could be more precise by checking
957 that the modification is after the current PC, but it
958 would require a specialized function to partially
959 restore the CPU state */
960
961 current_tb_modified = 1;
962 cpu_restore_state(current_tb, env,
963 env->mem_io_pc, NULL);
964 cpu_get_tb_cpu_state(env, &current_pc, &current_cs_base,
965 &current_flags);
966 }
967 #endif /* TARGET_HAS_PRECISE_SMC */
968 /* we need to do that to handle the case where a signal
969 occurs while doing tb_phys_invalidate() */
970 saved_tb = NULL;
971 if (env) {
972 saved_tb = env->current_tb;
973 env->current_tb = NULL;
974 }
975 tb_phys_invalidate(tb, -1);
976 if (env) {
977 env->current_tb = saved_tb;
978 if (env->interrupt_request && env->current_tb)
979 cpu_interrupt(env, env->interrupt_request);
980 }
981 }
982 tb = tb_next;
983 }
984 #if !defined(CONFIG_USER_ONLY)
985 /* if no code remaining, no need to continue to use slow writes */
986 if (!p->first_tb) {
987 invalidate_page_bitmap(p);
988 if (is_cpu_write_access) {
989 tlb_unprotect_code_phys(env, start, env->mem_io_vaddr);
990 }
991 }
992 #endif
993 #ifdef TARGET_HAS_PRECISE_SMC
994 if (current_tb_modified) {
995 /* we generate a block containing just the instruction
996 modifying the memory. It will ensure that it cannot modify
997 itself */
998 env->current_tb = NULL;
999 tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
1000 cpu_resume_from_signal(env, NULL);
1001 }
1002 #endif
1003 }
1004
1005 /* len must be <= 8 and start must be a multiple of len */
1006 static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int len)
1007 {
1008 PageDesc *p;
1009 int offset, b;
1010 #if 0
1011 if (1) {
1012 qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n",
1013 cpu_single_env->mem_io_vaddr, len,
1014 cpu_single_env->eip,
1015 cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base);
1016 }
1017 #endif
1018 p = page_find(start >> TARGET_PAGE_BITS);
1019 if (!p)
1020 return;
1021 if (p->code_bitmap) {
1022 offset = start & ~TARGET_PAGE_MASK;
1023 b = p->code_bitmap[offset >> 3] >> (offset & 7);
1024 if (b & ((1 << len) - 1))
1025 goto do_invalidate;
1026 } else {
1027 do_invalidate:
1028 tb_invalidate_phys_page_range(start, start + len, 1);
1029 }
1030 }
1031
1032 #if !defined(CONFIG_SOFTMMU)
1033 static void tb_invalidate_phys_page(target_phys_addr_t addr,
1034 unsigned long pc, void *puc)
1035 {
1036 TranslationBlock *tb;
1037 PageDesc *p;
1038 int n;
1039 #ifdef TARGET_HAS_PRECISE_SMC
1040 TranslationBlock *current_tb = NULL;
1041 CPUState *env = cpu_single_env;
1042 int current_tb_modified = 0;
1043 target_ulong current_pc = 0;
1044 target_ulong current_cs_base = 0;
1045 int current_flags = 0;
1046 #endif
1047
1048 addr &= TARGET_PAGE_MASK;
1049 p = page_find(addr >> TARGET_PAGE_BITS);
1050 if (!p)
1051 return;
1052 tb = p->first_tb;
1053 #ifdef TARGET_HAS_PRECISE_SMC
1054 if (tb && pc != 0) {
1055 current_tb = tb_find_pc(pc);
1056 }
1057 #endif
1058 while (tb != NULL) {
1059 n = (long)tb & 3;
1060 tb = (TranslationBlock *)((long)tb & ~3);
1061 #ifdef TARGET_HAS_PRECISE_SMC
1062 if (current_tb == tb &&
1063 (current_tb->cflags & CF_COUNT_MASK) != 1) {
1064 /* If we are modifying the current TB, we must stop
1065 its execution. We could be more precise by checking
1066 that the modification is after the current PC, but it
1067 would require a specialized function to partially
1068 restore the CPU state */
1069
1070 current_tb_modified = 1;
1071 cpu_restore_state(current_tb, env, pc, puc);
1072 cpu_get_tb_cpu_state(env, &current_pc, &current_cs_base,
1073 &current_flags);
1074 }
1075 #endif /* TARGET_HAS_PRECISE_SMC */
1076 tb_phys_invalidate(tb, addr);
1077 tb = tb->page_next[n];
1078 }
1079 p->first_tb = NULL;
1080 #ifdef TARGET_HAS_PRECISE_SMC
1081 if (current_tb_modified) {
1082 /* we generate a block containing just the instruction
1083 modifying the memory. It will ensure that it cannot modify
1084 itself */
1085 env->current_tb = NULL;
1086 tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
1087 cpu_resume_from_signal(env, puc);
1088 }
1089 #endif
1090 }
1091 #endif
1092
1093 /* add the tb in the target page and protect it if necessary */
1094 static inline void tb_alloc_page(TranslationBlock *tb,
1095 unsigned int n, target_ulong page_addr)
1096 {
1097 PageDesc *p;
1098 TranslationBlock *last_first_tb;
1099
1100 tb->page_addr[n] = page_addr;
1101 p = page_find_alloc(page_addr >> TARGET_PAGE_BITS);
1102 tb->page_next[n] = p->first_tb;
1103 last_first_tb = p->first_tb;
1104 p->first_tb = (TranslationBlock *)((long)tb | n);
1105 invalidate_page_bitmap(p);
1106
1107 #if defined(TARGET_HAS_SMC) || 1
1108
1109 #if defined(CONFIG_USER_ONLY)
1110 if (p->flags & PAGE_WRITE) {
1111 target_ulong addr;
1112 PageDesc *p2;
1113 int prot;
1114
1115 /* force the host page as non writable (writes will have a
1116 page fault + mprotect overhead) */
1117 page_addr &= qemu_host_page_mask;
1118 prot = 0;
1119 for(addr = page_addr; addr < page_addr + qemu_host_page_size;
1120 addr += TARGET_PAGE_SIZE) {
1121
1122 p2 = page_find (addr >> TARGET_PAGE_BITS);
1123 if (!p2)
1124 continue;
1125 prot |= p2->flags;
1126 p2->flags &= ~PAGE_WRITE;
1127 page_get_flags(addr);
1128 }
1129 mprotect(g2h(page_addr), qemu_host_page_size,
1130 (prot & PAGE_BITS) & ~PAGE_WRITE);
1131 #ifdef DEBUG_TB_INVALIDATE
1132 printf("protecting code page: 0x" TARGET_FMT_lx "\n",
1133 page_addr);
1134 #endif
1135 }
1136 #else
1137 /* if some code is already present, then the pages are already
1138 protected. So we handle the case where only the first TB is
1139 allocated in a physical page */
1140 if (!last_first_tb) {
1141 tlb_protect_code(page_addr);
1142 }
1143 #endif
1144
1145 #endif /* TARGET_HAS_SMC */
1146 }
1147
1148 /* Allocate a new translation block. Flush the translation buffer if
1149 too many translation blocks or too much generated code. */
1150 TranslationBlock *tb_alloc(target_ulong pc)
1151 {
1152 TranslationBlock *tb;
1153
1154 if (nb_tbs >= code_gen_max_blocks ||
1155 (code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size)
1156 return NULL;
1157 tb = &tbs[nb_tbs++];
1158 tb->pc = pc;
1159 tb->cflags = 0;
1160 return tb;
1161 }
1162
1163 void tb_free(TranslationBlock *tb)
1164 {
1165 /* In practice this is mostly used for single use temporary TB
1166 Ignore the hard cases and just back up if this TB happens to
1167 be the last one generated. */
1168 if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) {
1169 code_gen_ptr = tb->tc_ptr;
1170 nb_tbs--;
1171 }
1172 }
1173
1174 /* add a new TB and link it to the physical page tables. phys_page2 is
1175 (-1) to indicate that only one page contains the TB. */
1176 void tb_link_phys(TranslationBlock *tb,
1177 target_ulong phys_pc, target_ulong phys_page2)
1178 {
1179 unsigned int h;
1180 TranslationBlock **ptb;
1181
1182 /* Grab the mmap lock to stop another thread invalidating this TB
1183 before we are done. */
1184 mmap_lock();
1185 /* add in the physical hash table */
1186 h = tb_phys_hash_func(phys_pc);
1187 ptb = &tb_phys_hash[h];
1188 tb->phys_hash_next = *ptb;
1189 *ptb = tb;
1190
1191 /* add in the page list */
1192 tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK);
1193 if (phys_page2 != -1)
1194 tb_alloc_page(tb, 1, phys_page2);
1195 else
1196 tb->page_addr[1] = -1;
1197
1198 tb->jmp_first = (TranslationBlock *)((long)tb | 2);
1199 tb->jmp_next[0] = NULL;
1200 tb->jmp_next[1] = NULL;
1201
1202 /* init original jump addresses */
1203 if (tb->tb_next_offset[0] != 0xffff)
1204 tb_reset_jump(tb, 0);
1205 if (tb->tb_next_offset[1] != 0xffff)
1206 tb_reset_jump(tb, 1);
1207
1208 #ifdef DEBUG_TB_CHECK
1209 tb_page_check();
1210 #endif
1211 mmap_unlock();
1212 }
1213
1214 /* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr <
1215 tb[1].tc_ptr. Return NULL if not found */
1216 TranslationBlock *tb_find_pc(unsigned long tc_ptr)
1217 {
1218 int m_min, m_max, m;
1219 unsigned long v;
1220 TranslationBlock *tb;
1221
1222 if (nb_tbs <= 0)
1223 return NULL;
1224 if (tc_ptr < (unsigned long)code_gen_buffer ||
1225 tc_ptr >= (unsigned long)code_gen_ptr)
1226 return NULL;
1227 /* binary search (cf Knuth) */
1228 m_min = 0;
1229 m_max = nb_tbs - 1;
1230 while (m_min <= m_max) {
1231 m = (m_min + m_max) >> 1;
1232 tb = &tbs[m];
1233 v = (unsigned long)tb->tc_ptr;
1234 if (v == tc_ptr)
1235 return tb;
1236 else if (tc_ptr < v) {
1237 m_max = m - 1;
1238 } else {
1239 m_min = m + 1;
1240 }
1241 }
1242 return &tbs[m_max];
1243 }
1244
1245 static void tb_reset_jump_recursive(TranslationBlock *tb);
1246
1247 static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n)
1248 {
1249 TranslationBlock *tb1, *tb_next, **ptb;
1250 unsigned int n1;
1251
1252 tb1 = tb->jmp_next[n];
1253 if (tb1 != NULL) {
1254 /* find head of list */
1255 for(;;) {
1256 n1 = (long)tb1 & 3;
1257 tb1 = (TranslationBlock *)((long)tb1 & ~3);
1258 if (n1 == 2)
1259 break;
1260 tb1 = tb1->jmp_next[n1];
1261 }
1262 /* we are now sure now that tb jumps to tb1 */
1263 tb_next = tb1;
1264
1265 /* remove tb from the jmp_first list */
1266 ptb = &tb_next->jmp_first;
1267 for(;;) {
1268 tb1 = *ptb;
1269 n1 = (long)tb1 & 3;
1270 tb1 = (TranslationBlock *)((long)tb1 & ~3);
1271 if (n1 == n && tb1 == tb)
1272 break;
1273 ptb = &tb1->jmp_next[n1];
1274 }
1275 *ptb = tb->jmp_next[n];
1276 tb->jmp_next[n] = NULL;
1277
1278 /* suppress the jump to next tb in generated code */
1279 tb_reset_jump(tb, n);
1280
1281 /* suppress jumps in the tb on which we could have jumped */
1282 tb_reset_jump_recursive(tb_next);
1283 }
1284 }
1285
1286 static void tb_reset_jump_recursive(TranslationBlock *tb)
1287 {
1288 tb_reset_jump_recursive2(tb, 0);
1289 tb_reset_jump_recursive2(tb, 1);
1290 }
1291
1292 #if defined(TARGET_HAS_ICE)
1293 static void breakpoint_invalidate(CPUState *env, target_ulong pc)
1294 {
1295 target_phys_addr_t addr;
1296 target_ulong pd;
1297 ram_addr_t ram_addr;
1298 PhysPageDesc *p;
1299
1300 addr = cpu_get_phys_page_debug(env, pc);
1301 p = phys_page_find(addr >> TARGET_PAGE_BITS);
1302 if (!p) {
1303 pd = IO_MEM_UNASSIGNED;
1304 } else {
1305 pd = p->phys_offset;
1306 }
1307 ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK);
1308 tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0);
1309 }
1310 #endif
1311
1312 /* Add a watchpoint. */
1313 int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
1314 int flags, CPUWatchpoint **watchpoint)
1315 {
1316 target_ulong len_mask = ~(len - 1);
1317 CPUWatchpoint *wp;
1318
1319 /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */
1320 if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) {
1321 fprintf(stderr, "qemu: tried to set invalid watchpoint at "
1322 TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len);
1323 return -EINVAL;
1324 }
1325 wp = qemu_malloc(sizeof(*wp));
1326
1327 wp->vaddr = addr;
1328 wp->len_mask = len_mask;
1329 wp->flags = flags;
1330
1331 /* keep all GDB-injected watchpoints in front */
1332 if (flags & BP_GDB)
1333 TAILQ_INSERT_HEAD(&env->watchpoints, wp, entry);
1334 else
1335 TAILQ_INSERT_TAIL(&env->watchpoints, wp, entry);
1336
1337 tlb_flush_page(env, addr);
1338
1339 if (watchpoint)
1340 *watchpoint = wp;
1341 return 0;
1342 }
1343
1344 /* Remove a specific watchpoint. */
1345 int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len,
1346 int flags)
1347 {
1348 target_ulong len_mask = ~(len - 1);
1349 CPUWatchpoint *wp;
1350
1351 TAILQ_FOREACH(wp, &env->watchpoints, entry) {
1352 if (addr == wp->vaddr && len_mask == wp->len_mask
1353 && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
1354 cpu_watchpoint_remove_by_ref(env, wp);
1355 return 0;
1356 }
1357 }
1358 return -ENOENT;
1359 }
1360
1361 /* Remove a specific watchpoint by reference. */
1362 void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint)
1363 {
1364 TAILQ_REMOVE(&env->watchpoints, watchpoint, entry);
1365
1366 tlb_flush_page(env, watchpoint->vaddr);
1367
1368 qemu_free(watchpoint);
1369 }
1370
1371 /* Remove all matching watchpoints. */
1372 void cpu_watchpoint_remove_all(CPUState *env, int mask)
1373 {
1374 CPUWatchpoint *wp, *next;
1375
1376 TAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) {
1377 if (wp->flags & mask)
1378 cpu_watchpoint_remove_by_ref(env, wp);
1379 }
1380 }
1381
1382 /* Add a breakpoint. */
1383 int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags,
1384 CPUBreakpoint **breakpoint)
1385 {
1386 #if defined(TARGET_HAS_ICE)
1387 CPUBreakpoint *bp;
1388
1389 bp = qemu_malloc(sizeof(*bp));
1390
1391 bp->pc = pc;
1392 bp->flags = flags;
1393
1394 /* keep all GDB-injected breakpoints in front */
1395 if (flags & BP_GDB)
1396 TAILQ_INSERT_HEAD(&env->breakpoints, bp, entry);
1397 else
1398 TAILQ_INSERT_TAIL(&env->breakpoints, bp, entry);
1399
1400 breakpoint_invalidate(env, pc);
1401
1402 if (breakpoint)
1403 *breakpoint = bp;
1404 return 0;
1405 #else
1406 return -ENOSYS;
1407 #endif
1408 }
1409
1410 /* Remove a specific breakpoint. */
1411 int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags)
1412 {
1413 #if defined(TARGET_HAS_ICE)
1414 CPUBreakpoint *bp;
1415
1416 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
1417 if (bp->pc == pc && bp->flags == flags) {
1418 cpu_breakpoint_remove_by_ref(env, bp);
1419 return 0;
1420 }
1421 }
1422 return -ENOENT;
1423 #else
1424 return -ENOSYS;
1425 #endif
1426 }
1427
1428 /* Remove a specific breakpoint by reference. */
1429 void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint)
1430 {
1431 #if defined(TARGET_HAS_ICE)
1432 TAILQ_REMOVE(&env->breakpoints, breakpoint, entry);
1433
1434 breakpoint_invalidate(env, breakpoint->pc);
1435
1436 qemu_free(breakpoint);
1437 #endif
1438 }
1439
1440 /* Remove all matching breakpoints. */
1441 void cpu_breakpoint_remove_all(CPUState *env, int mask)
1442 {
1443 #if defined(TARGET_HAS_ICE)
1444 CPUBreakpoint *bp, *next;
1445
1446 TAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) {
1447 if (bp->flags & mask)
1448 cpu_breakpoint_remove_by_ref(env, bp);
1449 }
1450 #endif
1451 }
1452
1453 /* enable or disable single step mode. EXCP_DEBUG is returned by the
1454 CPU loop after each instruction */
1455 void cpu_single_step(CPUState *env, int enabled)
1456 {
1457 #if defined(TARGET_HAS_ICE)
1458 if (env->singlestep_enabled != enabled) {
1459 env->singlestep_enabled = enabled;
1460 /* must flush all the translated code to avoid inconsistancies */
1461 /* XXX: only flush what is necessary */
1462 tb_flush(env);
1463 }
1464 #endif
1465 }
1466
1467 /* enable or disable low levels log */
1468 void cpu_set_log(int log_flags)
1469 {
1470 loglevel = log_flags;
1471 if (loglevel && !logfile) {
1472 logfile = fopen(logfilename, log_append ? "a" : "w");
1473 if (!logfile) {
1474 perror(logfilename);
1475 _exit(1);
1476 }
1477 #if !defined(CONFIG_SOFTMMU)
1478 /* must avoid mmap() usage of glibc by setting a buffer "by hand" */
1479 {
1480 static char logfile_buf[4096];
1481 setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf));
1482 }
1483 #else
1484 setvbuf(logfile, NULL, _IOLBF, 0);
1485 #endif
1486 log_append = 1;
1487 }
1488 if (!loglevel && logfile) {
1489 fclose(logfile);
1490 logfile = NULL;
1491 }
1492 }
1493
1494 void cpu_set_log_filename(const char *filename)
1495 {
1496 logfilename = strdup(filename);
1497 if (logfile) {
1498 fclose(logfile);
1499 logfile = NULL;
1500 }
1501 cpu_set_log(loglevel);
1502 }
1503
1504 static void cpu_unlink_tb(CPUState *env)
1505 {
1506 #if defined(USE_NPTL)
1507 /* FIXME: TB unchaining isn't SMP safe. For now just ignore the
1508 problem and hope the cpu will stop of its own accord. For userspace
1509 emulation this often isn't actually as bad as it sounds. Often
1510 signals are used primarily to interrupt blocking syscalls. */
1511 #else
1512 TranslationBlock *tb;
1513 static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED;
1514
1515 tb = env->current_tb;
1516 /* if the cpu is currently executing code, we must unlink it and
1517 all the potentially executing TB */
1518 if (tb && !testandset(&interrupt_lock)) {
1519 env->current_tb = NULL;
1520 tb_reset_jump_recursive(tb);
1521 resetlock(&interrupt_lock);
1522 }
1523 #endif
1524 }
1525
1526 /* mask must never be zero, except for A20 change call */
1527 void cpu_interrupt(CPUState *env, int mask)
1528 {
1529 int old_mask;
1530
1531 old_mask = env->interrupt_request;
1532 env->interrupt_request |= mask;
1533
1534 if (use_icount) {
1535 env->icount_decr.u16.high = 0xffff;
1536 #ifndef CONFIG_USER_ONLY
1537 if (!can_do_io(env)
1538 && (mask & ~old_mask) != 0) {
1539 cpu_abort(env, "Raised interrupt while not in I/O function");
1540 }
1541 #endif
1542 } else {
1543 cpu_unlink_tb(env);
1544 }
1545 }
1546
1547 void cpu_reset_interrupt(CPUState *env, int mask)
1548 {
1549 env->interrupt_request &= ~mask;
1550 }
1551
1552 void cpu_exit(CPUState *env)
1553 {
1554 env->exit_request = 1;
1555 cpu_unlink_tb(env);
1556 }
1557
1558 const CPULogItem cpu_log_items[] = {
1559 { CPU_LOG_TB_OUT_ASM, "out_asm",
1560 "show generated host assembly code for each compiled TB" },
1561 { CPU_LOG_TB_IN_ASM, "in_asm",
1562 "show target assembly code for each compiled TB" },
1563 { CPU_LOG_TB_OP, "op",
1564 "show micro ops for each compiled TB" },
1565 { CPU_LOG_TB_OP_OPT, "op_opt",
1566 "show micro ops "
1567 #ifdef TARGET_I386
1568 "before eflags optimization and "
1569 #endif
1570 "after liveness analysis" },
1571 { CPU_LOG_INT, "int",
1572 "show interrupts/exceptions in short format" },
1573 { CPU_LOG_EXEC, "exec",
1574 "show trace before each executed TB (lots of logs)" },
1575 { CPU_LOG_TB_CPU, "cpu",
1576 "show CPU state before block translation" },
1577 #ifdef TARGET_I386
1578 { CPU_LOG_PCALL, "pcall",
1579 "show protected mode far calls/returns/exceptions" },
1580 { CPU_LOG_RESET, "cpu_reset",
1581 "show CPU state before CPU resets" },
1582 #endif
1583 #ifdef DEBUG_IOPORT
1584 { CPU_LOG_IOPORT, "ioport",
1585 "show all i/o ports accesses" },
1586 #endif
1587 { 0, NULL, NULL },
1588 };
1589
1590 static int cmp1(const char *s1, int n, const char *s2)
1591 {
1592 if (strlen(s2) != n)
1593 return 0;
1594 return memcmp(s1, s2, n) == 0;
1595 }
1596
1597 /* takes a comma separated list of log masks. Return 0 if error. */
1598 int cpu_str_to_log_mask(const char *str)
1599 {
1600 const CPULogItem *item;
1601 int mask;
1602 const char *p, *p1;
1603
1604 p = str;
1605 mask = 0;
1606 for(;;) {
1607 p1 = strchr(p, ',');
1608 if (!p1)
1609 p1 = p + strlen(p);
1610 if(cmp1(p,p1-p,"all")) {
1611 for(item = cpu_log_items; item->mask != 0; item++) {
1612 mask |= item->mask;
1613 }
1614 } else {
1615 for(item = cpu_log_items; item->mask != 0; item++) {
1616 if (cmp1(p, p1 - p, item->name))
1617 goto found;
1618 }
1619 return 0;
1620 }
1621 found:
1622 mask |= item->mask;
1623 if (*p1 != ',')
1624 break;
1625 p = p1 + 1;
1626 }
1627 return mask;
1628 }
1629
1630 void cpu_abort(CPUState *env, const char *fmt, ...)
1631 {
1632 va_list ap;
1633 va_list ap2;
1634
1635 va_start(ap, fmt);
1636 va_copy(ap2, ap);
1637 fprintf(stderr, "qemu: fatal: ");
1638 vfprintf(stderr, fmt, ap);
1639 fprintf(stderr, "\n");
1640 #ifdef TARGET_I386
1641 cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP);
1642 #else
1643 cpu_dump_state(env, stderr, fprintf, 0);
1644 #endif
1645 if (qemu_log_enabled()) {
1646 qemu_log("qemu: fatal: ");
1647 qemu_log_vprintf(fmt, ap2);
1648 qemu_log("\n");
1649 #ifdef TARGET_I386
1650 log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP);
1651 #else
1652 log_cpu_state(env, 0);
1653 #endif
1654 qemu_log_flush();
1655 qemu_log_close();
1656 }
1657 va_end(ap2);
1658 va_end(ap);
1659 abort();
1660 }
1661
1662 CPUState *cpu_copy(CPUState *env)
1663 {
1664 CPUState *new_env = cpu_init(env->cpu_model_str);
1665 CPUState *next_cpu = new_env->next_cpu;
1666 int cpu_index = new_env->cpu_index;
1667 #if defined(TARGET_HAS_ICE)
1668 CPUBreakpoint *bp;
1669 CPUWatchpoint *wp;
1670 #endif
1671
1672 memcpy(new_env, env, sizeof(CPUState));
1673
1674 /* Preserve chaining and index. */
1675 new_env->next_cpu = next_cpu;
1676 new_env->cpu_index = cpu_index;
1677
1678 /* Clone all break/watchpoints.
1679 Note: Once we support ptrace with hw-debug register access, make sure
1680 BP_CPU break/watchpoints are handled correctly on clone. */
1681 TAILQ_INIT(&env->breakpoints);
1682 TAILQ_INIT(&env->watchpoints);
1683 #if defined(TARGET_HAS_ICE)
1684 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
1685 cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL);
1686 }
1687 TAILQ_FOREACH(wp, &env->watchpoints, entry) {
1688 cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1,
1689 wp->flags, NULL);
1690 }
1691 #endif
1692
1693 return new_env;
1694 }
1695
1696 #if !defined(CONFIG_USER_ONLY)
1697
1698 static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr)
1699 {
1700 unsigned int i;
1701
1702 /* Discard jump cache entries for any tb which might potentially
1703 overlap the flushed page. */
1704 i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE);
1705 memset (&env->tb_jmp_cache[i], 0,
1706 TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
1707
1708 i = tb_jmp_cache_hash_page(addr);
1709 memset (&env->tb_jmp_cache[i], 0,
1710 TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
1711 }
1712
1713 /* NOTE: if flush_global is true, also flush global entries (not
1714 implemented yet) */
1715 void tlb_flush(CPUState *env, int flush_global)
1716 {
1717 int i;
1718
1719 #if defined(DEBUG_TLB)
1720 printf("tlb_flush:\n");
1721 #endif
1722 /* must reset current TB so that interrupts cannot modify the
1723 links while we are modifying them */
1724 env->current_tb = NULL;
1725
1726 for(i = 0; i < CPU_TLB_SIZE; i++) {
1727 env->tlb_table[0][i].addr_read = -1;
1728 env->tlb_table[0][i].addr_write = -1;
1729 env->tlb_table[0][i].addr_code = -1;
1730 env->tlb_table[1][i].addr_read = -1;
1731 env->tlb_table[1][i].addr_write = -1;
1732 env->tlb_table[1][i].addr_code = -1;
1733 #if (NB_MMU_MODES >= 3)
1734 env->tlb_table[2][i].addr_read = -1;
1735 env->tlb_table[2][i].addr_write = -1;
1736 env->tlb_table[2][i].addr_code = -1;
1737 #if (NB_MMU_MODES == 4)
1738 env->tlb_table[3][i].addr_read = -1;
1739 env->tlb_table[3][i].addr_write = -1;
1740 env->tlb_table[3][i].addr_code = -1;
1741 #endif
1742 #endif
1743 }
1744
1745 memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
1746
1747 #ifdef USE_KQEMU
1748 if (env->kqemu_enabled) {
1749 kqemu_flush(env, flush_global);
1750 }
1751 #endif
1752 tlb_flush_count++;
1753 }
1754
1755 static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
1756 {
1757 if (addr == (tlb_entry->addr_read &
1758 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
1759 addr == (tlb_entry->addr_write &
1760 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
1761 addr == (tlb_entry->addr_code &
1762 (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
1763 tlb_entry->addr_read = -1;
1764 tlb_entry->addr_write = -1;
1765 tlb_entry->addr_code = -1;
1766 }
1767 }
1768
1769 void tlb_flush_page(CPUState *env, target_ulong addr)
1770 {
1771 int i;
1772
1773 #if defined(DEBUG_TLB)
1774 printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr);
1775 #endif
1776 /* must reset current TB so that interrupts cannot modify the
1777 links while we are modifying them */
1778 env->current_tb = NULL;
1779
1780 addr &= TARGET_PAGE_MASK;
1781 i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
1782 tlb_flush_entry(&env->tlb_table[0][i], addr);
1783 tlb_flush_entry(&env->tlb_table[1][i], addr);
1784 #if (NB_MMU_MODES >= 3)
1785 tlb_flush_entry(&env->tlb_table[2][i], addr);
1786 #if (NB_MMU_MODES == 4)
1787 tlb_flush_entry(&env->tlb_table[3][i], addr);
1788 #endif
1789 #endif
1790
1791 tlb_flush_jmp_cache(env, addr);
1792
1793 #ifdef USE_KQEMU
1794 if (env->kqemu_enabled) {
1795 kqemu_flush_page(env, addr);
1796 }
1797 #endif
1798 }
1799
1800 /* update the TLBs so that writes to code in the virtual page 'addr'
1801 can be detected */
1802 static void tlb_protect_code(ram_addr_t ram_addr)
1803 {
1804 cpu_physical_memory_reset_dirty(ram_addr,
1805 ram_addr + TARGET_PAGE_SIZE,
1806 CODE_DIRTY_FLAG);
1807 }
1808
1809 /* update the TLB so that writes in physical page 'phys_addr' are no longer
1810 tested for self modifying code */
1811 static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
1812 target_ulong vaddr)
1813 {
1814 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] |= CODE_DIRTY_FLAG;
1815 }
1816
1817 static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry,
1818 unsigned long start, unsigned long length)
1819 {
1820 unsigned long addr;
1821 if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
1822 addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
1823 if ((addr - start) < length) {
1824 tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY;
1825 }
1826 }
1827 }
1828
1829 void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
1830 int dirty_flags)
1831 {
1832 CPUState *env;
1833 unsigned long length, start1;
1834 int i, mask, len;
1835 uint8_t *p;
1836
1837 start &= TARGET_PAGE_MASK;
1838 end = TARGET_PAGE_ALIGN(end);
1839
1840 length = end - start;
1841 if (length == 0)
1842 return;
1843 len = length >> TARGET_PAGE_BITS;
1844 #ifdef USE_KQEMU
1845 /* XXX: should not depend on cpu context */
1846 env = first_cpu;
1847 if (env->kqemu_enabled) {
1848 ram_addr_t addr;
1849 addr = start;
1850 for(i = 0; i < len; i++) {
1851 kqemu_set_notdirty(env, addr);
1852 addr += TARGET_PAGE_SIZE;
1853 }
1854 }
1855 #endif
1856 mask = ~dirty_flags;
1857 p = phys_ram_dirty + (start >> TARGET_PAGE_BITS);
1858 for(i = 0; i < len; i++)
1859 p[i] &= mask;
1860
1861 /* we modify the TLB cache so that the dirty bit will be set again
1862 when accessing the range */
1863 start1 = start + (unsigned long)phys_ram_base;
1864 for(env = first_cpu; env != NULL; env = env->next_cpu) {
1865 for(i = 0; i < CPU_TLB_SIZE; i++)
1866 tlb_reset_dirty_range(&env->tlb_table[0][i], start1, length);
1867 for(i = 0; i < CPU_TLB_SIZE; i++)
1868 tlb_reset_dirty_range(&env->tlb_table[1][i], start1, length);
1869 #if (NB_MMU_MODES >= 3)
1870 for(i = 0; i < CPU_TLB_SIZE; i++)
1871 tlb_reset_dirty_range(&env->tlb_table[2][i], start1, length);
1872 #if (NB_MMU_MODES == 4)
1873 for(i = 0; i < CPU_TLB_SIZE; i++)
1874 tlb_reset_dirty_range(&env->tlb_table[3][i], start1, length);
1875 #endif
1876 #endif
1877 }
1878 }
1879
1880 int cpu_physical_memory_set_dirty_tracking(int enable)
1881 {
1882 in_migration = enable;
1883 return 0;
1884 }
1885
1886 int cpu_physical_memory_get_dirty_tracking(void)
1887 {
1888 return in_migration;
1889 }
1890
1891 void cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, target_phys_addr_t end_addr)
1892 {
1893 if (kvm_enabled())
1894 kvm_physical_sync_dirty_bitmap(start_addr, end_addr);
1895 }
1896
1897 static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry)
1898 {
1899 ram_addr_t ram_addr;
1900
1901 if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
1902 ram_addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) +
1903 tlb_entry->addend - (unsigned long)phys_ram_base;
1904 if (!cpu_physical_memory_is_dirty(ram_addr)) {
1905 tlb_entry->addr_write |= TLB_NOTDIRTY;
1906 }
1907 }
1908 }
1909
1910 /* update the TLB according to the current state of the dirty bits */
1911 void cpu_tlb_update_dirty(CPUState *env)
1912 {
1913 int i;
1914 for(i = 0; i < CPU_TLB_SIZE; i++)
1915 tlb_update_dirty(&env->tlb_table[0][i]);
1916 for(i = 0; i < CPU_TLB_SIZE; i++)
1917 tlb_update_dirty(&env->tlb_table[1][i]);
1918 #if (NB_MMU_MODES >= 3)
1919 for(i = 0; i < CPU_TLB_SIZE; i++)
1920 tlb_update_dirty(&env->tlb_table[2][i]);
1921 #if (NB_MMU_MODES == 4)
1922 for(i = 0; i < CPU_TLB_SIZE; i++)
1923 tlb_update_dirty(&env->tlb_table[3][i]);
1924 #endif
1925 #endif
1926 }
1927
1928 static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
1929 {
1930 if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY))
1931 tlb_entry->addr_write = vaddr;
1932 }
1933
1934 /* update the TLB corresponding to virtual page vaddr
1935 so that it is no longer dirty */
1936 static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr)
1937 {
1938 int i;
1939
1940 vaddr &= TARGET_PAGE_MASK;
1941 i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
1942 tlb_set_dirty1(&env->tlb_table[0][i], vaddr);
1943 tlb_set_dirty1(&env->tlb_table[1][i], vaddr);
1944 #if (NB_MMU_MODES >= 3)
1945 tlb_set_dirty1(&env->tlb_table[2][i], vaddr);
1946 #if (NB_MMU_MODES == 4)
1947 tlb_set_dirty1(&env->tlb_table[3][i], vaddr);
1948 #endif
1949 #endif
1950 }
1951
1952 /* add a new TLB entry. At most one entry for a given virtual address
1953 is permitted. Return 0 if OK or 2 if the page could not be mapped
1954 (can only happen in non SOFTMMU mode for I/O pages or pages
1955 conflicting with the host address space). */
1956 int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
1957 target_phys_addr_t paddr, int prot,
1958 int mmu_idx, int is_softmmu)
1959 {
1960 PhysPageDesc *p;
1961 unsigned long pd;
1962 unsigned int index;
1963 target_ulong address;
1964 target_ulong code_address;
1965 target_phys_addr_t addend;
1966 int ret;
1967 CPUTLBEntry *te;
1968 CPUWatchpoint *wp;
1969 target_phys_addr_t iotlb;
1970
1971 p = phys_page_find(paddr >> TARGET_PAGE_BITS);
1972 if (!p) {
1973 pd = IO_MEM_UNASSIGNED;
1974 } else {
1975 pd = p->phys_offset;
1976 }
1977 #if defined(DEBUG_TLB)
1978 printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x%08x prot=%x idx=%d smmu=%d pd=0x%08lx\n",
1979 vaddr, (int)paddr, prot, mmu_idx, is_softmmu, pd);
1980 #endif
1981
1982 ret = 0;
1983 address = vaddr;
1984 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
1985 /* IO memory case (romd handled later) */
1986 address |= TLB_MMIO;
1987 }
1988 addend = (unsigned long)phys_ram_base + (pd & TARGET_PAGE_MASK);
1989 if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) {
1990 /* Normal RAM. */
1991 iotlb = pd & TARGET_PAGE_MASK;
1992 if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM)
1993 iotlb |= IO_MEM_NOTDIRTY;
1994 else
1995 iotlb |= IO_MEM_ROM;
1996 } else {
1997 /* IO handlers are currently passed a phsical address.
1998 It would be nice to pass an offset from the base address
1999 of that region. This would avoid having to special case RAM,
2000 and avoid full address decoding in every device.
2001 We can't use the high bits of pd for this because
2002 IO_MEM_ROMD uses these as a ram address. */
2003 iotlb = (pd & ~TARGET_PAGE_MASK);
2004 if (p) {
2005 iotlb += p->region_offset;
2006 } else {
2007 iotlb += paddr;
2008 }
2009 }
2010
2011 code_address = address;
2012 /* Make accesses to pages with watchpoints go via the
2013 watchpoint trap routines. */
2014 TAILQ_FOREACH(wp, &env->watchpoints, entry) {
2015 if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) {
2016 iotlb = io_mem_watch + paddr;
2017 /* TODO: The memory case can be optimized by not trapping
2018 reads of pages with a write breakpoint. */
2019 address |= TLB_MMIO;
2020 }
2021 }
2022
2023 index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
2024 env->iotlb[mmu_idx][index] = iotlb - vaddr;
2025 te = &env->tlb_table[mmu_idx][index];
2026 te->addend = addend - vaddr;
2027 if (prot & PAGE_READ) {
2028 te->addr_read = address;
2029 } else {
2030 te->addr_read = -1;
2031 }
2032
2033 if (prot & PAGE_EXEC) {
2034 te->addr_code = code_address;
2035 } else {
2036 te->addr_code = -1;
2037 }
2038 if (prot & PAGE_WRITE) {
2039 if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM ||
2040 (pd & IO_MEM_ROMD)) {
2041 /* Write access calls the I/O callback. */
2042 te->addr_write = address | TLB_MMIO;
2043 } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM &&
2044 !cpu_physical_memory_is_dirty(pd)) {
2045 te->addr_write = address | TLB_NOTDIRTY;
2046 } else {
2047 te->addr_write = address;
2048 }
2049 } else {
2050 te->addr_write = -1;
2051 }
2052 return ret;
2053 }
2054
2055 #else
2056
2057 void tlb_flush(CPUState *env, int flush_global)
2058 {
2059 }
2060
2061 void tlb_flush_page(CPUState *env, target_ulong addr)
2062 {
2063 }
2064
2065 int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
2066 target_phys_addr_t paddr, int prot,
2067 int mmu_idx, int is_softmmu)
2068 {
2069 return 0;
2070 }
2071
2072 /* dump memory mappings */
2073 void page_dump(FILE *f)
2074 {
2075 unsigned long start, end;
2076 int i, j, prot, prot1;
2077 PageDesc *p;
2078
2079 fprintf(f, "%-8s %-8s %-8s %s\n",
2080 "start", "end", "size", "prot");
2081 start = -1;
2082 end = -1;
2083 prot = 0;
2084 for(i = 0; i <= L1_SIZE; i++) {
2085 if (i < L1_SIZE)
2086 p = l1_map[i];
2087 else
2088 p = NULL;
2089 for(j = 0;j < L2_SIZE; j++) {
2090 if (!p)
2091 prot1 = 0;
2092 else
2093 prot1 = p[j].flags;
2094 if (prot1 != prot) {
2095 end = (i << (32 - L1_BITS)) | (j << TARGET_PAGE_BITS);
2096 if (start != -1) {
2097 fprintf(f, "%08lx-%08lx %08lx %c%c%c\n",
2098 start, end, end - start,
2099 prot & PAGE_READ ? 'r' : '-',
2100 prot & PAGE_WRITE ? 'w' : '-',
2101 prot & PAGE_EXEC ? 'x' : '-');
2102 }
2103 if (prot1 != 0)
2104 start = end;
2105 else
2106 start = -1;
2107 prot = prot1;
2108 }
2109 if (!p)
2110 break;
2111 }
2112 }
2113 }
2114
2115 int page_get_flags(target_ulong address)
2116 {
2117 PageDesc *p;
2118
2119 p = page_find(address >> TARGET_PAGE_BITS);
2120 if (!p)
2121 return 0;
2122 return p->flags;
2123 }
2124
2125 /* modify the flags of a page and invalidate the code if
2126 necessary. The flag PAGE_WRITE_ORG is positionned automatically
2127 depending on PAGE_WRITE */
2128 void page_set_flags(target_ulong start, target_ulong end, int flags)
2129 {
2130 PageDesc *p;
2131 target_ulong addr;
2132
2133 /* mmap_lock should already be held. */
2134 start = start & TARGET_PAGE_MASK;
2135 end = TARGET_PAGE_ALIGN(end);
2136 if (flags & PAGE_WRITE)
2137 flags |= PAGE_WRITE_ORG;
2138 for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) {
2139 p = page_find_alloc(addr >> TARGET_PAGE_BITS);
2140 /* We may be called for host regions that are outside guest
2141 address space. */
2142 if (!p)
2143 return;
2144 /* if the write protection is set, then we invalidate the code
2145 inside */
2146 if (!(p->flags & PAGE_WRITE) &&
2147 (flags & PAGE_WRITE) &&
2148 p->first_tb) {
2149 tb_invalidate_phys_page(addr, 0, NULL);
2150 }
2151 p->flags = flags;
2152 }
2153 }
2154
2155 int page_check_range(target_ulong start, target_ulong len, int flags)
2156 {
2157 PageDesc *p;
2158 target_ulong end;
2159 target_ulong addr;
2160
2161 if (start + len < start)
2162 /* we've wrapped around */
2163 return -1;
2164
2165 end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */
2166 start = start & TARGET_PAGE_MASK;
2167
2168 for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) {
2169 p = page_find(addr >> TARGET_PAGE_BITS);
2170 if( !p )
2171 return -1;
2172 if( !(p->flags & PAGE_VALID) )
2173 return -1;
2174
2175 if ((flags & PAGE_READ) && !(p->flags & PAGE_READ))
2176 return -1;
2177 if (flags & PAGE_WRITE) {
2178 if (!(p->flags & PAGE_WRITE_ORG))
2179 return -1;
2180 /* unprotect the page if it was put read-only because it
2181 contains translated code */
2182 if (!(p->flags & PAGE_WRITE)) {
2183 if (!page_unprotect(addr, 0, NULL))
2184 return -1;
2185 }
2186 return 0;
2187 }
2188 }
2189 return 0;
2190 }
2191
2192 /* called from signal handler: invalidate the code and unprotect the
2193 page. Return TRUE if the fault was succesfully handled. */
2194 int page_unprotect(target_ulong address, unsigned long pc, void *puc)
2195 {
2196 unsigned int page_index, prot, pindex;
2197 PageDesc *p, *p1;
2198 target_ulong host_start, host_end, addr;
2199
2200 /* Technically this isn't safe inside a signal handler. However we
2201 know this only ever happens in a synchronous SEGV handler, so in
2202 practice it seems to be ok. */
2203 mmap_lock();
2204
2205 host_start = address & qemu_host_page_mask;
2206 page_index = host_start >> TARGET_PAGE_BITS;
2207 p1 = page_find(page_index);
2208 if (!p1) {
2209 mmap_unlock();
2210 return 0;
2211 }
2212 host_end = host_start + qemu_host_page_size;
2213 p = p1;
2214 prot = 0;
2215 for(addr = host_start;addr < host_end; addr += TARGET_PAGE_SIZE) {
2216 prot |= p->flags;
2217 p++;
2218 }
2219 /* if the page was really writable, then we change its
2220 protection back to writable */
2221 if (prot & PAGE_WRITE_ORG) {
2222 pindex = (address - host_start) >> TARGET_PAGE_BITS;
2223 if (!(p1[pindex].flags & PAGE_WRITE)) {
2224 mprotect((void *)g2h(host_start), qemu_host_page_size,
2225 (prot & PAGE_BITS) | PAGE_WRITE);
2226 p1[pindex].flags |= PAGE_WRITE;
2227 /* and since the content will be modified, we must invalidate
2228 the corresponding translated code. */
2229 tb_invalidate_phys_page(address, pc, puc);
2230 #ifdef DEBUG_TB_CHECK
2231 tb_invalidate_check(address);
2232 #endif
2233 mmap_unlock();
2234 return 1;
2235 }
2236 }
2237 mmap_unlock();
2238 return 0;
2239 }
2240
2241 static inline void tlb_set_dirty(CPUState *env,
2242 unsigned long addr, target_ulong vaddr)
2243 {
2244 }
2245 #endif /* defined(CONFIG_USER_ONLY) */
2246
2247 #if !defined(CONFIG_USER_ONLY)
2248
2249 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
2250 ram_addr_t memory, ram_addr_t region_offset);
2251 static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
2252 ram_addr_t orig_memory, ram_addr_t region_offset);
2253 #define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \
2254 need_subpage) \
2255 do { \
2256 if (addr > start_addr) \
2257 start_addr2 = 0; \
2258 else { \
2259 start_addr2 = start_addr & ~TARGET_PAGE_MASK; \
2260 if (start_addr2 > 0) \
2261 need_subpage = 1; \
2262 } \
2263 \
2264 if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \
2265 end_addr2 = TARGET_PAGE_SIZE - 1; \
2266 else { \
2267 end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \
2268 if (end_addr2 < TARGET_PAGE_SIZE - 1) \
2269 need_subpage = 1; \
2270 } \
2271 } while (0)
2272
2273 /* register physical memory. 'size' must be a multiple of the target
2274 page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an
2275 io memory page. The address used when calling the IO function is
2276 the offset from the start of the region, plus region_offset. Both
2277 start_region and regon_offset are rounded down to a page boundary
2278 before calculating this offset. This should not be a problem unless
2279 the low bits of start_addr and region_offset differ. */
2280 void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
2281 ram_addr_t size,
2282 ram_addr_t phys_offset,
2283 ram_addr_t region_offset)
2284 {
2285 target_phys_addr_t addr, end_addr;
2286 PhysPageDesc *p;
2287 CPUState *env;
2288 ram_addr_t orig_size = size;
2289 void *subpage;
2290
2291 #ifdef USE_KQEMU
2292 /* XXX: should not depend on cpu context */
2293 env = first_cpu;
2294 if (env->kqemu_enabled) {
2295 kqemu_set_phys_mem(start_addr, size, phys_offset);
2296 }
2297 #endif
2298 if (kvm_enabled())
2299 kvm_set_phys_mem(start_addr, size, phys_offset);
2300
2301 if (phys_offset == IO_MEM_UNASSIGNED) {
2302 region_offset = start_addr;
2303 }
2304 region_offset &= TARGET_PAGE_MASK;
2305 size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
2306 end_addr = start_addr + (target_phys_addr_t)size;
2307 for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) {
2308 p = phys_page_find(addr >> TARGET_PAGE_BITS);
2309 if (p && p->phys_offset != IO_MEM_UNASSIGNED) {
2310 ram_addr_t orig_memory = p->phys_offset;
2311 target_phys_addr_t start_addr2, end_addr2;
2312 int need_subpage = 0;
2313
2314 CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2,
2315 need_subpage);
2316 if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) {
2317 if (!(orig_memory & IO_MEM_SUBPAGE)) {
2318 subpage = subpage_init((addr & TARGET_PAGE_MASK),
2319 &p->phys_offset, orig_memory,
2320 p->region_offset);
2321 } else {
2322 subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK)
2323 >> IO_MEM_SHIFT];
2324 }
2325 subpage_register(subpage, start_addr2, end_addr2, phys_offset,
2326 region_offset);
2327 p->region_offset = 0;
2328 } else {
2329 p->phys_offset = phys_offset;
2330 if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
2331 (phys_offset & IO_MEM_ROMD))
2332 phys_offset += TARGET_PAGE_SIZE;
2333 }
2334 } else {
2335 p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
2336 p->phys_offset = phys_offset;
2337 p->region_offset = region_offset;
2338 if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
2339 (phys_offset & IO_MEM_ROMD)) {
2340 phys_offset += TARGET_PAGE_SIZE;
2341 } else {
2342 target_phys_addr_t start_addr2, end_addr2;
2343 int need_subpage = 0;
2344
2345 CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr,
2346 end_addr2, need_subpage);
2347
2348 if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) {
2349 subpage = subpage_init((addr & TARGET_PAGE_MASK),
2350 &p->phys_offset, IO_MEM_UNASSIGNED,
2351 addr & TARGET_PAGE_MASK);
2352 subpage_register(subpage, start_addr2, end_addr2,
2353 phys_offset, region_offset);
2354 p->region_offset = 0;
2355 }
2356 }
2357 }
2358 region_offset += TARGET_PAGE_SIZE;
2359 }
2360
2361 /* since each CPU stores ram addresses in its TLB cache, we must
2362 reset the modified entries */
2363 /* XXX: slow ! */
2364 for(env = first_cpu; env != NULL; env = env->next_cpu) {
2365 tlb_flush(env, 1);
2366 }
2367 }
2368
2369 /* XXX: temporary until new memory mapping API */
2370 ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr)
2371 {
2372 PhysPageDesc *p;
2373
2374 p = phys_page_find(addr >> TARGET_PAGE_BITS);
2375 if (!p)
2376 return IO_MEM_UNASSIGNED;
2377 return p->phys_offset;
2378 }
2379
2380 void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size)
2381 {
2382 if (kvm_enabled())
2383 kvm_coalesce_mmio_region(addr, size);
2384 }
2385
2386 void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size)
2387 {
2388 if (kvm_enabled())
2389 kvm_uncoalesce_mmio_region(addr, size);
2390 }
2391
2392 /* XXX: better than nothing */
2393 ram_addr_t qemu_ram_alloc(ram_addr_t size)
2394 {
2395 ram_addr_t addr;
2396 if ((phys_ram_alloc_offset + size) > phys_ram_size) {
2397 fprintf(stderr, "Not enough memory (requested_size = %" PRIu64 ", max memory = %" PRIu64 ")\n",
2398 (uint64_t)size, (uint64_t)phys_ram_size);
2399 abort();
2400 }
2401 addr = phys_ram_alloc_offset;
2402 phys_ram_alloc_offset = TARGET_PAGE_ALIGN(phys_ram_alloc_offset + size);
2403 return addr;
2404 }
2405
2406 void qemu_ram_free(ram_addr_t addr)
2407 {
2408 }
2409
2410 static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr)
2411 {
2412 #ifdef DEBUG_UNASSIGNED
2413 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
2414 #endif
2415 #if defined(TARGET_SPARC)
2416 do_unassigned_access(addr, 0, 0, 0, 1);
2417 #endif
2418 return 0;
2419 }
2420
2421 static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr)
2422 {
2423 #ifdef DEBUG_UNASSIGNED
2424 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
2425 #endif
2426 #if defined(TARGET_SPARC)
2427 do_unassigned_access(addr, 0, 0, 0, 2);
2428 #endif
2429 return 0;
2430 }
2431
2432 static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr)
2433 {
2434 #ifdef DEBUG_UNASSIGNED
2435 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
2436 #endif
2437 #if defined(TARGET_SPARC)
2438 do_unassigned_access(addr, 0, 0, 0, 4);
2439 #endif
2440 return 0;
2441 }
2442
2443 static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
2444 {
2445 #ifdef DEBUG_UNASSIGNED
2446 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
2447 #endif
2448 #if defined(TARGET_SPARC)
2449 do_unassigned_access(addr, 1, 0, 0, 1);
2450 #endif
2451 }
2452
2453 static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2454 {
2455 #ifdef DEBUG_UNASSIGNED
2456 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
2457 #endif
2458 #if defined(TARGET_SPARC)
2459 do_unassigned_access(addr, 1, 0, 0, 2);
2460 #endif
2461 }
2462
2463 static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2464 {
2465 #ifdef DEBUG_UNASSIGNED
2466 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
2467 #endif
2468 #if defined(TARGET_SPARC)
2469 do_unassigned_access(addr, 1, 0, 0, 4);
2470 #endif
2471 }
2472
2473 static CPUReadMemoryFunc *unassigned_mem_read[3] = {
2474 unassigned_mem_readb,
2475 unassigned_mem_readw,
2476 unassigned_mem_readl,
2477 };
2478
2479 static CPUWriteMemoryFunc *unassigned_mem_write[3] = {
2480 unassigned_mem_writeb,
2481 unassigned_mem_writew,
2482 unassigned_mem_writel,
2483 };
2484
2485 static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr,
2486 uint32_t val)
2487 {
2488 int dirty_flags;
2489 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2490 if (!(dirty_flags & CODE_DIRTY_FLAG)) {
2491 #if !defined(CONFIG_USER_ONLY)
2492 tb_invalidate_phys_page_fast(ram_addr, 1);
2493 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2494 #endif
2495 }
2496 stb_p(phys_ram_base + ram_addr, val);
2497 #ifdef USE_KQEMU
2498 if (cpu_single_env->kqemu_enabled &&
2499 (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
2500 kqemu_modify_page(cpu_single_env, ram_addr);
2501 #endif
2502 dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2503 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
2504 /* we remove the notdirty callback only if the code has been
2505 flushed */
2506 if (dirty_flags == 0xff)
2507 tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
2508 }
2509
2510 static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr,
2511 uint32_t val)
2512 {
2513 int dirty_flags;
2514 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2515 if (!(dirty_flags & CODE_DIRTY_FLAG)) {
2516 #if !defined(CONFIG_USER_ONLY)
2517 tb_invalidate_phys_page_fast(ram_addr, 2);
2518 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2519 #endif
2520 }
2521 stw_p(phys_ram_base + ram_addr, val);
2522 #ifdef USE_KQEMU
2523 if (cpu_single_env->kqemu_enabled &&
2524 (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
2525 kqemu_modify_page(cpu_single_env, ram_addr);
2526 #endif
2527 dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2528 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
2529 /* we remove the notdirty callback only if the code has been
2530 flushed */
2531 if (dirty_flags == 0xff)
2532 tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
2533 }
2534
2535 static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr,
2536 uint32_t val)
2537 {
2538 int dirty_flags;
2539 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2540 if (!(dirty_flags & CODE_DIRTY_FLAG)) {
2541 #if !defined(CONFIG_USER_ONLY)
2542 tb_invalidate_phys_page_fast(ram_addr, 4);
2543 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2544 #endif
2545 }
2546 stl_p(phys_ram_base + ram_addr, val);
2547 #ifdef USE_KQEMU
2548 if (cpu_single_env->kqemu_enabled &&
2549 (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
2550 kqemu_modify_page(cpu_single_env, ram_addr);
2551 #endif
2552 dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2553 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
2554 /* we remove the notdirty callback only if the code has been
2555 flushed */
2556 if (dirty_flags == 0xff)
2557 tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
2558 }
2559
2560 static CPUReadMemoryFunc *error_mem_read[3] = {
2561 NULL, /* never used */
2562 NULL, /* never used */
2563 NULL, /* never used */
2564 };
2565
2566 static CPUWriteMemoryFunc *notdirty_mem_write[3] = {
2567 notdirty_mem_writeb,
2568 notdirty_mem_writew,
2569 notdirty_mem_writel,
2570 };
2571
2572 /* Generate a debug exception if a watchpoint has been hit. */
2573 static void check_watchpoint(int offset, int len_mask, int flags)
2574 {
2575 CPUState *env = cpu_single_env;
2576 target_ulong pc, cs_base;
2577 TranslationBlock *tb;
2578 target_ulong vaddr;
2579 CPUWatchpoint *wp;
2580 int cpu_flags;
2581
2582 if (env->watchpoint_hit) {
2583 /* We re-entered the check after replacing the TB. Now raise
2584 * the debug interrupt so that is will trigger after the
2585 * current instruction. */
2586 cpu_interrupt(env, CPU_INTERRUPT_DEBUG);
2587 return;
2588 }
2589 vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
2590 TAILQ_FOREACH(wp, &env->watchpoints, entry) {
2591 if ((vaddr == (wp->vaddr & len_mask) ||
2592 (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) {
2593 wp->flags |= BP_WATCHPOINT_HIT;
2594 if (!env->watchpoint_hit) {
2595 env->watchpoint_hit = wp;
2596 tb = tb_find_pc(env->mem_io_pc);
2597 if (!tb) {
2598 cpu_abort(env, "check_watchpoint: could not find TB for "
2599 "pc=%p", (void *)env->mem_io_pc);
2600 }
2601 cpu_restore_state(tb, env, env->mem_io_pc, NULL);
2602 tb_phys_invalidate(tb, -1);
2603 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
2604 env->exception_index = EXCP_DEBUG;
2605 } else {
2606 cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags);
2607 tb_gen_code(env, pc, cs_base, cpu_flags, 1);
2608 }
2609 cpu_resume_from_signal(env, NULL);
2610 }
2611 } else {
2612 wp->flags &= ~BP_WATCHPOINT_HIT;
2613 }
2614 }
2615 }
2616
2617 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2618 so these check for a hit then pass through to the normal out-of-line
2619 phys routines. */
2620 static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr)
2621 {
2622 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ);
2623 return ldub_phys(addr);
2624 }
2625
2626 static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr)
2627 {
2628 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ);
2629 return lduw_phys(addr);
2630 }
2631
2632 static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr)
2633 {
2634 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ);
2635 return ldl_phys(addr);
2636 }
2637
2638 static void watch_mem_writeb(void *opaque, target_phys_addr_t addr,
2639 uint32_t val)
2640 {
2641 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE);
2642 stb_phys(addr, val);
2643 }
2644
2645 static void watch_mem_writew(void *opaque, target_phys_addr_t addr,
2646 uint32_t val)
2647 {
2648 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE);
2649 stw_phys(addr, val);
2650 }
2651
2652 static void watch_mem_writel(void *opaque, target_phys_addr_t addr,
2653 uint32_t val)
2654 {
2655 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE);
2656 stl_phys(addr, val);
2657 }
2658
2659 static CPUReadMemoryFunc *watch_mem_read[3] = {
2660 watch_mem_readb,
2661 watch_mem_readw,
2662 watch_mem_readl,
2663 };
2664
2665 static CPUWriteMemoryFunc *watch_mem_write[3] = {
2666 watch_mem_writeb,
2667 watch_mem_writew,
2668 watch_mem_writel,
2669 };
2670
2671 static inline uint32_t subpage_readlen (subpage_t *mmio, target_phys_addr_t addr,
2672 unsigned int len)
2673 {
2674 uint32_t ret;
2675 unsigned int idx;
2676
2677 idx = SUBPAGE_IDX(addr);
2678 #if defined(DEBUG_SUBPAGE)
2679 printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__,
2680 mmio, len, addr, idx);
2681 #endif
2682 ret = (**mmio->mem_read[idx][len])(mmio->opaque[idx][0][len],
2683 addr + mmio->region_offset[idx][0][len]);
2684
2685 return ret;
2686 }
2687
2688 static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr,
2689 uint32_t value, unsigned int len)
2690 {
2691 unsigned int idx;
2692
2693 idx = SUBPAGE_IDX(addr);
2694 #if defined(DEBUG_SUBPAGE)
2695 printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", __func__,
2696 mmio, len, addr, idx, value);
2697 #endif
2698 (**mmio->mem_write[idx][len])(mmio->opaque[idx][1][len],
2699 addr + mmio->region_offset[idx][1][len],
2700 value);
2701 }
2702
2703 static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr)
2704 {
2705 #if defined(DEBUG_SUBPAGE)
2706 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
2707 #endif
2708
2709 return subpage_readlen(opaque, addr, 0);
2710 }
2711
2712 static void subpage_writeb (void *opaque, target_phys_addr_t addr,
2713 uint32_t value)
2714 {
2715 #if defined(DEBUG_SUBPAGE)
2716 printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
2717 #endif
2718 subpage_writelen(opaque, addr, value, 0);
2719 }
2720
2721 static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr)
2722 {
2723 #if defined(DEBUG_SUBPAGE)
2724 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
2725 #endif
2726
2727 return subpage_readlen(opaque, addr, 1);
2728 }
2729
2730 static void subpage_writew (void *opaque, target_phys_addr_t addr,
2731 uint32_t value)
2732 {
2733 #if defined(DEBUG_SUBPAGE)
2734 printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
2735 #endif
2736 subpage_writelen(opaque, addr, value, 1);
2737 }
2738
2739 static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr)
2740 {
2741 #if defined(DEBUG_SUBPAGE)
2742 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
2743 #endif
2744
2745 return subpage_readlen(opaque, addr, 2);
2746 }
2747
2748 static void subpage_writel (void *opaque,
2749 target_phys_addr_t addr, uint32_t value)
2750 {
2751 #if defined(DEBUG_SUBPAGE)
2752 printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
2753 #endif
2754 subpage_writelen(opaque, addr, value, 2);
2755 }
2756
2757 static CPUReadMemoryFunc *subpage_read[] = {
2758 &subpage_readb,
2759 &subpage_readw,
2760 &subpage_readl,
2761 };
2762
2763 static CPUWriteMemoryFunc *subpage_write[] = {
2764 &subpage_writeb,
2765 &subpage_writew,
2766 &subpage_writel,
2767 };
2768
2769 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
2770 ram_addr_t memory, ram_addr_t region_offset)
2771 {
2772 int idx, eidx;
2773 unsigned int i;
2774
2775 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
2776 return -1;
2777 idx = SUBPAGE_IDX(start);
2778 eidx = SUBPAGE_IDX(end);
2779 #if defined(DEBUG_SUBPAGE)
2780 printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %d\n", __func__,
2781 mmio, start, end, idx, eidx, memory);
2782 #endif
2783 memory >>= IO_MEM_SHIFT;
2784 for (; idx <= eidx; idx++) {
2785 for (i = 0; i < 4; i++) {
2786 if (io_mem_read[memory][i]) {
2787 mmio->mem_read[idx][i] = &io_mem_read[memory][i];
2788 mmio->opaque[idx][0][i] = io_mem_opaque[memory];
2789 mmio->region_offset[idx][0][i] = region_offset;
2790 }
2791 if (io_mem_write[memory][i]) {
2792 mmio->mem_write[idx][i] = &io_mem_write[memory][i];
2793 mmio->opaque[idx][1][i] = io_mem_opaque[memory];
2794 mmio->region_offset[idx][1][i] = region_offset;
2795 }
2796 }
2797 }
2798
2799 return 0;
2800 }
2801
2802 static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
2803 ram_addr_t orig_memory, ram_addr_t region_offset)
2804 {
2805 subpage_t *mmio;
2806 int subpage_memory;
2807
2808 mmio = qemu_mallocz(sizeof(subpage_t));
2809
2810 mmio->base = base;
2811 subpage_memory = cpu_register_io_memory(0, subpage_read, subpage_write, mmio);
2812 #if defined(DEBUG_SUBPAGE)
2813 printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__,
2814 mmio, base, TARGET_PAGE_SIZE, subpage_memory);
2815 #endif
2816 *phys = subpage_memory | IO_MEM_SUBPAGE;
2817 subpage_register(mmio, 0, TARGET_PAGE_SIZE - 1, orig_memory,
2818 region_offset);
2819
2820 return mmio;
2821 }
2822
2823 static int get_free_io_mem_idx(void)
2824 {
2825 int i;
2826
2827 for (i = 0; i<IO_MEM_NB_ENTRIES; i++)
2828 if (!io_mem_used[i]) {
2829 io_mem_used[i] = 1;
2830 return i;
2831 }
2832
2833 return -1;
2834 }
2835
2836 static void io_mem_init(void)
2837 {
2838 int i;
2839
2840 cpu_register_io_memory(IO_MEM_ROM >> IO_MEM_SHIFT, error_mem_read, unassigned_mem_write, NULL);
2841 cpu_register_io_memory(IO_MEM_UNASSIGNED >> IO_MEM_SHIFT, unassigned_mem_read, unassigned_mem_write, NULL);
2842 cpu_register_io_memory(IO_MEM_NOTDIRTY >> IO_MEM_SHIFT, error_mem_read, notdirty_mem_write, NULL);
2843 for (i=0; i<5; i++)
2844 io_mem_used[i] = 1;
2845
2846 io_mem_watch = cpu_register_io_memory(0, watch_mem_read,
2847 watch_mem_write, NULL);
2848 /* alloc dirty bits array */
2849 phys_ram_dirty = qemu_vmalloc(phys_ram_size >> TARGET_PAGE_BITS);
2850 memset(phys_ram_dirty, 0xff, phys_ram_size >> TARGET_PAGE_BITS);
2851 }
2852
2853 /* mem_read and mem_write are arrays of functions containing the
2854 function to access byte (index 0), word (index 1) and dword (index
2855 2). Functions can be omitted with a NULL function pointer. The
2856 registered functions may be modified dynamically later.
2857 If io_index is non zero, the corresponding io zone is
2858 modified. If it is zero, a new io zone is allocated. The return
2859 value can be used with cpu_register_physical_memory(). (-1) is
2860 returned if error. */
2861 int cpu_register_io_memory(int io_index,
2862 CPUReadMemoryFunc **mem_read,
2863 CPUWriteMemoryFunc **mem_write,
2864 void *opaque)
2865 {
2866 int i, subwidth = 0;
2867
2868 if (io_index <= 0) {
2869 io_index = get_free_io_mem_idx();
2870 if (io_index == -1)
2871 return io_index;
2872 } else {
2873 if (io_index >= IO_MEM_NB_ENTRIES)
2874 return -1;
2875 }
2876
2877 for(i = 0;i < 3; i++) {
2878 if (!mem_read[i] || !mem_write[i])
2879 subwidth = IO_MEM_SUBWIDTH;
2880 io_mem_read[io_index][i] = mem_read[i];
2881 io_mem_write[io_index][i] = mem_write[i];
2882 }
2883 io_mem_opaque[io_index] = opaque;
2884 return (io_index << IO_MEM_SHIFT) | subwidth;
2885 }
2886
2887 void cpu_unregister_io_memory(int io_table_address)
2888 {
2889 int i;
2890 int io_index = io_table_address >> IO_MEM_SHIFT;
2891
2892 for (i=0;i < 3; i++) {
2893 io_mem_read[io_index][i] = unassigned_mem_read[i];
2894 io_mem_write[io_index][i] = unassigned_mem_write[i];
2895 }
2896 io_mem_opaque[io_index] = NULL;
2897 io_mem_used[io_index] = 0;
2898 }
2899
2900 CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index)
2901 {
2902 return io_mem_write[io_index >> IO_MEM_SHIFT];
2903 }
2904
2905 CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index)
2906 {
2907 return io_mem_read[io_index >> IO_MEM_SHIFT];
2908 }
2909
2910 #endif /* !defined(CONFIG_USER_ONLY) */
2911
2912 /* physical memory access (slow version, mainly for debug) */
2913 #if defined(CONFIG_USER_ONLY)
2914 void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
2915 int len, int is_write)
2916 {
2917 int l, flags;
2918 target_ulong page;
2919 void * p;
2920
2921 while (len > 0) {
2922 page = addr & TARGET_PAGE_MASK;
2923 l = (page + TARGET_PAGE_SIZE) - addr;
2924 if (l > len)
2925 l = len;
2926 flags = page_get_flags(page);
2927 if (!(flags & PAGE_VALID))
2928 return;
2929 if (is_write) {
2930 if (!(flags & PAGE_WRITE))
2931 return;
2932 /* XXX: this code should not depend on lock_user */
2933 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
2934 /* FIXME - should this return an error rather than just fail? */
2935 return;
2936 memcpy(p, buf, l);
2937 unlock_user(p, addr, l);
2938 } else {
2939 if (!(flags & PAGE_READ))
2940 return;
2941 /* XXX: this code should not depend on lock_user */
2942 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
2943 /* FIXME - should this return an error rather than just fail? */
2944 return;
2945 memcpy(buf, p, l);
2946 unlock_user(p, addr, 0);
2947 }
2948 len -= l;
2949 buf += l;
2950 addr += l;
2951 }
2952 }
2953
2954 #else
2955 void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
2956 int len, int is_write)
2957 {
2958 int l, io_index;
2959 uint8_t *ptr;
2960 uint32_t val;
2961 target_phys_addr_t page;
2962 unsigned long pd;
2963 PhysPageDesc *p;
2964
2965 while (len > 0) {
2966 page = addr & TARGET_PAGE_MASK;
2967 l = (page + TARGET_PAGE_SIZE) - addr;
2968 if (l > len)
2969 l = len;
2970 p = phys_page_find(page >> TARGET_PAGE_BITS);
2971 if (!p) {
2972 pd = IO_MEM_UNASSIGNED;
2973 } else {
2974 pd = p->phys_offset;
2975 }
2976
2977 if (is_write) {
2978 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
2979 target_phys_addr_t addr1 = addr;
2980 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
2981 if (p)
2982 addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
2983 /* XXX: could force cpu_single_env to NULL to avoid
2984 potential bugs */
2985 if (l >= 4 && ((addr1 & 3) == 0)) {
2986 /* 32 bit write access */
2987 val = ldl_p(buf);
2988 io_mem_write[io_index][2](io_mem_opaque[io_index], addr1, val);
2989 l = 4;
2990 } else if (l >= 2 && ((addr1 & 1) == 0)) {
2991 /* 16 bit write access */
2992 val = lduw_p(buf);
2993 io_mem_write[io_index][1](io_mem_opaque[io_index], addr1, val);
2994 l = 2;
2995 } else {
2996 /* 8 bit write access */
2997 val = ldub_p(buf);
2998 io_mem_write[io_index][0](io_mem_opaque[io_index], addr1, val);
2999 l = 1;
3000 }
3001 } else {
3002 unsigned long addr1;
3003 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3004 /* RAM case */
3005 ptr = phys_ram_base + addr1;
3006 memcpy(ptr, buf, l);
3007 if (!cpu_physical_memory_is_dirty(addr1)) {
3008 /* invalidate code */
3009 tb_invalidate_phys_page_range(addr1, addr1 + l, 0);
3010 /* set dirty bit */
3011 phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
3012 (0xff & ~CODE_DIRTY_FLAG);
3013 }
3014 }
3015 } else {
3016 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
3017 !(pd & IO_MEM_ROMD)) {
3018 target_phys_addr_t addr1 = addr;
3019 /* I/O case */
3020 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3021 if (p)
3022 addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
3023 if (l >= 4 && ((addr1 & 3) == 0)) {
3024 /* 32 bit read access */
3025 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr1);
3026 stl_p(buf, val);
3027 l = 4;
3028 } else if (l >= 2 && ((addr1 & 1) == 0)) {
3029 /* 16 bit read access */
3030 val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr1);
3031 stw_p(buf, val);
3032 l = 2;
3033 } else {
3034 /* 8 bit read access */
3035 val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr1);
3036 stb_p(buf, val);
3037 l = 1;
3038 }
3039 } else {
3040 /* RAM case */
3041 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
3042 (addr & ~TARGET_PAGE_MASK);
3043 memcpy(buf, ptr, l);
3044 }
3045 }
3046 len -= l;
3047 buf += l;
3048 addr += l;
3049 }
3050 }
3051
3052 /* used for ROM loading : can write in RAM and ROM */
3053 void cpu_physical_memory_write_rom(target_phys_addr_t addr,
3054 const uint8_t *buf, int len)
3055 {
3056 int l;
3057 uint8_t *ptr;
3058 target_phys_addr_t page;
3059 unsigned long pd;
3060 PhysPageDesc *p;
3061
3062 while (len > 0) {
3063 page = addr & TARGET_PAGE_MASK;
3064 l = (page + TARGET_PAGE_SIZE) - addr;
3065 if (l > len)
3066 l = len;
3067 p = phys_page_find(page >> TARGET_PAGE_BITS);
3068 if (!p) {
3069 pd = IO_MEM_UNASSIGNED;
3070 } else {
3071 pd = p->phys_offset;
3072 }
3073
3074 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM &&
3075 (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM &&
3076 !(pd & IO_MEM_ROMD)) {
3077 /* do nothing */
3078 } else {
3079 unsigned long addr1;
3080 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3081 /* ROM/RAM case */
3082 ptr = phys_ram_base + addr1;
3083 memcpy(ptr, buf, l);
3084 }
3085 len -= l;
3086 buf += l;
3087 addr += l;
3088 }
3089 }
3090
3091 typedef struct {
3092 void *buffer;
3093 target_phys_addr_t addr;
3094 target_phys_addr_t len;
3095 } BounceBuffer;
3096
3097 static BounceBuffer bounce;
3098
3099 typedef struct MapClient {
3100 void *opaque;
3101 void (*callback)(void *opaque);
3102 LIST_ENTRY(MapClient) link;
3103 } MapClient;
3104
3105 static LIST_HEAD(map_client_list, MapClient) map_client_list
3106 = LIST_HEAD_INITIALIZER(map_client_list);
3107
3108 void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque))
3109 {
3110 MapClient *client = qemu_malloc(sizeof(*client));
3111
3112 client->opaque = opaque;
3113 client->callback = callback;
3114 LIST_INSERT_HEAD(&map_client_list, client, link);
3115 return client;
3116 }
3117
3118 void cpu_unregister_map_client(void *_client)
3119 {
3120 MapClient *client = (MapClient *)_client;
3121
3122 LIST_REMOVE(client, link);
3123 }
3124
3125 static void cpu_notify_map_clients(void)
3126 {
3127 MapClient *client;
3128
3129 while (!LIST_EMPTY(&map_client_list)) {
3130 client = LIST_FIRST(&map_client_list);
3131 client->callback(client->opaque);
3132 LIST_REMOVE(client, link);
3133 }
3134 }
3135
3136 /* Map a physical memory region into a host virtual address.
3137 * May map a subset of the requested range, given by and returned in *plen.
3138 * May return NULL if resources needed to perform the mapping are exhausted.
3139 * Use only for reads OR writes - not for read-modify-write operations.
3140 * Use cpu_register_map_client() to know when retrying the map operation is
3141 * likely to succeed.
3142 */
3143 void *cpu_physical_memory_map(target_phys_addr_t addr,
3144 target_phys_addr_t *plen,
3145 int is_write)
3146 {
3147 target_phys_addr_t len = *plen;
3148 target_phys_addr_t done = 0;
3149 int l;
3150 uint8_t *ret = NULL;
3151 uint8_t *ptr;
3152 target_phys_addr_t page;
3153 unsigned long pd;
3154 PhysPageDesc *p;
3155 unsigned long addr1;
3156
3157 while (len > 0) {
3158 page = addr & TARGET_PAGE_MASK;
3159 l = (page + TARGET_PAGE_SIZE) - addr;
3160 if (l > len)
3161 l = len;
3162 p = phys_page_find(page >> TARGET_PAGE_BITS);
3163 if (!p) {
3164 pd = IO_MEM_UNASSIGNED;
3165 } else {
3166 pd = p->phys_offset;
3167 }
3168
3169 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
3170 if (done || bounce.buffer) {
3171 break;
3172 }
3173 bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, TARGET_PAGE_SIZE);
3174 bounce.addr = addr;
3175 bounce.len = l;
3176 if (!is_write) {
3177 cpu_physical_memory_rw(addr, bounce.buffer, l, 0);
3178 }
3179 ptr = bounce.buffer;
3180 } else {
3181 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3182 ptr = phys_ram_base + addr1;
3183 }
3184 if (!done) {
3185 ret = ptr;
3186 } else if (ret + done != ptr) {
3187 break;
3188 }
3189
3190 len -= l;
3191 addr += l;
3192 done += l;
3193 }
3194 *plen = done;
3195 return ret;
3196 }
3197
3198 /* Unmaps a memory region previously mapped by cpu_physical_memory_map().
3199 * Will also mark the memory as dirty if is_write == 1. access_len gives
3200 * the amount of memory that was actually read or written by the caller.
3201 */
3202 void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
3203 int is_write, target_phys_addr_t access_len)
3204 {
3205 if (buffer != bounce.buffer) {
3206 if (is_write) {
3207 unsigned long addr1 = (uint8_t *)buffer - phys_ram_base;
3208 while (access_len) {
3209 unsigned l;
3210 l = TARGET_PAGE_SIZE;
3211 if (l > access_len)
3212 l = access_len;
3213 if (!cpu_physical_memory_is_dirty(addr1)) {
3214 /* invalidate code */
3215 tb_invalidate_phys_page_range(addr1, addr1 + l, 0);
3216 /* set dirty bit */
3217 phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
3218 (0xff & ~CODE_DIRTY_FLAG);
3219 }
3220 addr1 += l;
3221 access_len -= l;
3222 }
3223 }
3224 return;
3225 }
3226 if (is_write) {
3227 cpu_physical_memory_write(bounce.addr, bounce.buffer, access_len);
3228 }
3229 qemu_free(bounce.buffer);
3230 bounce.buffer = NULL;
3231 cpu_notify_map_clients();
3232 }
3233
3234 /* warning: addr must be aligned */
3235 uint32_t ldl_phys(target_phys_addr_t addr)
3236 {
3237 int io_index;
3238 uint8_t *ptr;
3239 uint32_t val;
3240 unsigned long pd;
3241 PhysPageDesc *p;
3242
3243 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3244 if (!p) {
3245 pd = IO_MEM_UNASSIGNED;
3246 } else {
3247 pd = p->phys_offset;
3248 }
3249
3250 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
3251 !(pd & IO_MEM_ROMD)) {
3252 /* I/O case */
3253 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3254 if (p)
3255 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
3256 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
3257 } else {
3258 /* RAM case */
3259 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
3260 (addr & ~TARGET_PAGE_MASK);
3261 val = ldl_p(ptr);
3262 }
3263 return val;
3264 }
3265
3266 /* warning: addr must be aligned */
3267 uint64_t ldq_phys(target_phys_addr_t addr)
3268 {
3269 int io_index;
3270 uint8_t *ptr;
3271 uint64_t val;
3272 unsigned long pd;
3273 PhysPageDesc *p;
3274
3275 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3276 if (!p) {
3277 pd = IO_MEM_UNASSIGNED;
3278 } else {
3279 pd = p->phys_offset;
3280 }
3281
3282 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
3283 !(pd & IO_MEM_ROMD)) {
3284 /* I/O case */
3285 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3286 if (p)
3287 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
3288 #ifdef TARGET_WORDS_BIGENDIAN
3289 val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32;
3290 val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4);
3291 #else
3292 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
3293 val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32;
3294 #endif
3295 } else {
3296 /* RAM case */
3297 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
3298 (addr & ~TARGET_PAGE_MASK);
3299 val = ldq_p(ptr);
3300 }
3301 return val;
3302 }
3303
3304 /* XXX: optimize */
3305 uint32_t ldub_phys(target_phys_addr_t addr)
3306 {
3307 uint8_t val;
3308 cpu_physical_memory_read(addr, &val, 1);
3309 return val;
3310 }
3311
3312 /* XXX: optimize */
3313 uint32_t lduw_phys(target_phys_addr_t addr)
3314 {
3315 uint16_t val;
3316 cpu_physical_memory_read(addr, (uint8_t *)&val, 2);
3317 return tswap16(val);
3318 }
3319
3320 /* warning: addr must be aligned. The ram page is not masked as dirty
3321 and the code inside is not invalidated. It is useful if the dirty
3322 bits are used to track modified PTEs */
3323 void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
3324 {
3325 int io_index;
3326 uint8_t *ptr;
3327 unsigned long pd;
3328 PhysPageDesc *p;
3329
3330 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3331 if (!p) {
3332 pd = IO_MEM_UNASSIGNED;
3333 } else {
3334 pd = p->phys_offset;
3335 }
3336
3337 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
3338 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3339 if (p)
3340 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
3341 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3342 } else {
3343 unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3344 ptr = phys_ram_base + addr1;
3345 stl_p(ptr, val);
3346
3347 if (unlikely(in_migration)) {
3348 if (!cpu_physical_memory_is_dirty(addr1)) {
3349 /* invalidate code */
3350 tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
3351 /* set dirty bit */
3352 phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
3353 (0xff & ~CODE_DIRTY_FLAG);
3354 }
3355 }
3356 }
3357 }
3358
3359 void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
3360 {
3361 int io_index;
3362 uint8_t *ptr;
3363 unsigned long pd;
3364 PhysPageDesc *p;
3365
3366 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3367 if (!p) {
3368 pd = IO_MEM_UNASSIGNED;
3369 } else {
3370 pd = p->phys_offset;
3371 }
3372
3373 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
3374 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3375 if (p)
3376 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
3377 #ifdef TARGET_WORDS_BIGENDIAN
3378 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32);
3379 io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val);
3380 #else
3381 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3382 io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32);
3383 #endif
3384 } else {
3385 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
3386 (addr & ~TARGET_PAGE_MASK);
3387 stq_p(ptr, val);
3388 }
3389 }
3390
3391 /* warning: addr must be aligned */
3392 void stl_phys(target_phys_addr_t addr, uint32_t val)
3393 {
3394 int io_index;
3395 uint8_t *ptr;
3396 unsigned long pd;
3397 PhysPageDesc *p;
3398
3399 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3400 if (!p) {
3401 pd = IO_MEM_UNASSIGNED;
3402 } else {
3403 pd = p->phys_offset;
3404 }
3405
3406 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
3407 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3408 if (p)
3409 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
3410 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3411 } else {
3412 unsigned long addr1;
3413 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3414 /* RAM case */
3415 ptr = phys_ram_base + addr1;
3416 stl_p(ptr, val);
3417 if (!cpu_physical_memory_is_dirty(addr1)) {
3418 /* invalidate code */
3419 tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
3420 /* set dirty bit */
3421 phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
3422 (0xff & ~CODE_DIRTY_FLAG);
3423 }
3424 }
3425 }
3426
3427 /* XXX: optimize */
3428 void stb_phys(target_phys_addr_t addr, uint32_t val)
3429 {
3430 uint8_t v = val;
3431 cpu_physical_memory_write(addr, &v, 1);
3432 }
3433
3434 /* XXX: optimize */
3435 void stw_phys(target_phys_addr_t addr, uint32_t val)
3436 {
3437 uint16_t v = tswap16(val);
3438 cpu_physical_memory_write(addr, (const uint8_t *)&v, 2);
3439 }
3440
3441 /* XXX: optimize */
3442 void stq_phys(target_phys_addr_t addr, uint64_t val)
3443 {
3444 val = tswap64(val);
3445 cpu_physical_memory_write(addr, (const uint8_t *)&val, 8);
3446 }
3447
3448 #endif
3449
3450 /* virtual memory access for debug */
3451 int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
3452 uint8_t *buf, int len, int is_write)
3453 {
3454 int l;
3455 target_phys_addr_t phys_addr;
3456 target_ulong page;
3457
3458 while (len > 0) {
3459 page = addr & TARGET_PAGE_MASK;
3460 phys_addr = cpu_get_phys_page_debug(env, page);
3461 /* if no physical page mapped, return an error */
3462 if (phys_addr == -1)
3463 return -1;
3464 l = (page + TARGET_PAGE_SIZE) - addr;
3465 if (l > len)
3466 l = len;
3467 cpu_physical_memory_rw(phys_addr + (addr & ~TARGET_PAGE_MASK),
3468 buf, l, is_write);
3469 len -= l;
3470 buf += l;
3471 addr += l;
3472 }
3473 return 0;
3474 }
3475
3476 /* in deterministic execution mode, instructions doing device I/Os
3477 must be at the end of the TB */
3478 void cpu_io_recompile(CPUState *env, void *retaddr)
3479 {
3480 TranslationBlock *tb;
3481 uint32_t n, cflags;
3482 target_ulong pc, cs_base;
3483 uint64_t flags;
3484
3485 tb = tb_find_pc((unsigned long)retaddr);
3486 if (!tb) {
3487 cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p",
3488 retaddr);
3489 }
3490 n = env->icount_decr.u16.low + tb->icount;
3491 cpu_restore_state(tb, env, (unsigned long)retaddr, NULL);
3492 /* Calculate how many instructions had been executed before the fault
3493 occurred. */
3494 n = n - env->icount_decr.u16.low;
3495 /* Generate a new TB ending on the I/O insn. */
3496 n++;
3497 /* On MIPS and SH, delay slot instructions can only be restarted if
3498 they were already the first instruction in the TB. If this is not
3499 the first instruction in a TB then re-execute the preceding
3500 branch. */
3501 #if defined(TARGET_MIPS)
3502 if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) {
3503 env->active_tc.PC -= 4;
3504 env->icount_decr.u16.low++;
3505 env->hflags &= ~MIPS_HFLAG_BMASK;
3506 }
3507 #elif defined(TARGET_SH4)
3508 if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0
3509 && n > 1) {
3510 env->pc -= 2;
3511 env->icount_decr.u16.low++;
3512 env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
3513 }
3514 #endif
3515 /* This should never happen. */
3516 if (n > CF_COUNT_MASK)
3517 cpu_abort(env, "TB too big during recompile");
3518
3519 cflags = n | CF_LAST_IO;
3520 pc = tb->pc;
3521 cs_base = tb->cs_base;
3522 flags = tb->flags;
3523 tb_phys_invalidate(tb, -1);
3524 /* FIXME: In theory this could raise an exception. In practice
3525 we have already translated the block once so it's probably ok. */
3526 tb_gen_code(env, pc, cs_base, flags, cflags);
3527 /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not
3528 the first in the TB) then we end up generating a whole new TB and
3529 repeating the fault, which is horribly inefficient.
3530 Better would be to execute just this insn uncached, or generate a
3531 second new TB. */
3532 cpu_resume_from_signal(env, NULL);
3533 }
3534
3535 void dump_exec_info(FILE *f,
3536 int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
3537 {
3538 int i, target_code_size, max_target_code_size;
3539 int direct_jmp_count, direct_jmp2_count, cross_page;
3540 TranslationBlock *tb;
3541
3542 target_code_size = 0;
3543 max_target_code_size = 0;
3544 cross_page = 0;
3545 direct_jmp_count = 0;
3546 direct_jmp2_count = 0;
3547 for(i = 0; i < nb_tbs; i++) {
3548 tb = &tbs[i];
3549 target_code_size += tb->size;
3550 if (tb->size > max_target_code_size)
3551 max_target_code_size = tb->size;
3552 if (tb->page_addr[1] != -1)
3553 cross_page++;
3554 if (tb->tb_next_offset[0] != 0xffff) {
3555 direct_jmp_count++;
3556 if (tb->tb_next_offset[1] != 0xffff) {
3557 direct_jmp2_count++;
3558 }
3559 }
3560 }
3561 /* XXX: avoid using doubles ? */
3562 cpu_fprintf(f, "Translation buffer state:\n");
3563 cpu_fprintf(f, "gen code size %ld/%ld\n",
3564 code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size);
3565 cpu_fprintf(f, "TB count %d/%d\n",
3566 nb_tbs, code_gen_max_blocks);
3567 cpu_fprintf(f, "TB avg target size %d max=%d bytes\n",
3568 nb_tbs ? target_code_size / nb_tbs : 0,
3569 max_target_code_size);
3570 cpu_fprintf(f, "TB avg host size %d bytes (expansion ratio: %0.1f)\n",
3571 nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0,
3572 target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0);
3573 cpu_fprintf(f, "cross page TB count %d (%d%%)\n",
3574 cross_page,
3575 nb_tbs ? (cross_page * 100) / nb_tbs : 0);
3576 cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n",
3577 direct_jmp_count,
3578 nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0,
3579 direct_jmp2_count,
3580 nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0);
3581 cpu_fprintf(f, "\nStatistics:\n");
3582 cpu_fprintf(f, "TB flush count %d\n", tb_flush_count);
3583 cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count);
3584 cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count);
3585 tcg_dump_info(f, cpu_fprintf);
3586 }
3587
3588 #if !defined(CONFIG_USER_ONLY)
3589
3590 #define MMUSUFFIX _cmmu
3591 #define GETPC() NULL
3592 #define env cpu_single_env
3593 #define SOFTMMU_CODE_ACCESS
3594
3595 #define SHIFT 0
3596 #include "softmmu_template.h"
3597
3598 #define SHIFT 1
3599 #include "softmmu_template.h"
3600
3601 #define SHIFT 2
3602 #include "softmmu_template.h"
3603
3604 #define SHIFT 3
3605 #include "softmmu_template.h"
3606
3607 #undef env
3608
3609 #endif