hw/s3c.h

   1 /*
   2  * Samsung S3C2410A RISC Microprocessor support (ARM920T based SoC).
   3  *
   4  * Copyright (c) 2007 OpenMoko, Inc.
   5  * Author: Andrzej Zaborowski <andrew@openedhand.com>
   6  *
   7  * This code is licenced under the GNU GPL v2.
   8  */
   9 #ifndef S3C_H
  10 # define S3C_H  "s3c.h"
  11
  12 # include "qemu-common.h"
  13 # include "flash.h"
  14 # include "sd.h"
  15
  16 #define S3C_CPU_2410    0x32410002
  17 #define S3C_CPU_2440    0x32440001
  18
  19 /* Interrupt numbers */
  20 # define S3C_PIC_EINT0  0
  21 # define S3C_PIC_EINT1  1
  22 # define S3C_PIC_EINT2  2
  23 # define S3C_PIC_EINT3  3
  24 # define S3C_PIC_EINT4  4
  25 # define S3C_PIC_EINT8  5
  26 # define S3C_PIC_WDT    9
  27 # define S3C_PIC_TIMER0 10
  28 # define S3C_PIC_TIMER1 11
  29 # define S3C_PIC_TIMER2 12
  30 # define S3C_PIC_TIMER3 13
  31 # define S3C_PIC_TIMER4 14
  32 # define S3C_PIC_UART2  15
  33 # define S3C_PIC_LCD    16
  34 # define S3C_PIC_DMA0   17
  35 # define S3C_PIC_DMA1   18
  36 # define S3C_PIC_DMA2   19
  37 # define S3C_PIC_DMA3   20
  38 # define S3C_PIC_SDI    21
  39 # define S3C_PIC_SPI0   22
  40 # define S3C_PIC_UART1  23
  41 # define S3C_PIC_USBD   25
  42 # define S3C_PIC_USBH   26
  43 # define S3C_PIC_IIC    27
  44 # define S3C_PIC_UART0  28
  45 # define S3C_PIC_SPI1   29
  46 # define S3C_PIC_RTC    30
  47 # define S3C_PIC_ADC    31
  48 /* "Sub source" interrupt numbers */
  49 # define S3C_PICS_RXD0  32
  50 # define S3C_PICS_TXD0  33
  51 # define S3C_PICS_ERR0  34
  52 # define S3C_PICS_RXD1  35
  53 # define S3C_PICS_TXD1  36
  54 # define S3C_PICS_ERR1  37
  55 # define S3C_PICS_RXD2  38
  56 # define S3C_PICS_TXD2  39
  57 # define S3C_PICS_ERR2  40
  58 # define S3C_PICS_TC    41
  59 # define S3C_PICS_ADC   42
  60
  61 # define S3C_PIC_MAX    43
  62 /* External interrupt numbers */
  63 # define S3C_EINT(n)    ((n >= 8) ? (6 << 5) | (n - 8) : (5 << 5) | n)
  64
  65 /* DMA requests */
  66 # define S3C_RQ_nXDREQ0 0x00
  67 # define S3C_RQ_nXDREQ1 0x10
  68 # define S3C_RQ_I2SSDO  0x20
  69 # define S3C_RQ_UART2   0x30
  70 # define S3C_RQ_UART0   0x01
  71 # define S3C_RQ_UART1   0x11
  72 # define S3C_RQ_I2SSDI0 0x21
  73 # define S3C_RQ_SDI0    0x31
  74 # define S3C_RQ_SDI1    0x02
  75 # define S3C_RQ_I2SSDI1 0x12
  76 # define S3C_RQ_SDI2    0x22
  77 # define S3C_RQ_SPI1    0x32
  78 # define S3C_RQ_TIMER0  0x03
  79 # define S3C_RQ_SPI0    0x13
  80 # define S3C_RQ_TIMER1  0x23
  81 # define S3C_RQ_TIMER2  0x33
  82 # define S3C_RQ_USB_EP1 0x04
  83 # define S3C_RQ_USB_EP2 0x14
  84 # define S3C_RQ_USB_EP3 0x24
  85 # define S3C_RQ_USB_EP4 0x34
  86
  87 # define S3C_RQ_MAX     0x35
  88
  89 /* I/O port numbers */
  90 # define S3C_GP(b, n)   (((b) << 5) | n)
  91 # define S3C_GPA(n)     S3C_GP(0, n)
  92 # define S3C_GPB(n)     S3C_GP(1, n)
  93 # define S3C_GPC(n)     S3C_GP(2, n)
  94 # define S3C_GPD(n)     S3C_GP(3, n)
  95 # define S3C_GPE(n)     S3C_GP(4, n)
  96 # define S3C_GPF(n)     S3C_GP(5, n)
  97 # define S3C_GPG(n)     S3C_GP(6, n)
  98 # define S3C_GPH(n)     S3C_GP(7, n)
  99 # define S3C_GP_MAX     S3C_GP(8, 0)
 100
 101 # define S3C_RAM_BASE   0x30000000
 102 # define S3C_SRAM_BASE_NORBOOT  0x40000000
 103 # define S3C_SRAM_BASE_NANDBOOT 0x00000000
 104 # define S3C_SRAM_SIZE  0x00001000
 105
 106 # define S3C_PCLK_FREQ  66500000        /* Hz */
 107 # define S3C_XTAL_FREQ  32768           /* Hz */
 108
 109 /* s3c2410.c */
 110 struct s3c_pic_state_s;
 111 struct s3c_pic_state_s *s3c_pic_init(target_phys_addr_t base,
 112                 qemu_irq *arm_pic);
 113 qemu_irq *s3c_pic_get(struct s3c_pic_state_s *s);
 114
 115 struct s3c_dma_state_s;
 116 struct s3c_dma_state_s *s3c_dma_init(target_phys_addr_t base, qemu_irq *pic);
 117 qemu_irq *s3c_dma_get(struct s3c_dma_state_s *s);
 118
 119 /* GPIO TODO: remove this out, replace with qemu_irq or sumpthin */
 120 typedef void (*gpio_handler_t)(int line, int level, void *opaque);
 121
 122 struct s3c_timers_state_s;
 123 struct s3c_timers_state_s *s3c_timers_init(target_phys_addr_t base,
 124                 qemu_irq *pic, qemu_irq *dma);
 125 void s3c_timers_cmp_handler_set(void *opaque, int line,
 126                 gpio_handler_t handler, void *cmp_opaque);
 127
 128 struct s3c_uart_state_s;
 129 struct s3c_uart_state_s *s3c_uart_init(target_phys_addr_t base,
 130                 qemu_irq *irqs, qemu_irq *dma);
 131 void s3c_uart_attach(struct s3c_uart_state_s *s, CharDriverState *chr);
 132
 133 struct s3c_adc_state_s;
 134 struct s3c_adc_state_s *s3c_adc_init(target_phys_addr_t base, qemu_irq irq,
 135                 qemu_irq tcirq);
 136 void s3c_adc_setscale(struct s3c_adc_state_s *adc, const int m[]);
 137
 138 struct s3c_i2c_state_s;
 139 struct s3c_i2c_state_s *s3c_i2c_init(target_phys_addr_t base, qemu_irq irq);
 140 i2c_bus *s3c_i2c_bus(struct s3c_i2c_state_s *s);
 141
 142 struct s3c_i2s_state_s;
 143 struct s3c_i2s_state_s *s3c_i2s_init(target_phys_addr_t base, qemu_irq *dma);
 144
 145 struct s3c_wdt_state_s;
 146 struct s3c_wdt_state_s *s3c_wdt_init(target_phys_addr_t base, qemu_irq irq);
 147
 148 /* s3c24xx_gpio.c */
 149 struct s3c_gpio_state_s;
 150 struct s3c_gpio_state_s *s3c_gpio_init(target_phys_addr_t base, qemu_irq *pic, uint32_t cpu_id);
 151 qemu_irq *s3c_gpio_in_get(struct s3c_gpio_state_s *s);
 152 void s3c_gpio_out_set(struct s3c_gpio_state_s *s, int line, qemu_irq handler);
 153 void s3c_gpio_setpwrstat(struct s3c_gpio_state_s *s, int stat);
 154 void s3c_gpio_reset(struct s3c_gpio_state_s *s);
 155
 156 /* s3c24xx_lcd.c */
 157 struct s3c_lcd_state_s;
 158 struct s3c_lcd_state_s *s3c_lcd_init(target_phys_addr_t base,
 159                 qemu_irq irq);
 160 void s3c_lcd_reset(struct s3c_lcd_state_s *s);
 161
 162 /* s3c24xx_mmci.c */
 163 struct s3c_mmci_state_s;
 164 struct s3c_mmci_state_s *s3c_mmci_init(target_phys_addr_t base, uint16_t model,
 165                 SDState *mmc, qemu_irq irq, qemu_irq *dma);
 166 void s3c_mmci_reset(struct s3c_mmci_state_s *s);
 167
 168 /* s3c24xx_rtc.c */
 169 struct s3c_rtc_state_s;
 170 struct s3c_rtc_state_s *s3c_rtc_init(target_phys_addr_t base, qemu_irq irq);
 171 void s3c_rtc_reset(struct s3c_rtc_state_s *s);
 172
 173 /* s3c24xx_udc.c */
 174 struct s3c_udc_state_s;
 175 struct s3c_udc_state_s *s3c_udc_init(target_phys_addr_t base, qemu_irq irq,
 176                 qemu_irq *dma);
 177 void s3c_udc_reset(struct s3c_udc_state_s *s);
 178
 179 struct s3c_nand_driver_s {
 180         void (*reset)(void * opaque);
 181         void (*setwp)(void * opaque, int wp);
 182         void (*reg)(void * opaque, struct nand_flash_s *chip);
 183 };
 184
 185 /* s3c2410_nand.c */
 186 struct s3c_nand_driver_s * s3c2410_nand_init(void);
 187 /* s3c2440_nand.c */
 188 struct s3c_nand_driver_s * s3c2440_nand_init(void);
 189
 190 /* s3c2410.c */
 191 struct s3c_spi_state_s;
 192 struct s3c_spi_state_s *s3c_spi_init(target_phys_addr_t base,
 193                 qemu_irq irq0, qemu_irq drq0, qemu_irq irq1, qemu_irq drq1,
 194                 struct s3c_gpio_state_s *gpio);
 195 void s3c_spi_attach(struct s3c_spi_state_s *s, int ch,
 196                 uint8_t (*txrx)(void *opaque, uint8_t value),
 197                 uint8_t (*btxrx)(void *opaque, uint8_t value), void *opaque);
 198
 199 struct s3c_state_s {
 200     CPUState *env;
 201     uint32_t cpu_id;
 202     qemu_irq *irq;
 203     qemu_irq *drq;
 204     struct s3c_pic_state_s *pic;
 205     struct s3c_dma_state_s *dma;
 206     struct s3c_gpio_state_s *io;
 207     struct s3c_lcd_state_s *lcd;
 208     struct s3c_timers_state_s *timers;
 209     struct s3c_uart_state_s *uart[3];
 210     struct s3c_mmci_state_s *mmci;
 211     struct s3c_adc_state_s *adc;
 212     struct s3c_i2c_state_s *i2c;
 213     struct s3c_i2s_state_s *i2s;
 214     struct s3c_rtc_state_s *rtc;
 215     struct s3c_spi_state_s *spi;
 216     struct s3c_udc_state_s *udc;
 217     struct s3c_wdt_state_s *wdt;
 218     struct s3c_nand_driver_s *nand;
 219
 220     /* Memory controller */
 221     target_phys_addr_t mc_base;
 222     uint32_t mc_regs[13];
 223
 224     /* Clock & power management */
 225     target_phys_addr_t clkpwr_base;
 226     uint32_t clkpwr_regs[6 + 1];        // 6 2410. 1 2440
 227 };
 228
 229 /* s3c2410.c */
 230 struct s3c_state_s *s3c24xx_init(uint32_t cpu_id, unsigned int sdram_size, uint32_t sram_address,
 231                 SDState *mmc);
 232
 233
 234 struct s3c_i2s_state_s { /* XXX move to .c */
 235     target_phys_addr_t base;
 236     qemu_irq *dma;
 237     void (*data_req)(void *, int, int);
 238
 239     uint16_t control;
 240     uint16_t mode;
 241     uint16_t prescaler;
 242     uint16_t fcontrol;
 243
 244     int tx_en;
 245     int rx_en;
 246     int tx_len;
 247     int rx_len;
 248     void (*codec_out)(void *, uint32_t);
 249     uint32_t (*codec_in)(void *);
 250     void *opaque;
 251
 252     uint16_t buffer;
 253     int cycle;
 254 };
 255
 256 #endif  /* S3C_H */