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[S3C] Pass SRAM mapping address as parameter
[sniper_test.git] / hw / s3c2410.c
blobded4a50a6098cad6735cfc7c9efd7ab221cc0fd0
1 /*
2 * Samsung S3C2410A RISC Microprocessor support (ARM920T based SoC).
3 *
4 * Copyright (c) 2007 OpenMoko, Inc.
5 * Author: Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This code is licenced under the GNU GPL v2.
8 */
9
10 #include "s3c.h"
11 #include "qemu-timer.h"
12 #include "qemu-char.h"
13 #include "hw.h"
14 #include "console.h"
15 #include "devices.h"
16 #include "arm-misc.h"
17 #include "i2c.h"
18 #include "pxa.h"
19 #include "sysemu.h"
20
21 /* Interrupt controller */
22 struct s3c_pic_state_s {
23 target_phys_addr_t base;
24 qemu_irq *parent_pic;
25 qemu_irq *irqs;
26
27 uint32_t srcpnd;
28 uint32_t intpnd;
29 uint32_t intmsk;
30 uint32_t intmod;
31 uint32_t priority;
32 int intoffset;
33 uint32_t subsrcpnd;
34 uint32_t intsubmsk;
35 };
36
37 static void s3c_pic_update(struct s3c_pic_state_s *s)
38 {
39 qemu_set_irq(s->parent_pic[ARM_PIC_CPU_FIQ],
40 s->srcpnd & s->intmod);
41 qemu_set_irq(s->parent_pic[ARM_PIC_CPU_IRQ],
42 s->intpnd & ~s->intmsk & ~s->intmod);
43 }
44
45 /*
46 * Performs interrupt arbitration and notifies the CPU.
47 *
48 * Since it's a complex logic which cannot be relied on by the OS
49 * anyway - first because real hardware doesn't do it accurately,
50 * second because it only matters when interrupts occur at the
51 * same time which normally can't be predicted - we use a simpler
52 * version for non-debug runs.
53 */
54 #ifdef DEBUG
55 static const uint32_t s3c_arbmsk[6] = {
56 0x0000000f,
57 0x000003f0,
58 0x0000fc00,
59 0x003f0000,
60 0x0fc00000,
61 0xf0000000,
62 };
63
64 # define S3C_ARB_SEL(i) ((s->priority >> (7 + (i << 1))) & 3)
65 # define S3C_ARB_MODE(i) ((s->priority >> i) & 1)
66 # define S3C_ARB_SEL_SET(i, v) \
67 s->priority &= ~(3 << (7 + (i << 1))); \
68 s->priority |= v << (7 + (i << 1));
69
70 static void s3c_pic_arbitrate(struct s3c_pic_state_s *s)
71 {
72 uint32_t pnd = s->srcpnd & ~s->intmsk & ~s->intmod;
73 int offset, i, arb;
74 if (s->intpnd || !pnd) {
75 s3c_pic_update(s);
76 return;
77 }
78
79 if (pnd & s3c_arbmsk[0]) {
80 offset = 0;
81 arb = 0;
82 } else if (pnd & 0x0ffffff0) {
83 i = S3C_ARB_SEL(6);
84 i ^= i << 1;
85 if (!(pnd & s3c_arbmsk[1 + (i & 3)]))
86 if (!(pnd & s3c_arbmsk[1 + (++ i & 3)]))
87 if (!(pnd & s3c_arbmsk[1 + (++ i & 3)]))
88 i ++;
89
90 if (S3C_ARB_MODE(6))
91 S3C_ARB_SEL_SET(6, ((i + 1) & 3));
92 offset = (i & 3) * 6 + 4;
93 if (pnd & (1 << offset))
94 goto known_offset;
95 else if (!(pnd & (0x1f << offset))) {
96 offset += 5;
97 goto known_offset;
98 }
99 offset ++;
100 arb = (i & 3) + 1;
101 } else {
102 arb = 5;
103 offset = 28;
104 }
105
106 pnd >>= offset;
107 i = S3C_ARB_SEL(arb);
108 i ^= i << 1;
109 if (!(pnd & (1 << (i & 3))))
110 if (!(pnd & (1 << (++ i & 3))))
111 if (!(pnd & (1 << (++ i & 3))))
112 i ++;
113
114 if (S3C_ARB_MODE(arb))
115 S3C_ARB_SEL_SET(arb, ((i + 1) & 3));
116 offset += i & 3;
117 known_offset:
118 s->intoffset = offset;
119 s->intpnd = 1 << offset;
120 s3c_pic_update(s);
121 }
122 #else
123 inline static void s3c_pic_arbitrate(struct s3c_pic_state_s *s)
124 {
125 uint32_t pnd = s->srcpnd & ~s->intmsk & ~s->intmod;
126 if (pnd && !s->intpnd)
127 s->intpnd = 1 << (s->intoffset = ffs(pnd) - 1);
128 s3c_pic_update(s);
129 }
130 #endif
131
132 static const int s3c_sub_src_map[] = {
133 [S3C_PICS_RXD0 & 31] = S3C_PIC_UART0,
134 [S3C_PICS_TXD0 & 31] = S3C_PIC_UART0,
135 [S3C_PICS_ERR0 & 31] = S3C_PIC_UART0,
136 [S3C_PICS_RXD1 & 31] = S3C_PIC_UART1,
137 [S3C_PICS_TXD1 & 31] = S3C_PIC_UART1,
138 [S3C_PICS_ERR1 & 31] = S3C_PIC_UART1,
139 [S3C_PICS_RXD2 & 31] = S3C_PIC_UART2,
140 [S3C_PICS_TXD2 & 31] = S3C_PIC_UART2,
141 [S3C_PICS_ERR2 & 31] = S3C_PIC_UART2,
142 [S3C_PICS_TC & 31] = S3C_PIC_ADC,
143 [S3C_PICS_ADC & 31] = S3C_PIC_ADC,
144 };
145
146 static void s3c_pic_subupdate(struct s3c_pic_state_s *s)
147 {
148 int next;
149 const int *sub = &s3c_sub_src_map[-1];
150 uint32_t pnd = s->subsrcpnd & ~s->intsubmsk;
151 while ((next = ffs(pnd))) {
152 sub += next;
153 pnd >>= next;
154 s->srcpnd |= 1 << *sub;
155 }
156 s3c_pic_arbitrate(s);
157 }
158
159 static void s3c_pic_set_irq(void *opaque, int irq, int req)
160 {
161 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *) opaque;
162 uint32_t mask;
163 /* This interrupt controller doesn't clear any request signals
164 * or register bits automatically. */
165 if (!req)
166 return;
167
168 if (irq & 32) {
169 irq &= 31;
170 s->subsrcpnd |= 1 << irq;
171 if (s->intsubmsk & (1 << irq))
172 return;
173 else
174 irq = s3c_sub_src_map[irq];
175 }
176 s->srcpnd |= (mask = 1 << irq);
177
178 /* A FIQ */
179 if (s->intmod & mask)
180 qemu_irq_raise(s->parent_pic[ARM_PIC_CPU_FIQ]);
181 else if (!s->intpnd && !(s->intmsk & mask)) {
182 #ifdef DEBUG
183 s3c_pic_arbitrate(s);
184 #else
185 s->intpnd = mask;
186 s->intoffset = irq;
187 qemu_irq_raise(s->parent_pic[ARM_PIC_CPU_IRQ]);
188 #endif
189 }
190 }
191
192 static void s3c_pic_reset(struct s3c_pic_state_s *s)
193 {
194 s->srcpnd = 0;
195 s->intpnd = 0;
196 s->intmsk = 0xffffffff;
197 s->intmod = 0;
198 s->priority = 0x7f;
199 s->intoffset = 0;
200 s->subsrcpnd = 0;
201 s->intsubmsk = 0x7ff;
202 s3c_pic_update(s);
203 }
204
205 #define S3C_SRCPND 0x00 /* Source Pending register */
206 #define S3C_INTMOD 0x04 /* Source Mode register */
207 #define S3C_INTMSK 0x08 /* Interrupt Mask register */
208 #define S3C_PRIORITY 0x0c /* Priority register */
209 #define S3C_INTPND 0x10 /* Interrupt Pending register */
210 #define S3C_INTOFFSET 0x14 /* Interrupt Offset register */
211 #define S3C_SUBSRCPND 0x18 /* Sub Source Pending register */
212 #define S3C_INTSUBMSK 0x1c /* Interrupt Sub Mask register */
213
214 static uint32_t s3c_pic_read(void *opaque, target_phys_addr_t addr)
215 {
216 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *) opaque;
217
218 switch (addr) {
219 case S3C_SRCPND:
220 return s->srcpnd;
221 case S3C_INTPND:
222 return s->intpnd;
223 case S3C_INTMSK:
224 return s->intmsk;
225 case S3C_INTMOD:
226 return s->intmod;
227 case S3C_PRIORITY:
228 return s->priority;
229 case S3C_INTOFFSET:
230 return s->intoffset;
231 case S3C_SUBSRCPND:
232 return s->subsrcpnd;
233 case S3C_INTSUBMSK:
234 return s->intsubmsk;
235 default:
236 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
237 break;
238 }
239 return 0;
240 }
241
242 static void s3c_pic_write(void *opaque, target_phys_addr_t addr,
243 uint32_t value)
244 {
245 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *) opaque;
246
247 switch (addr) {
248 case S3C_SRCPND:
249 s->srcpnd &= ~value;
250 if (value & s->intmod)
251 s3c_pic_update(s);
252 break;
253 case S3C_INTPND:
254 if (s->intpnd & value) {
255 s->intpnd = 0;
256 s->intoffset = 0;
257 s3c_pic_arbitrate(s);
258 }
259 break;
260 case S3C_INTMSK:
261 s->intmsk = value;
262 if (s->intpnd & value) {
263 s->intpnd = 0;
264 s->intoffset = 0;
265 }
266 s3c_pic_arbitrate(s);
267 break;
268 case S3C_INTMOD:
269 s->intmod = value;
270 break;
271 case S3C_PRIORITY:
272 s->priority = value;
273 break;
274 case S3C_SUBSRCPND:
275 s->subsrcpnd &= ~value;
276 break;
277 case S3C_INTSUBMSK:
278 s->intsubmsk = value;
279 s3c_pic_subupdate(s);
280 break;
281 default:
282 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
283 }
284 }
285
286 static CPUReadMemoryFunc *s3c_pic_readfn[] = {
287 s3c_pic_read,
288 s3c_pic_read,
289 s3c_pic_read,
290 };
291
292 static CPUWriteMemoryFunc *s3c_pic_writefn[] = {
293 s3c_pic_write,
294 s3c_pic_write,
295 s3c_pic_write,
296 };
297
298 static void s3c_pic_save(QEMUFile *f, void *opaque)
299 {
300 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *) opaque;
301 qemu_put_be32s(f, &s->srcpnd);
302 qemu_put_be32s(f, &s->intpnd);
303 qemu_put_be32s(f, &s->intmsk);
304 qemu_put_be32s(f, &s->intmod);
305 qemu_put_be32s(f, &s->priority);
306 qemu_put_be32s(f, &s->subsrcpnd);
307 qemu_put_be32s(f, &s->intsubmsk);
308 qemu_put_be32(f, s->intoffset);
309 }
310
311 static int s3c_pic_load(QEMUFile *f, void *opaque, int version_id)
312 {
313 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *) opaque;
314 qemu_get_be32s(f, &s->srcpnd);
315 qemu_get_be32s(f, &s->intpnd);
316 qemu_get_be32s(f, &s->intmsk);
317 qemu_get_be32s(f, &s->intmod);
318 qemu_get_be32s(f, &s->priority);
319 qemu_get_be32s(f, &s->subsrcpnd);
320 qemu_get_be32s(f, &s->intsubmsk);
321 s->intoffset = qemu_get_be32(f);
322 s3c_pic_update(s);
323 return 0;
324 }
325
326 struct s3c_pic_state_s *s3c_pic_init(target_phys_addr_t base,
327 qemu_irq *arm_pic)
328 {
329 int iomemtype;
330 struct s3c_pic_state_s *s = (struct s3c_pic_state_s *)
331 qemu_mallocz(sizeof(struct s3c_pic_state_s));
332
333 s->base = base;
334 s->parent_pic = arm_pic;
335 s->irqs = qemu_allocate_irqs(s3c_pic_set_irq, s, S3C_PIC_MAX);
336
337 s3c_pic_reset(s);
338
339 iomemtype = cpu_register_io_memory(0, s3c_pic_readfn,
340 s3c_pic_writefn, s);
341 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
342
343 register_savevm("s3c24xx_pic", 0, 0, s3c_pic_save, s3c_pic_load, s);
344
345 return s;
346 }
347
348 qemu_irq *s3c_pic_get(struct s3c_pic_state_s *s)
349 {
350 return s->irqs;
351 }
352
353 /* Memory controller */
354 #define S3C_BWSCON 0x00 /* Bus Width & Wait Control register */
355 #define S3C_BANKCON0 0x04 /* Bank 0 Control register */
356 #define S3C_BANKCON1 0x08 /* Bank 1 Control register */
357 #define S3C_BANKCON2 0x0c /* Bank 2 Control register */
358 #define S3C_BANKCON3 0x10 /* Bank 3 Control register */
359 #define S3C_BANKCON4 0x14 /* Bank 4 Control register */
360 #define S3C_BANKCON5 0x18 /* Bank 5 Control register */
361 #define S3C_BANKCON6 0x1c /* Bank 6 Control register */
362 #define S3C_BANKCON7 0x20 /* Bank 7 Control register */
363 #define S3C_REFRESH 0x24 /* SDRAM Refresh Control register */
364 #define S3C_BANKSIZE 0x28 /* Flexible Bank Size register */
365 #define S3C_MRSRB6 0x2c /* Bank 6 Mode Set register */
366 #define S3C_MRSRB7 0x30 /* Bank 6 Mode Set register */
367
368 static void s3c_mc_reset(struct s3c_state_s *s)
369 {
370 s->mc_regs[S3C_BWSCON >> 2] = 0x0000000;
371 s->mc_regs[S3C_BANKCON0 >> 2] = 0x0700;
372 s->mc_regs[S3C_BANKCON1 >> 2] = 0x0700;
373 s->mc_regs[S3C_BANKCON2 >> 2] = 0x0700;
374 s->mc_regs[S3C_BANKCON3 >> 2] = 0x0700;
375 s->mc_regs[S3C_BANKCON4 >> 2] = 0x0700;
376 s->mc_regs[S3C_BANKCON5 >> 2] = 0x0700;
377 s->mc_regs[S3C_BANKCON6 >> 2] = 0x18008;
378 s->mc_regs[S3C_BANKCON7 >> 2] = 0x18008;
379 s->mc_regs[S3C_REFRESH >> 2] = 0xac0000;
380 s->mc_regs[S3C_BANKSIZE >> 2] = 0x2;
381 s->mc_regs[S3C_MRSRB6 >> 2] = 0x00;
382 s->mc_regs[S3C_MRSRB7 >> 2] = 0x00;
383 }
384
385 static uint32_t s3c_mc_read(void *opaque, target_phys_addr_t addr)
386 {
387 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
388
389 switch (addr >> 2) {
390 case S3C_BWSCON ... S3C_MRSRB7:
391 return s->mc_regs[addr >> 2];
392 default:
393 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
394 break;
395 }
396 return 0;
397 }
398
399 static void s3c_mc_write(void *opaque, target_phys_addr_t addr,
400 uint32_t value)
401 {
402 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
403
404 switch (addr >> 2) {
405 case S3C_BWSCON ... S3C_MRSRB7:
406 s->mc_regs[addr >> 2] = value;
407 break;
408 default:
409 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
410 }
411 }
412
413 static CPUReadMemoryFunc *s3c_mc_readfn[] = {
414 s3c_mc_read,
415 s3c_mc_read,
416 s3c_mc_read,
417 };
418
419 static CPUWriteMemoryFunc *s3c_mc_writefn[] = {
420 s3c_mc_write,
421 s3c_mc_write,
422 s3c_mc_write,
423 };
424
425 static void s3c_mc_save(QEMUFile *f, void *opaque)
426 {
427 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
428 int i;
429 for (i = 0; i < 13; i ++)
430 qemu_put_be32s(f, &s->mc_regs[i]);
431 }
432
433 static int s3c_mc_load(QEMUFile *f, void *opaque, int version_id)
434 {
435 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
436 int i;
437 for (i = 0; i < 13; i ++)
438 qemu_get_be32s(f, &s->mc_regs[i]);
439 return 0;
440 }
441
442 /* Clock & power management */
443 #define S3C_LOCKTIME 0x00 /* PLL Lock Time Count register */
444 #define S3C_MPLLCON 0x04 /* MPLL Configuration register */
445 #define S3C_UPLLCON 0x08 /* UPLL Configuration register */
446 #define S3C_CLKCON 0x0c /* Clock Generator Control register */
447 #define S3C_CLKSLOW 0x10 /* Slow Clock Control register */
448 #define S3C_CLKDIVN 0x14 /* Clock Divider Control register */
449
450 #define S3C2440_CAMDIVN 0x18 /* Camera Clock Divider register */
451
452 static void s3c_clkpwr_reset(struct s3c_state_s *s)
453 {
454 s->clkpwr_regs[S3C_LOCKTIME >> 2] = 0x00ffffff;
455 s->clkpwr_regs[S3C_MPLLCON >> 2] = 0x0005c080;
456 s->clkpwr_regs[S3C_UPLLCON >> 2] = 0x00028080;
457 s->clkpwr_regs[S3C_CLKCON >> 2] = 0x0007fff0;
458 s->clkpwr_regs[S3C_CLKSLOW >> 2] = 0x00000004;
459 s->clkpwr_regs[S3C_CLKDIVN >> 2] = 0x00000000;
460 s->clkpwr_regs[S3C2440_CAMDIVN >> 2] = 0x00000000;
461 }
462
463 static uint32_t s3c_clkpwr_read(void *opaque, target_phys_addr_t addr)
464 {
465 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
466
467 switch (addr) {
468 case S3C_LOCKTIME ... S3C_CLKDIVN:
469 return s->clkpwr_regs[addr >> 2];
470 case S3C2440_CAMDIVN:
471 if (s->cpu_id == S3C_CPU_2440)
472 return s->clkpwr_regs[addr >> 2];
473 default:
474 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
475 break;
476 }
477 return 0;
478 }
479
480 static void s3c_clkpwr_write(void *opaque, target_phys_addr_t addr,
481 uint32_t value)
482 {
483 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
484
485 switch (addr) {
486 case S3C_LOCKTIME:
487 case S3C_MPLLCON:
488 case S3C_UPLLCON:
489 case S3C_CLKDIVN:
490 s->clkpwr_regs[addr >> 2] = value;
491 break;
492 case S3C_CLKCON:
493 if (value & (1 << 3)) {
494 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
495 printf("%s: processor powered off\n", __FUNCTION__);
496 s3c_gpio_setpwrstat(s->io, 2);
497 #if 0
498 cpu_reset(s->env);
499 s->env->regs[15] = 0; /* XXX */
500 #endif
501 } else
502 if (value & (1 << 2)) /* Normal IDLE mode */
503 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
504 if ((s->clkpwr_regs[addr >> 2] ^ value) & 1)
505 printf("%s: SPECIAL mode %s\n", __FUNCTION__,
506 (value & 1) ? "on" : "off");
507 s->clkpwr_regs[addr >> 2] = value;
508 break;
509 case S3C_CLKSLOW:
510 if ((s->clkpwr_regs[addr >> 2] ^ value) & (1 << 4))
511 printf("%s: SLOW mode %s\n", __FUNCTION__,
512 (value & (1 << 4)) ? "on" : "off");
513 s->clkpwr_regs[addr >> 2] = value;
514 break;
515 case S3C2440_CAMDIVN:
516 if (s->cpu_id == S3C_CPU_2440) {
517 s->clkpwr_regs[addr >> 2] = value;
518 break;
519 }
520 default:
521 printf("%s: Bad register 0x%lx (cpu %08x)\n", __FUNCTION__, /*(unsigned long)*/addr, s->cpu_id);
522 }
523 }
524
525 static CPUReadMemoryFunc *s3c_clkpwr_readfn[] = {
526 s3c_clkpwr_read,
527 s3c_clkpwr_read,
528 s3c_clkpwr_read,
529 };
530
531 static CPUWriteMemoryFunc *s3c_clkpwr_writefn[] = {
532 s3c_clkpwr_write,
533 s3c_clkpwr_write,
534 s3c_clkpwr_write,
535 };
536
537 static void s3c_clkpwr_save(QEMUFile *f, void *opaque)
538 {
539 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
540 int i;
541 for (i = 0; i < 6; i ++)
542 qemu_put_be32s(f, &s->clkpwr_regs[i]);
543 }
544
545 static int s3c_clkpwr_load(QEMUFile *f, void *opaque, int version_id)
546 {
547 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
548 int i;
549 for (i = 0; i < 6; i ++)
550 qemu_get_be32s(f, &s->clkpwr_regs[i]);
551 return 0;
552 }
553
554 /* DMA controller */
555 #define S3C_DMA_CH_N 4
556
557 struct s3c_dma_ch_state_s;
558 struct s3c_dma_state_s { /* Modelled as an interrupt controller */
559 target_phys_addr_t base;
560 qemu_irq *drqs;
561 struct s3c_dma_ch_state_s {
562 qemu_irq intr;
563 int curr_tc;
564 int req;
565 int running;
566 uint32_t con;
567 uint32_t isrc;
568 uint32_t isrcc;
569 uint32_t idst;
570 uint32_t idstc;
571 uint32_t csrc;
572 uint32_t cdst;
573 uint32_t mask;
574 } ch[S3C_DMA_CH_N];
575 };
576
577 static inline void s3c_dma_ch_run(struct s3c_dma_state_s *s,
578 struct s3c_dma_ch_state_s *ch)
579 {
580 int width, burst, t;
581 uint8_t buffer[4];
582 width = 1 << ((ch->con >> 20) & 3); /* DSZ */
583 burst = (ch->con & (1 << 28)) ? 4 : 1; /* TSZ */
584
585 while (!ch->running && ch->curr_tc > 0 && ch->req &&
586 (ch->mask & (1 << 1))) { /* ON_OFF */
587 if (width > sizeof(buffer)) {
588 printf("%s: wrong access width\n", __FUNCTION__);
589 return;
590 }
591 ch->running = 1;
592 while (ch->curr_tc --) {
593 for (t = 0; t < burst; t ++) {
594 cpu_physical_memory_read(ch->csrc, buffer, width);
595 cpu_physical_memory_write(ch->cdst, buffer, width);
596
597 if (!(ch->isrcc & 1)) /* INT */
598 ch->csrc += width;
599 if (!(ch->idstc & 1)) /* INT */
600 ch->cdst += width;
601 }
602
603 if (!(ch->con & (1 << 27)) && !ch->req) /* SERVMODE */
604 break;
605 }
606 ch->running = 0;
607
608 if (!(ch->con & (1 << 23))) { /* SWHW_SEL */
609 ch->req = 0;
610 }
611
612 if (ch->curr_tc <= 0) {
613 if (ch->con & (1 << 22)) /* RELOAD */
614 ch->mask &= ~(1 << 1); /* ON_OFF */
615 else {
616 if (!(ch->con & (1 << 23))) { /* SWHW_SEL */
617 printf("%s: auto-reload software controlled transfer\n",
618 __FUNCTION__);
619 break;
620 }
621 ch->csrc = ch->isrc; /* S_ADDR */
622 ch->cdst = ch->idst; /* D_ADDR */
623 ch->curr_tc = ch->con & 0xfffff; /* TC */
624 ch->con |= 1 << 22; /* ON_OFF */
625 }
626
627 if (ch->con & (1 << 31)) /* DMD_HS */
628 ch->req = 0;
629
630 if (ch->con & (1 << 29)) { /* INT */
631 qemu_irq_raise(ch->intr);
632 /* Give the system a chance to respond. */
633 break;
634 }
635 }
636 }
637 }
638
639 static void s3c_dma_reset(struct s3c_dma_state_s *s)
640 {
641 int i;
642 for (i = 0; i < S3C_DMA_CH_N; i ++) {
643 s->ch[i].curr_tc = 0;
644 s->ch[i].csrc = 0;
645 s->ch[i].isrc = 0;
646 s->ch[i].isrcc = 0;
647 s->ch[i].cdst = 0;
648 s->ch[i].idst = 0;
649 s->ch[i].idstc = 0;
650 s->ch[i].con = 0;
651 s->ch[i].csrc = 0;
652 s->ch[i].cdst = 0;
653 s->ch[i].mask = 0;
654 }
655 }
656
657 static void s3c_dma_dreq(void *opaque, int line, int req)
658 {
659 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *) opaque;
660 struct s3c_dma_ch_state_s *ch = &s->ch[line >> 4];
661
662 if (ch->con & (1 << 23)) /* SWHW_SEL */
663 if (((ch->con >> 24) & 7) == (line & 7)) { /* HWSRCSEL */
664 ch->req = req;
665 s3c_dma_ch_run(s, ch);
666 }
667 }
668
669 #define S3C_DISRC 0x00 /* DMA Initial Source register */
670 #define S3C_DISRCC 0x04 /* DMA Initial Source Control register */
671 #define S3C_DIDST 0x08 /* DMA Initial Destination register */
672 #define S3C_DIDSTC 0x0c /* DMA Initial Destination Control register */
673 #define S3C_DCON 0x10 /* DMA Control register */
674 #define S3C_DSTAT 0x14 /* DMA Count register */
675 #define S3C_DCSRC 0x18 /* DMA Current Source register */
676 #define S3C_DCDST 0x1c /* DMA Current Destination register */
677 #define S3C_DMASKTRIG 0x20 /* DMA Mask Trigger register */
678
679 static uint32_t s3c_dma_read(void *opaque, target_phys_addr_t addr)
680 {
681 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *) opaque;
682 struct s3c_dma_ch_state_s *ch = 0;
683
684 if (addr >= 0 && addr <= (S3C_DMA_CH_N << 6)) {
685 ch = &s->ch[addr >> 6];
686 addr &= 0x3f;
687 }
688
689 switch (addr) {
690 case S3C_DISRC:
691 return ch->isrc;
692 case S3C_DISRCC:
693 return ch->isrcc;
694 case S3C_DIDST:
695 return ch->idst;
696 case S3C_DIDSTC:
697 return ch->idstc;
698 case S3C_DCON:
699 return ch->con;
700 case S3C_DSTAT:
701 return ch->curr_tc;
702 case S3C_DCSRC:
703 return ch->csrc;
704 case S3C_DCDST:
705 return ch->cdst;
706 case S3C_DMASKTRIG:
707 return ch->mask;
708 default:
709 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
710 break;
711 }
712 return 0;
713 }
714
715 static void s3c_dma_write(void *opaque, target_phys_addr_t addr,
716 uint32_t value)
717 {
718 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *) opaque;
719 struct s3c_dma_ch_state_s *ch = 0;
720
721 if (addr >= 0 && addr <= (S3C_DMA_CH_N << 6)) {
722 ch = &s->ch[addr >> 6];
723 addr &= 0x3f;
724 }
725
726 switch (addr) {
727 case S3C_DCON:
728 ch->con = value;
729 break;
730 case S3C_DISRC:
731 ch->isrc = value;
732 break;
733 case S3C_DISRCC:
734 ch->isrcc = value;
735 break;
736 case S3C_DIDST:
737 ch->idst = value;
738 break;
739 case S3C_DIDSTC:
740 ch->idstc = value;
741 break;
742 case S3C_DMASKTRIG:
743 if (~ch->mask & value & (1 << 1)) { /* ON_OFF */
744 ch->curr_tc = ch->con & 0xfffff; /* TC */
745 ch->csrc = ch->isrc; /* S_ADDR */
746 ch->cdst = ch->idst; /* D_ADDR */
747 }
748
749 ch->mask = value;
750 if (value & (1 << 2)) { /* STOP */
751 ch->mask &= ~(3 << 1); /* ON_OFF */
752 } else if (!(ch->con & (1 << 23))) { /* SWHW_SEL */
753 ch->req = value & 1; /* SW_TRIG */
754 s3c_dma_ch_run(s, ch);
755 }
756 break;
757 default:
758 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
759 }
760 }
761
762 static CPUReadMemoryFunc *s3c_dma_readfn[] = {
763 s3c_dma_read,
764 s3c_dma_read,
765 s3c_dma_read,
766 };
767
768 static CPUWriteMemoryFunc *s3c_dma_writefn[] = {
769 s3c_dma_write,
770 s3c_dma_write,
771 s3c_dma_write,
772 };
773
774 static void s3c_dma_save(QEMUFile *f, void *opaque)
775 {
776 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *) opaque;
777 int i;
778 for (i = 0; i < S3C_DMA_CH_N; i ++) {
779 qemu_put_be32(f, s->ch[i].curr_tc);
780 qemu_put_be32(f, s->ch[i].req);
781 qemu_put_be32s(f, &s->ch[i].con);
782 qemu_put_be32s(f, &s->ch[i].isrc);
783 qemu_put_be32s(f, &s->ch[i].isrcc);
784 qemu_put_be32s(f, &s->ch[i].idst);
785 qemu_put_be32s(f, &s->ch[i].idstc);
786 qemu_put_be32s(f, &s->ch[i].csrc);
787 qemu_put_be32s(f, &s->ch[i].cdst);
788 qemu_put_be32s(f, &s->ch[i].mask);
789 }
790 }
791
792 static int s3c_dma_load(QEMUFile *f, void *opaque, int version_id)
793 {
794 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *) opaque;
795 int i;
796 for (i = 0; i < S3C_DMA_CH_N; i ++) {
797 s->ch[i].curr_tc = qemu_get_be32(f);
798 s->ch[i].req = qemu_get_be32(f);
799 qemu_get_be32s(f, &s->ch[i].con);
800 qemu_get_be32s(f, &s->ch[i].isrc);
801 qemu_get_be32s(f, &s->ch[i].isrcc);
802 qemu_get_be32s(f, &s->ch[i].idst);
803 qemu_get_be32s(f, &s->ch[i].idstc);
804 qemu_get_be32s(f, &s->ch[i].csrc);
805 qemu_get_be32s(f, &s->ch[i].cdst);
806 qemu_get_be32s(f, &s->ch[i].mask);
807 }
808 return 0;
809 }
810
811 struct s3c_dma_state_s *s3c_dma_init(target_phys_addr_t base, qemu_irq *pic)
812 {
813 int iomemtype;
814 struct s3c_dma_state_s *s = (struct s3c_dma_state_s *)
815 qemu_mallocz(sizeof(struct s3c_dma_state_s));
816
817 s->base = base;
818 s->ch[0].intr = pic[0];
819 s->ch[1].intr = pic[1];
820 s->ch[2].intr = pic[2];
821 s->ch[3].intr = pic[3];
822 s->drqs = qemu_allocate_irqs(s3c_dma_dreq, s, S3C_RQ_MAX);
823
824 s3c_dma_reset(s);
825
826 iomemtype = cpu_register_io_memory(0, s3c_dma_readfn,
827 s3c_dma_writefn, s);
828 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
829
830 register_savevm("s3c24xx_dma", 0, 0, s3c_dma_save, s3c_dma_load, s);
831
832 return s;
833 }
834
835 qemu_irq *s3c_dma_get(struct s3c_dma_state_s *s)
836 {
837 return s->drqs;
838 }
839
840 /* PWM timers controller */
841 struct s3c_timer_state_s;
842 struct s3c_timers_state_s {
843 target_phys_addr_t base;
844 qemu_irq *dma;
845 DisplayState *ds;
846 struct s3c_timer_state_s {
847 QEMUTimer *t;
848 struct s3c_timers_state_s *s;
849 int n;
850 int running;
851 uint32_t divider;
852 uint16_t count;
853 int64_t reload;
854 qemu_irq irq;
855 gpio_handler_t cmp_cb;
856 void *cmp_opaque;
857 } timer[5];
858
859 uint16_t compareb[4];
860 uint16_t countb[5];
861 uint32_t config[2];
862 uint32_t control;
863 };
864
865 static const int s3c_tm_bits[] = { 0, 8, 12, 16, 20 };
866
867 static uint16_t s3c_timers_get(struct s3c_timers_state_s *s, int tm)
868 {
869 uint16_t elapsed;
870 if (!s->timer[tm].running)
871 return s->timer[tm].count;
872
873 elapsed = muldiv64(qemu_get_clock(vm_clock) - s->timer[tm].reload,
874 s->timer[tm].divider, ticks_per_sec);
875 if (unlikely(elapsed > s->timer[tm].count))
876 return s->timer[tm].count;
877
878 return s->timer[tm].count - elapsed;
879 }
880
881 static void s3c_timers_stop(struct s3c_timers_state_s *s, int tm)
882 {
883 s->timer[tm].count = s3c_timers_get(s, tm);
884 s->timer[tm].running = 0;
885 }
886
887 static void s3c_timers_start(struct s3c_timers_state_s *s, int tm)
888 {
889 if (s->timer[tm].running)
890 return;
891
892 s->timer[tm].divider = S3C_PCLK_FREQ >>
893 (((s->config[1] >> (tm * 4)) & 3) + 1);
894 if (tm < 2)
895 s->timer[tm].divider /= ((s->config[0] >> 0) & 0xff) + 1;
896 else
897 s->timer[tm].divider /= ((s->config[0] >> 8) & 0xff) + 1;
898 s->timer[tm].running = 1;
899 s->timer[tm].reload = qemu_get_clock(vm_clock);
900 qemu_mod_timer(s->timer[tm].t,
901 s->timer[tm].reload + muldiv64(s->timer[tm].count,
902 ticks_per_sec, s->timer[tm].divider));
903 }
904
905 static void s3c_timers_reset(struct s3c_timers_state_s *s)
906 {
907 int i;
908 s->config[0] = 0x00000000;
909 s->config[1] = 0x00000000;
910 s->control = 0x00000000;
911
912 for (i = 0; i < 5; i ++) {
913 if (s->timer[i].running)
914 s3c_timers_stop(s, i);
915 s->countb[i] = 0x0000;
916 s->timer[i].count = 0;
917 }
918 for (i = 0; i < 4; i ++)
919 s->compareb[i] = 0x0000;
920 }
921
922 static void s3c_timers_tick(void *opaque)
923 {
924 struct s3c_timer_state_s *t = (struct s3c_timer_state_s *) opaque;
925 struct s3c_timers_state_s *s = t->s;
926 if (!t->running)
927 return;
928
929 if (((s->config[1] >> 20) & 0xf) == t->n + 1) {
930 qemu_irq_raise(s->dma[S3C_RQ_TIMER0]); /* TODO */
931 qemu_irq_raise(s->dma[S3C_RQ_TIMER1]);
932 qemu_irq_raise(s->dma[S3C_RQ_TIMER2]);
933 } else
934 qemu_irq_raise(t->irq);
935
936 t->running = 0;
937 t->count = 0;
938
939 if (s->control & (1 << ((t->n == 4) ? 22 : (s3c_tm_bits[t->n] + 3)))) {
940 /* Auto-reload */
941 t->count = s->countb[t->n];
942 s3c_timers_start(s, t->n);
943 } else
944 s->control &= ~(1 << s3c_tm_bits[t->n]);
945 }
946
947 #define S3C_TCFG0 0x00 /* Timer Configuration register 0 */
948 #define S3C_TCFG1 0x04 /* Timer Configuration register 1 */
949 #define S3C_TCON 0x08 /* Timer Control register */
950 #define S3C_TCNTB0 0x0c /* Timer 0 Count Buffer register */
951 #define S3C_TCMPB0 0x10 /* Timer 0 Compare Buffer register */
952 #define S3C_TCNTO0 0x14 /* Timer 0 Count Observation register */
953 #define S3C_TCNTB1 0x18 /* Timer 1 Count Buffer register */
954 #define S3C_TCMPB1 0x1c /* Timer 1 Compare Buffer register */
955 #define S3C_TCNTO1 0x20 /* Timer 1 Count Observation register */
956 #define S3C_TCNTB2 0x24 /* Timer 2 Count Buffer register */
957 #define S3C_TCMPB2 0x28 /* Timer 2 Compare Buffer register */
958 #define S3C_TCNTO2 0x2c /* Timer 2 Count Observation register */
959 #define S3C_TCNTB3 0x30 /* Timer 3 Count Buffer register */
960 #define S3C_TCMPB3 0x34 /* Timer 3 Compare Buffer register */
961 #define S3C_TCNTO3 0x38 /* Timer 3 Count Observation register */
962 #define S3C_TCNTB4 0x3c /* Timer 4 Count Buffer register */
963 #define S3C_TCNTO4 0x40 /* Timer 4 Count Observation register */
964
965 static uint32_t s3c_timers_read(void *opaque, target_phys_addr_t addr)
966 {
967 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *) opaque;
968 int tm = 0;
969
970 switch (addr) {
971 case S3C_TCFG0:
972 return s->config[0];
973 case S3C_TCFG1:
974 return s->config[1];
975 case S3C_TCON:
976 return s->control;
977 case S3C_TCMPB3: tm ++;
978 case S3C_TCMPB2: tm ++;
979 case S3C_TCMPB1: tm ++;
980 case S3C_TCMPB0:
981 return s->compareb[tm];
982 case S3C_TCNTB4: tm ++;
983 case S3C_TCNTB3: tm ++;
984 case S3C_TCNTB2: tm ++;
985 case S3C_TCNTB1: tm ++;
986 case S3C_TCNTB0:
987 return s->countb[tm];
988 case S3C_TCNTO4: tm ++;
989 case S3C_TCNTO3: tm ++;
990 case S3C_TCNTO2: tm ++;
991 case S3C_TCNTO1: tm ++;
992 case S3C_TCNTO0:
993 return s3c_timers_get(s, tm);
994 default:
995 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
996 break;
997 }
998 return 0;
999 }
1000
1001 static void s3c_timers_write(void *opaque, target_phys_addr_t addr,
1002 uint32_t value)
1003 {
1004 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *) opaque;
1005 int tm = 0;
1006 // s->base;
1007
1008 switch (addr) {
1009 case S3C_TCFG0:
1010 s->config[0] = value & 0x00ffffff;
1011 break;
1012 case S3C_TCFG1:
1013 s->config[1] = value & 0x00ffffff;
1014 break;
1015 case S3C_TCON:
1016 for (tm = 0; tm < 5; tm ++) {
1017 if (value & (2 << (s3c_tm_bits[tm]))) {
1018 if (s->timer[tm].running) {
1019 s3c_timers_stop(s, tm);
1020 s->timer[tm].count = s->countb[tm];
1021 s3c_timers_start(s, tm);
1022 } else
1023 s->timer[tm].count = s->countb[tm];
1024 }
1025 if (((value >> s3c_tm_bits[tm]) & 1) ^ s->timer[tm].running) {
1026 if (s->timer[tm].running)
1027 s3c_timers_stop(s, tm);
1028 else
1029 s3c_timers_start(s, tm);
1030 }
1031 }
1032
1033 s->control = value & 0x007fff1f;
1034 break;
1035 case S3C_TCMPB3: tm ++;
1036 case S3C_TCMPB2: tm ++;
1037 case S3C_TCMPB1: tm ++;
1038 case S3C_TCMPB0:
1039 s->compareb[tm] = value & 0xffff;
1040 if (s->timer[tm].cmp_cb)
1041 s->timer[tm].cmp_cb(tm, s->compareb[tm], s->timer[tm].cmp_opaque);
1042 break;
1043 case S3C_TCNTB4: tm ++;
1044 case S3C_TCNTB3: tm ++;
1045 case S3C_TCNTB2: tm ++;
1046 case S3C_TCNTB1: tm ++;
1047 case S3C_TCNTB0:
1048 s->countb[tm] = value & 0xffff;
1049 break;
1050 default:
1051 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1052 }
1053 }
1054
1055 static CPUReadMemoryFunc *s3c_timers_readfn[] = {
1056 s3c_timers_read,
1057 s3c_timers_read,
1058 s3c_timers_read,
1059 };
1060
1061 static CPUWriteMemoryFunc *s3c_timers_writefn[] = {
1062 s3c_timers_write,
1063 s3c_timers_write,
1064 s3c_timers_write,
1065 };
1066
1067 static void s3c_timers_save(QEMUFile *f, void *opaque)
1068 {
1069 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *) opaque;
1070 int i;
1071 for (i = 0; i < 5; i ++) {
1072 qemu_put_be32(f, s->timer[i].running);
1073 qemu_put_be32s(f, &s->timer[i].divider);
1074 qemu_put_be16(f, s3c_timers_get(s, i));
1075 qemu_put_be64s(f, &s->timer[i].reload);
1076 }
1077
1078 for (i = 0; i < 4; i ++)
1079 qemu_put_be16s(f, &s->compareb[i]);
1080 for (i = 0; i < 5; i ++)
1081 qemu_put_be16s(f, &s->countb[i]);
1082 for (i = 0; i < 2; i ++)
1083 qemu_put_be32s(f, &s->config[i]);
1084 qemu_put_be32s(f, &s->control);
1085 }
1086
1087 static int s3c_timers_load(QEMUFile *f, void *opaque, int version_id)
1088 {
1089 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *) opaque;
1090 int i, running[5];
1091 for (i = 0; i < 5; i ++) {
1092 s->timer[i].running = 0;
1093 running[i] = qemu_get_be32(f);
1094 qemu_get_be32s(f, &s->timer[i].divider);
1095 qemu_get_be16s(f, &s->timer[i].count);
1096 qemu_get_be64s(f, &s->timer[i].reload);
1097 }
1098
1099 for (i = 0; i < 4; i ++)
1100 qemu_get_be16s(f, &s->compareb[i]);
1101 for (i = 0; i < 5; i ++)
1102 qemu_get_be16s(f, &s->countb[i]);
1103 for (i = 0; i < 2; i ++)
1104 qemu_get_be32s(f, &s->config[i]);
1105 qemu_get_be32s(f, &s->control);
1106
1107 for (i = 0; i < 5; i ++)
1108 if (running[i])
1109 s3c_timers_start(s, i);
1110
1111 return 0;
1112 }
1113
1114 struct s3c_timers_state_s *s3c_timers_init(target_phys_addr_t base,
1115 qemu_irq *pic, qemu_irq *dma)
1116 {
1117 int i, iomemtype;
1118 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *)
1119 qemu_mallocz(sizeof(struct s3c_timers_state_s));
1120
1121 s->base = base;
1122 s->dma = dma;
1123
1124 s3c_timers_reset(s);
1125
1126 for (i = 0; i < 5; i ++) {
1127 s->timer[i].t = qemu_new_timer(vm_clock,
1128 s3c_timers_tick, &s->timer[i]);
1129 s->timer[i].s = s;
1130 s->timer[i].n = i;
1131 s->timer[i].cmp_cb = 0;
1132 s->timer[i].irq = pic[i];
1133 }
1134
1135 iomemtype = cpu_register_io_memory(0, s3c_timers_readfn,
1136 s3c_timers_writefn, s);
1137 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
1138
1139 register_savevm("s3c24xx_timers", 0, 0,
1140 s3c_timers_save, s3c_timers_load, s);
1141
1142 return s;
1143 }
1144
1145 void s3c_timers_cmp_handler_set(void *opaque, int line,
1146 gpio_handler_t handler, void *cmp_opaque)
1147 {
1148 struct s3c_timers_state_s *s = (struct s3c_timers_state_s *) opaque;
1149 if (line > 4 || line < 0) {
1150 printf("%s: Bad timer number %i.\n", __FUNCTION__, line);
1151 exit(-1);
1152 }
1153 s->timer[line].cmp_cb = handler;
1154 s->timer[line].cmp_opaque = cmp_opaque;
1155 }
1156
1157 /* UART */
1158 struct s3c_uart_state_s {
1159 target_phys_addr_t base;
1160 qemu_irq *irq;
1161 qemu_irq *dma;
1162 uint8_t data;
1163 uint8_t rxfifo[16];
1164 int rxstart;
1165 int rxlen;
1166 #define UART_MAX_CHR 4
1167 int chr_num;
1168 CharDriverState *chr[UART_MAX_CHR];
1169
1170 uint8_t lcontrol;
1171 uint8_t fcontrol;
1172 uint8_t mcontrol;
1173 uint16_t control;
1174 uint16_t brdiv;
1175 uint8_t errstat;
1176 };
1177
1178 static void s3c_uart_reset(struct s3c_uart_state_s *s)
1179 {
1180 s->lcontrol = 0x00;
1181 s->fcontrol = 0x00;
1182 s->mcontrol = 0x00;
1183 s->control = 0x0000;
1184 s->errstat = 0;
1185
1186 s->rxstart = 0;
1187 s->rxlen = 0;
1188 }
1189
1190 static void s3c_uart_err(struct s3c_uart_state_s *s, int err)
1191 {
1192 s->errstat |= err;
1193 if (s->control & (1 << 6))
1194 qemu_irq_raise(s->irq[2]);
1195 }
1196
1197 inline static void s3c_uart_full(struct s3c_uart_state_s *s, int pulse)
1198 {
1199 if (s->fcontrol & 1) /* FIFOEnable */
1200 if (s->rxlen < (((s->fcontrol >> 4) & 3) + 1) * 4) {
1201 if (((s->control >> 0) & 3) != 1 || /* ReceiveMode */
1202 !s->rxlen)
1203 return;
1204 if (!(s->control & (1 << 7))) /* RxTimeOutEnable */
1205 return;
1206 /* When the Rx FIFO trigger level is not reached, the interrupt
1207 * is generated anyway, just after a small timeout instead of
1208 * immediately. */
1209 }
1210
1211 switch ((s->control >> 0) & 3) { /* ReceiveMode */
1212 case 1:
1213 if ((s->control & (1 << 8)) || pulse) /* RxInterruptType */
1214 qemu_irq_raise(s->irq[0]);
1215 break;
1216 case 2:
1217 case 3:
1218 qemu_irq_raise(s->dma[0]);
1219 break;
1220 }
1221 }
1222
1223 inline static void s3c_uart_empty(struct s3c_uart_state_s *s, int pulse)
1224 {
1225 switch ((s->control >> 2) & 3) { /* TransmitMode */
1226 case 1:
1227 if ((s->control & (1 << 9)) || pulse) /* TxInterruptType */
1228 qemu_irq_raise(s->irq[1]);
1229 break;
1230 case 2:
1231 case 3:
1232 qemu_irq_raise(s->dma[0]);
1233 break;
1234 }
1235 }
1236
1237 inline static void s3c_uart_update(struct s3c_uart_state_s *s)
1238 {
1239 s3c_uart_empty(s, 0);
1240 s3c_uart_full(s, 0);
1241 }
1242
1243 static void s3c_uart_params_update(struct s3c_uart_state_s *s)
1244 {
1245 QEMUSerialSetParams ssp;
1246 int i;
1247 if (!s->chr)
1248 return;
1249
1250 /* XXX Calculate PCLK frequency from clock manager registers */
1251 ssp.speed = (S3C_PCLK_FREQ >> 4) / (s->brdiv + 1);
1252
1253 switch ((s->lcontrol >> 3) & 7) {
1254 case 4:
1255 case 6:
1256 ssp.parity = 'O';
1257 break;
1258 case 5:
1259 case 7:
1260 ssp.parity = 'E';
1261 break;
1262 default:
1263 ssp.parity = 'N';
1264 }
1265
1266 ssp.data_bits = 5 + (s->lcontrol & 3);
1267
1268 ssp.stop_bits = (s->lcontrol & (1 << 2)) ? 2 : 1;
1269
1270 for (i = 0; i < s->chr_num; i ++)
1271 qemu_chr_ioctl(s->chr[i], CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
1272 }
1273
1274 static int s3c_uart_is_empty(void *opaque)
1275 {
1276 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1277 if (s->fcontrol & 1) /* FIFOEnable */
1278 return 16 - s->rxlen;
1279 else
1280 return 1 - s->rxlen;
1281 }
1282
1283 static void s3c_uart_rx(void *opaque, const uint8_t *buf, int size)
1284 {
1285 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1286 int left;
1287 if (s->fcontrol & 1) { /* FIFOEnable */
1288 if (s->rxlen + size > 16) {
1289 size = 16 - s->rxlen;
1290 s3c_uart_err(s, 1);
1291 }
1292
1293 left = 16 - ((s->rxstart + s->rxlen) & 15);
1294 if (size > left) {
1295 memcpy(s->rxfifo + ((s->rxstart + s->rxlen) & 15), buf, left);
1296 memcpy(s->rxfifo, buf + left, size - left);
1297 } else
1298 memcpy(s->rxfifo + ((s->rxstart + s->rxlen) & 15), buf, size);
1299 s->rxlen += size;
1300 } else {
1301 if (s->rxlen + size > 1)
1302 s3c_uart_err(s, 1);
1303 s->rxlen = 1;
1304 s->data = buf[0];
1305 }
1306 s3c_uart_full(s, 1);
1307 }
1308
1309 /* S3C2410 UART doesn't seem to understand break conditions. */
1310 static void s3c_uart_event(void *opaque, int event)
1311 {
1312 }
1313
1314 #define S3C_ULCON 0x00 /* UART Line Control register */
1315 #define S3C_UCON 0x04 /* UART Control register */
1316 #define S3C_UFCON 0x08 /* UART FIFO Control register */
1317 #define S3C_UMCON 0x0c /* UART Modem Control register */
1318 #define S3C_UTRSTAT 0x10 /* UART Tx/Rx Status register */
1319 #define S3C_UERSTAT 0x14 /* UART Error Status register */
1320 #define S3C_UFSTAT 0x18 /* UART FIFO Status register */
1321 #define S3C_UMSTAT 0x1c /* UART Modem Status register */
1322 #define S3C_UTXH 0x20 /* UART Transmit Buffer register */
1323 #define S3C_URXH 0x24 /* UART Receive Buffer register */
1324 #define S3C_UBRDIV 0x28 /* UART Baud Rate Divisor register */
1325
1326 static uint32_t s3c_uart_read(void *opaque, target_phys_addr_t addr)
1327 {
1328 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1329 uint8_t ret;
1330
1331 switch (addr) {
1332 case S3C_ULCON:
1333 return s->lcontrol;
1334 case S3C_UCON:
1335 return s->control;
1336 case S3C_UFCON:
1337 return s->fcontrol;
1338 case S3C_UMCON:
1339 return s->mcontrol;
1340 case S3C_UTRSTAT:
1341 return 6 | !!s->rxlen;
1342 case S3C_UERSTAT:
1343 /* XXX: UERSTAT[3] is Reserved but Linux thinks it is BREAK */
1344 ret = s->errstat;
1345 s->errstat = 0;
1346 s3c_uart_update(s);
1347 return ret;
1348 case S3C_UFSTAT:
1349 s3c_uart_update(s);
1350 return s->rxlen ? s->rxlen | (1 << 8) : 0;
1351 case S3C_UMSTAT:
1352 s3c_uart_update(s);
1353 return 0x11;
1354 case S3C_UTXH: /* why this is called by u-boot is not clear */
1355 return 0;
1356 case S3C_URXH:
1357 s3c_uart_update(s);
1358 if (s->rxlen) {
1359 s->rxlen --;
1360 if (s->fcontrol & 1) { /* FIFOEnable */
1361 ret = s->rxfifo[s->rxstart ++];
1362 s->rxstart &= 15;
1363 } else
1364 ret = s->data;
1365 return ret;
1366 }
1367 return 0;
1368 case S3C_UBRDIV:
1369 return s->brdiv;
1370 default:
1371 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1372 break;
1373 }
1374 return 0;
1375 }
1376
1377 static void s3c_uart_write(void *opaque, target_phys_addr_t addr,
1378 uint32_t value)
1379 {
1380 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1381 uint8_t ch;
1382 int i, afc;
1383
1384 switch (addr) {
1385 case S3C_ULCON:
1386 if ((s->lcontrol ^ value) & (1 << 6))
1387 printf("%s: UART Infra-red mode %s\n", __FUNCTION__,
1388 (value & (1 << 6)) ? "on" : "off");
1389 s->lcontrol = value;
1390 s3c_uart_params_update(s);
1391 s3c_uart_update(s);
1392 break;
1393 case S3C_UCON:
1394 /* XXX: UCON[4] is Reserved but Linux thinks it is BREAK */
1395 if ((s->control ^ value) & (1 << 5))
1396 printf("%s: UART loopback test mode %s\n", __FUNCTION__,
1397 (value & (1 << 5)) ? "on" : "off");
1398 s->control = value & 0x7ef;
1399 s3c_uart_update(s);
1400 break;
1401 case S3C_UFCON:
1402 if (value & (1 << 1)) /* RxReset */
1403 s->rxlen = 0;
1404 s->fcontrol = value & 0xf1;
1405 s3c_uart_update(s);
1406 break;
1407 case S3C_UMCON:
1408 #ifdef CONFIG_S3C_MODEM /* not handled, openmoko modem.c not imported */
1409 if ((s->mcontrol ^ value) & (1 << 4)) {
1410 afc = (value >> 4) & 1;
1411 for (i = 0; i < s->chr_num; i ++)
1412 qemu_chr_ioctl(s->chr[i], CHR_IOCTL_MODEM_HANDSHAKE, &afc);
1413 }
1414 #endif
1415 s->mcontrol = value & 0x11;
1416 s3c_uart_update(s);
1417 break;
1418 case S3C_UTXH:
1419 ch = value & 0xff;
1420 for (i = 0; i < s->chr_num; i ++)
1421 qemu_chr_write(s->chr[i], &ch, 1);
1422 s3c_uart_empty(s, 1);
1423 s3c_uart_update(s);
1424 break;
1425 case S3C_UBRDIV:
1426 s->brdiv = value & 0xffff;
1427 s3c_uart_params_update(s);
1428 s3c_uart_update(s);
1429 break;
1430 default:
1431 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1432 }
1433 }
1434
1435 static CPUReadMemoryFunc *s3c_uart_readfn[] = {
1436 s3c_uart_read,
1437 s3c_uart_read,
1438 s3c_uart_read,
1439 };
1440
1441 static CPUWriteMemoryFunc *s3c_uart_writefn[] = {
1442 s3c_uart_write,
1443 s3c_uart_write,
1444 s3c_uart_write,
1445 };
1446
1447 static void s3c_uart_save(QEMUFile *f, void *opaque)
1448 {
1449 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1450 qemu_put_8s(f, &s->data);
1451 qemu_put_buffer(f, s->rxfifo, sizeof(s->rxfifo));
1452 qemu_put_be32(f, s->rxstart);
1453 qemu_put_be32(f, s->rxlen);
1454 qemu_put_8s(f, &s->lcontrol);
1455 qemu_put_8s(f, &s->fcontrol);
1456 qemu_put_8s(f, &s->mcontrol);
1457 qemu_put_be16s(f, &s->control);
1458 qemu_put_be16s(f, &s->brdiv);
1459 qemu_put_8s(f, &s->errstat);
1460 }
1461
1462 static int s3c_uart_load(QEMUFile *f, void *opaque, int version_id)
1463 {
1464 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *) opaque;
1465 qemu_get_8s(f, &s->data);
1466 qemu_get_buffer(f, s->rxfifo, sizeof(s->rxfifo));
1467 s->rxstart = qemu_get_be32(f);
1468 s->rxlen = qemu_get_be32(f);
1469 qemu_get_8s(f, &s->lcontrol);
1470 qemu_get_8s(f, &s->fcontrol);
1471 qemu_get_8s(f, &s->mcontrol);
1472 qemu_get_be16s(f, &s->control);
1473 qemu_get_be16s(f, &s->brdiv);
1474 qemu_get_8s(f, &s->errstat);
1475
1476 return 0;
1477 }
1478
1479 struct s3c_uart_state_s *s3c_uart_init(target_phys_addr_t base,
1480 qemu_irq *irqs, qemu_irq *dma)
1481 {
1482 int iomemtype;
1483 struct s3c_uart_state_s *s = (struct s3c_uart_state_s *)
1484 qemu_mallocz(sizeof(struct s3c_uart_state_s));
1485
1486 s->base = base;
1487 s->irq = irqs;
1488 s->dma = dma;
1489
1490 s3c_uart_reset(s);
1491
1492 iomemtype = cpu_register_io_memory(0, s3c_uart_readfn,
1493 s3c_uart_writefn, s);
1494 cpu_register_physical_memory(s->base, 0xfff, iomemtype);
1495
1496 register_savevm("s3c24xx_uart", base, 0, s3c_uart_save, s3c_uart_load, s);
1497
1498 return s;
1499 }
1500
1501 void s3c_uart_attach(struct s3c_uart_state_s *s, CharDriverState *chr)
1502 {
1503 if (s->chr_num >= UART_MAX_CHR)
1504 cpu_abort(cpu_single_env, "%s: Too many devices\n", __FUNCTION__);
1505 s->chr[s->chr_num ++] = chr;
1506
1507 qemu_chr_add_handlers(chr, s3c_uart_is_empty,
1508 s3c_uart_rx, s3c_uart_event, s);
1509 }
1510
1511 /* ADC & Touchscreen interface */
1512 struct s3c_adc_state_s {
1513 target_phys_addr_t base;
1514 qemu_irq irq;
1515 qemu_irq tcirq;
1516 QEMUTimer *convt;
1517 QEMUTimer *tst;
1518 int x;
1519 int y;
1520 int down;
1521 int enable;
1522 int input[8];
1523 int in_idx;
1524 int noise;
1525 int scale[6];
1526
1527 uint16_t control;
1528 uint16_t ts;
1529 uint16_t delay;
1530 int16_t xdata;
1531 int16_t ydata;
1532 };
1533
1534 static void s3c_adc_reset(struct s3c_adc_state_s *s)
1535 {
1536 s->down = 0;
1537 s->control = 0x3fc4;
1538 s->ts = 0x58;
1539 s->delay = 0xff;
1540 s->enable = 1;
1541 }
1542
1543 static void s3c_adc_start(struct s3c_adc_state_s *s)
1544 {
1545 if (!s->enable || (s->ts & 7) == 0)
1546 return;
1547 s->control &= ~(1 << 15);
1548 s->in_idx = (s->control >> 3) & 7;
1549 qemu_mod_timer(s->convt, qemu_get_clock(vm_clock) + (ticks_per_sec >> 5));
1550 }
1551
1552 static void s3c_adc_done(void *opaque)
1553 {
1554 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1555 s->xdata = s->input[s->in_idx] & 0x3ff;
1556 s->control |= 1 << 15;
1557 qemu_irq_raise(s->irq);
1558 }
1559
1560 static void s3c_adc_tick(void *opaque)
1561 {
1562 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1563 int sx, sy;
1564
1565 if (s->down) {
1566 if ((s->ts & 3) == 3 && s->enable)
1567 qemu_irq_raise(s->tcirq);
1568 else if (s->enable && ((s->ts & (1 << 2)) || (s->ts & 3))) {
1569 sx = s->x * s->scale[0] + s->y * s->scale[1] + s->scale[2];
1570 sy = s->x * s->scale[3] + s->y * s->scale[4] + s->scale[5];
1571 s->xdata = ((sx >> 13) & 0xfff) | (1 << 14) | ((s->ts & 3) << 12);
1572 s->ydata = ((sy >> 13) & 0xfff) | (1 << 14) | ((s->ts & 3) << 12);
1573 s->xdata ^= s->noise >> 1;
1574 s->ydata ^= s->noise >> 2;
1575 qemu_irq_raise(s->irq);
1576 s->noise ++;
1577 s->noise &= 7;
1578 }
1579 qemu_mod_timer(s->tst, qemu_get_clock(vm_clock) +
1580 (ticks_per_sec >> 5));
1581 }
1582 }
1583
1584 static void s3c_adc_event(void *opaque,
1585 int x, int y, int z, int buttons_state)
1586 {
1587 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1588 s->down = !!buttons_state;
1589 s->x = x;
1590 s->y = y;
1591 s3c_adc_tick(s);
1592 }
1593
1594 #define S3C_ADCCON 0x00 /* ADC Control register */
1595 #define S3C_ADCTSC 0x04 /* ADC Touchscreen Control register */
1596 #define S3C_ADCDLY 0x08 /* ADC Start or Interval Delay register */
1597 #define S3C_ADCDAT0 0x0c /* ADC Conversion Data register 0 */
1598 #define S3C_ADCDAT1 0x10 /* ADC Conversion Data register 1 */
1599
1600 static uint32_t s3c_adc_read(void *opaque, target_phys_addr_t addr)
1601 {
1602 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1603
1604 switch (addr) {
1605 case S3C_ADCCON:
1606 return s->control;
1607 case S3C_ADCTSC:
1608 return s->ts;
1609 case S3C_ADCDLY:
1610 return s->delay;
1611 case S3C_ADCDAT0:
1612 if (s->control & 2)
1613 s3c_adc_start(s);
1614 return ((!s->down) << 15) | s->xdata;
1615 case S3C_ADCDAT1:
1616 return ((!s->down) << 15) | s->ydata;
1617 default:
1618 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1619 break;
1620 }
1621 return 0;
1622 }
1623
1624 static void s3c_adc_write(void *opaque, target_phys_addr_t addr,
1625 uint32_t value)
1626 {
1627 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1628
1629 switch (addr) {
1630 case S3C_ADCCON:
1631 s->control = (s->control & 0x8000) | (value & 0x7ffe);
1632 s->enable = !(value & 4);
1633 if ((value & 1) && !(value & 2))
1634 s3c_adc_start(s);
1635 if (!s->enable)
1636 qemu_del_timer(s->convt);
1637 s3c_adc_tick(s);
1638 break;
1639
1640 case S3C_ADCTSC:
1641 s->ts = value & 0xff;
1642 break;
1643
1644 case S3C_ADCDLY:
1645 s->delay = value & 0xffff;
1646
1647 default:
1648 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1649 }
1650 }
1651
1652 static CPUReadMemoryFunc *s3c_adc_readfn[] = {
1653 s3c_adc_read,
1654 s3c_adc_read,
1655 s3c_adc_read,
1656 };
1657
1658 static CPUWriteMemoryFunc *s3c_adc_writefn[] = {
1659 s3c_adc_write,
1660 s3c_adc_write,
1661 s3c_adc_write,
1662 };
1663
1664 static void s3c_adc_save(QEMUFile *f, void *opaque)
1665 {
1666 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1667 int i;
1668 qemu_put_be32(f, s->enable);
1669 for (i = 0; i < 8; i ++)
1670 qemu_put_be32(f, s->input[i]);
1671 qemu_put_be32(f, s->in_idx);
1672 qemu_put_be32(f, s->noise);
1673
1674 qemu_put_be16s(f, &s->control);
1675 qemu_put_be16s(f, &s->ts);
1676 qemu_put_be16s(f, &s->delay);
1677 qemu_put_be16s(f, &s->xdata);
1678 qemu_put_be16s(f, &s->ydata);
1679 }
1680
1681 static int s3c_adc_load(QEMUFile *f, void *opaque, int version_id)
1682 {
1683 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *) opaque;
1684 int i;
1685 s->enable = qemu_get_be32(f);
1686 for (i = 0; i < 8; i ++)
1687 s->input[i] = qemu_get_be32(f);
1688 s->in_idx = qemu_get_be32(f);
1689 s->noise = qemu_get_be32(f);
1690
1691 qemu_get_be16s(f, &s->control);
1692 qemu_get_be16s(f, &s->ts);
1693 qemu_get_be16s(f, &s->delay);
1694 qemu_get_be16s(f, &s->xdata);
1695 qemu_get_be16s(f, &s->ydata);
1696
1697 if (s->enable && (s->ts & 7) && !(s->control & (1 << 15)))
1698 s3c_adc_start(s);
1699
1700 return 0;
1701 }
1702
1703 struct s3c_adc_state_s *s3c_adc_init(target_phys_addr_t base, qemu_irq irq,
1704 qemu_irq tcirq)
1705 {
1706 int iomemtype;
1707 struct s3c_adc_state_s *s = (struct s3c_adc_state_s *)
1708 qemu_mallocz(sizeof(struct s3c_adc_state_s));
1709
1710 s->base = base;
1711 s->irq = irq;
1712 s->tcirq = tcirq;
1713 s->convt = qemu_new_timer(vm_clock, s3c_adc_done, s);
1714 s->tst = qemu_new_timer(vm_clock, s3c_adc_tick, s);
1715
1716 s3c_adc_reset(s);
1717
1718 iomemtype = cpu_register_io_memory(0, s3c_adc_readfn,
1719 s3c_adc_writefn, s);
1720 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
1721
1722 /* We want absolute coordinates */
1723 qemu_add_mouse_event_handler(s3c_adc_event, s, 1,
1724 "QEMU S3C2410-driven Touchscreen");
1725
1726 register_savevm("s3c24xx_adc", 0, 0, s3c_adc_save, s3c_adc_load, s);
1727
1728 return s;
1729 }
1730
1731 void s3c_adc_setscale(struct s3c_adc_state_s *adc, const int m[])
1732 {
1733 memcpy(adc->scale, m, 6 * sizeof(int));
1734 }
1735
1736 /* IIC-bus serial interface */
1737 struct s3c_i2c_state_s {
1738 i2c_slave slave;
1739 i2c_bus *bus;
1740 target_phys_addr_t base;
1741 qemu_irq irq;
1742
1743 uint8_t control;
1744 uint8_t status;
1745 uint8_t data;
1746 uint8_t addy;
1747 int busy;
1748 int newstart;
1749 };
1750
1751 static void s3c_i2c_irq(struct s3c_i2c_state_s *s)
1752 {
1753 s->control |= 1 << 4;
1754 if (s->control & (1 << 5))
1755 qemu_irq_raise(s->irq);
1756 }
1757
1758 static void s3c_i2c_reset(struct s3c_i2c_state_s *s)
1759 {
1760 s->control = 0x00;
1761 s->status = 0x00;
1762 s->busy = 0;
1763 s->newstart = 0;
1764 }
1765
1766 static void s3c_i2c_event(i2c_slave *i2c, enum i2c_event event)
1767 {
1768 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) i2c;
1769 if (!(s->status & (1 << 4)))
1770 return;
1771
1772 switch (event) {
1773 case I2C_START_RECV:
1774 case I2C_START_SEND:
1775 s->status |= 1 << 2;
1776 s3c_i2c_irq(s);
1777 break;
1778 case I2C_FINISH:
1779 s->status &= ~6;
1780 break;
1781 case I2C_NACK:
1782 s->status |= 1 << 0;
1783 break;
1784 default:
1785 break;
1786 }
1787 }
1788
1789 static int s3c_i2c_tx(i2c_slave *i2c, uint8_t data)
1790 {
1791 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) i2c;
1792 if (!(s->status & (1 << 4)))
1793 return 1;
1794
1795 if ((s->status >> 6) == 0)
1796 s->data = data; /* TODO */
1797 s->status &= ~(1 << 0);
1798 s3c_i2c_irq(s);
1799
1800 return !(s->control & (1 << 7));
1801 }
1802
1803 static int s3c_i2c_rx(i2c_slave *i2c)
1804 {
1805 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) i2c;
1806 if (!(s->status & (1 << 4)))
1807 return 1;
1808
1809 if ((s->status >> 6) == 1) {
1810 s->status &= ~(1 << 0);
1811 s3c_i2c_irq(s);
1812 return s->data;
1813 }
1814
1815 return 0x00;
1816 }
1817
1818 static void s3c_master_work(void *opaque)
1819 {
1820 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) opaque;
1821 int start = 0, stop = 0, ack = 1;
1822 if (s->control & (1 << 4)) /* Interrupt pending */
1823 return;
1824 if ((s->status & 0x90) != 0x90) /* Master */
1825 return;
1826 stop = ~s->status & (1 << 5);
1827 if (s->newstart && s->status & (1 << 5)) { /* START */
1828 s->busy = 1;
1829 start = 1;
1830 }
1831 s->newstart = 0;
1832 if (!s->busy)
1833 return;
1834
1835 if (start)
1836 ack = !i2c_start_transfer(s->bus, s->data >> 1, (~s->status >> 6) & 1);
1837 else if (stop)
1838 i2c_end_transfer(s->bus);
1839 else if (s->status & (1 << 6))
1840 ack = !i2c_send(s->bus, s->data);
1841 else {
1842 s->data = i2c_recv(s->bus);
1843
1844 if (!(s->control & (1 << 7))) /* ACK */
1845 i2c_nack(s->bus);
1846 }
1847
1848 if (!(s->status & (1 << 5))) {
1849 s->busy = 0;
1850 return;
1851 }
1852 s->status &= ~1;
1853 s->status |= !ack;
1854 if (!ack)
1855 s->busy = 0;
1856 s3c_i2c_irq(s);
1857 }
1858
1859 #define S3C_IICCON 0x00 /* IIC-Bus Control register */
1860 #define S3C_IICSTAT 0x04 /* IIC-Bus Control / Status register */
1861 #define S3C_IICADD 0x08 /* IIC-Bus Address register */
1862 #define S3C_IICDS 0x0c /* IIC-Bus Tx / Rx Data Shift register */
1863
1864 static uint32_t s3c_i2c_read(void *opaque, target_phys_addr_t addr)
1865 {
1866 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) opaque;
1867
1868 switch (addr) {
1869 case S3C_IICCON:
1870 return s->control;
1871 case S3C_IICSTAT:
1872 return s->status & ~(1 << 5); /* Busy signal */
1873 case S3C_IICADD:
1874 return s->addy;
1875 case S3C_IICDS:
1876 return s->data;
1877 default:
1878 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1879 break;
1880 }
1881 return 0;
1882 }
1883
1884 static void s3c_i2c_write(void *opaque, target_phys_addr_t addr,
1885 uint32_t value)
1886 {
1887 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) opaque;
1888
1889 switch (addr) {
1890 case S3C_IICCON:
1891 s->control = (s->control | 0xef) & value;
1892 if (s->busy)
1893 s3c_master_work(s);
1894 break;
1895
1896 case S3C_IICSTAT:
1897 s->status &= 0x0f;
1898 s->status |= value & 0xf0;
1899 if (s->status & (1 << 5))
1900 s->newstart = 1;
1901 s3c_master_work(s);
1902 break;
1903
1904 case S3C_IICADD:
1905 s->addy = value & 0x7f;
1906 i2c_set_slave_address(&s->slave, s->addy);
1907 break;
1908
1909 case S3C_IICDS:
1910 s->data = value & 0xff;
1911 break;
1912
1913 default:
1914 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
1915 }
1916 }
1917
1918 static CPUReadMemoryFunc *s3c_i2c_readfn[] = {
1919 s3c_i2c_read,
1920 s3c_i2c_read,
1921 s3c_i2c_read,
1922 };
1923
1924 static CPUWriteMemoryFunc *s3c_i2c_writefn[] = {
1925 s3c_i2c_write,
1926 s3c_i2c_write,
1927 s3c_i2c_write,
1928 };
1929
1930 static void s3c_i2c_save(QEMUFile *f, void *opaque)
1931 {
1932 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) opaque;
1933 qemu_put_8s(f, &s->control);
1934 qemu_put_8s(f, &s->status);
1935 qemu_put_8s(f, &s->data);
1936 qemu_put_8s(f, &s->addy);
1937
1938 qemu_put_be32(f, s->busy);
1939 qemu_put_be32(f, s->newstart);
1940
1941 // i2c_bus_save(f, s->bus);
1942 i2c_slave_save(f, &s->slave);
1943 }
1944
1945 static int s3c_i2c_load(QEMUFile *f, void *opaque, int version_id)
1946 {
1947 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *) opaque;
1948 qemu_get_8s(f, &s->control);
1949 qemu_get_8s(f, &s->status);
1950 qemu_get_8s(f, &s->data);
1951 qemu_get_8s(f, &s->addy);
1952
1953 s->busy = qemu_get_be32(f);
1954 s->newstart = qemu_get_be32(f);
1955
1956 // i2c_bus_load(f, s->bus);
1957 i2c_slave_load(f, &s->slave);
1958 return 0;
1959 }
1960
1961 struct s3c_i2c_state_s *s3c_i2c_init(target_phys_addr_t base, qemu_irq irq)
1962 {
1963 int iomemtype;
1964 struct s3c_i2c_state_s *s = (struct s3c_i2c_state_s *)
1965 qemu_mallocz(sizeof(struct s3c_i2c_state_s));
1966
1967 s->base = base;
1968 s->irq = irq;
1969 s->slave.event = s3c_i2c_event;
1970 s->slave.send = s3c_i2c_tx;
1971 s->slave.recv = s3c_i2c_rx;
1972 s->bus = i2c_init_bus();
1973
1974 s3c_i2c_reset(s);
1975
1976 iomemtype = cpu_register_io_memory(0, s3c_i2c_readfn,
1977 s3c_i2c_writefn, s);
1978 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
1979
1980 register_savevm("s3c24xx_i2c", 0, 0, s3c_i2c_save, s3c_i2c_load, s);
1981
1982 return s;
1983 }
1984
1985 i2c_bus *s3c_i2c_bus(struct s3c_i2c_state_s *s)
1986 {
1987 return s->bus;
1988 }
1989
1990 /* Serial Peripheral Interface */
1991 struct s3c_spi_state_s {
1992 target_phys_addr_t base;
1993
1994 struct {
1995 qemu_irq irq;
1996 qemu_irq drq;
1997 qemu_irq miso;
1998
1999 uint8_t control;
2000 uint8_t pin;
2001 uint8_t pre;
2002
2003 int cs_pin;
2004 int clk_pin;
2005 int mosi_pin;
2006 uint8_t txbuf;
2007 uint8_t rxbuf;
2008 int bit;
2009 } chan[2];
2010
2011 uint8_t (*txrx[2])(void *opaque, uint8_t value);
2012 uint8_t (*btxrx[2])(void *opaque, uint8_t value);
2013 void *opaque[2];
2014 };
2015
2016 static void s3c_spi_update(struct s3c_spi_state_s *s)
2017 {
2018 int i;
2019 for (i = 0; i < 2; i ++) {
2020 switch ((s->chan[i].control >> 5) & 3) { /* SMOD */
2021 case 1:
2022 qemu_irq_raise(s->chan[i].irq);
2023 break;
2024 case 2:
2025 qemu_irq_raise(s->chan[i].drq);
2026 break;
2027 }
2028 }
2029 }
2030
2031 static void s3c_spi_reset(struct s3c_spi_state_s *s)
2032 {
2033 memset(s->chan, 0, sizeof(s->chan));
2034 s->chan[0].pin = 0x02;
2035 s->chan[1].pin = 0x02;
2036 s3c_spi_update(s);
2037 }
2038
2039 #define S3C_SPCON0 0x00 /* SPI channel 0 control register */
2040 #define S3C_SPSTA0 0x04 /* SPI channel 0 status register */
2041 #define S3C_SPPIN0 0x08 /* SPI channel 0 pin control register */
2042 #define S3C_SPPRE0 0x0c /* SPI channel 0 baudrate prescaler register */
2043 #define S3C_SPTDAT0 0x10 /* SPI channel 0 Tx data register */
2044 #define S3C_SPRDAT0 0x14 /* SPI channel 0 Rx data register */
2045 #define S3C_SPCON1 0x20 /* SPI channel 1 control register */
2046 #define S3C_SPSTA1 0x24 /* SPI channel 1 status register */
2047 #define S3C_SPPIN1 0x28 /* SPI channel 1 pin control register */
2048 #define S3C_SPPRE1 0x2c /* SPI channel 1 baudrate prescaler register */
2049 #define S3C_SPTDAT1 0x30 /* SPI channel 1 Tx data register */
2050 #define S3C_SPRDAT1 0x34 /* SPI channel 1 Rx data register */
2051
2052 static uint32_t s3c_spi_read(void *opaque, target_phys_addr_t addr)
2053 {
2054 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2055 int ch;
2056
2057 ch = addr >> 5;
2058
2059 switch (addr) {
2060 case S3C_SPCON0:
2061 case S3C_SPCON1:
2062 return s->chan[ch].control;
2063
2064 case S3C_SPSTA0:
2065 case S3C_SPSTA1:
2066 return 0x01;
2067
2068 case S3C_SPPIN0:
2069 case S3C_SPPIN1:
2070 return s->chan[ch].pin;
2071
2072 case S3C_SPPRE0:
2073 case S3C_SPPRE1:
2074 return s->chan[ch].pre;
2075
2076 case S3C_SPTDAT0:
2077 case S3C_SPTDAT1:
2078 return s->chan[ch + 2].txbuf;
2079
2080 case S3C_SPRDAT0:
2081 case S3C_SPRDAT1:
2082 if (s->txrx[ch] && (s->chan[ch].control & 0x19) == 0x19)
2083 s->chan[ch].rxbuf = s->txrx[ch](s->opaque[ch], 'Q');
2084 s3c_spi_update(s);
2085 return s->chan[ch].rxbuf;
2086
2087 default:
2088 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2089 break;
2090 }
2091 return 0;
2092 }
2093
2094 static void s3c_spi_write(void *opaque, target_phys_addr_t addr,
2095 uint32_t value)
2096 {
2097 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2098 int ch;
2099
2100 ch = addr >> 5;
2101
2102 switch (addr) {
2103 case S3C_SPCON0:
2104 case S3C_SPCON1:
2105 s->chan[ch].control = value & 0x7f;
2106 s3c_spi_update(s);
2107 break;
2108
2109 case S3C_SPPIN0:
2110 case S3C_SPPIN1:
2111 s->chan[ch].pin = value & 0x07;
2112 break;
2113
2114 case S3C_SPPRE0:
2115 case S3C_SPPRE1:
2116 s->chan[ch].pre = value & 0xff;
2117 break;
2118
2119 case S3C_SPTDAT0:
2120 case S3C_SPTDAT1:
2121 s->chan[ch].txbuf = value & 0xff;
2122 if (s->txrx[ch] && (s->chan[ch].control & 0x19) == 0x18)
2123 s->chan[ch].rxbuf = s->txrx[ch](s->opaque[ch], value & 0xff);
2124 s3c_spi_update(s);
2125 break;
2126
2127 default:
2128 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2129 }
2130 }
2131
2132 static CPUReadMemoryFunc *s3c_spi_readfn[] = {
2133 s3c_spi_read,
2134 s3c_spi_read,
2135 s3c_spi_read,
2136 };
2137
2138 static CPUWriteMemoryFunc *s3c_spi_writefn[] = {
2139 s3c_spi_write,
2140 s3c_spi_write,
2141 s3c_spi_write,
2142 };
2143
2144 static void s3c_spi_save(QEMUFile *f, void *opaque)
2145 {
2146 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2147 int i;
2148 for (i = 0; i < 2; i ++) {
2149 qemu_put_8s(f, &s->chan[i].control);
2150 qemu_put_8s(f, &s->chan[i].pin);
2151 qemu_put_8s(f, &s->chan[i].pre);
2152
2153 qemu_put_8s(f, &s->chan[i].txbuf);
2154 qemu_put_8s(f, &s->chan[i].rxbuf);
2155 qemu_put_be32(f, s->chan[i].cs_pin);
2156 qemu_put_be32(f, s->chan[i].clk_pin);
2157 qemu_put_be32(f, s->chan[i].mosi_pin);
2158 qemu_put_be32(f, s->chan[i].bit);
2159 }
2160 }
2161
2162 static int s3c_spi_load(QEMUFile *f, void *opaque, int version_id)
2163 {
2164 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2165 int i;
2166 for (i = 0; i < 2; i ++) {
2167 qemu_get_8s(f, &s->chan[i].control);
2168 qemu_get_8s(f, &s->chan[i].pin);
2169 qemu_get_8s(f, &s->chan[i].pre);
2170
2171 qemu_get_8s(f, &s->chan[i].txbuf);
2172 qemu_get_8s(f, &s->chan[i].rxbuf);
2173 s->chan[i].cs_pin = qemu_get_be32(f);
2174 s->chan[i].clk_pin = qemu_get_be32(f);
2175 s->chan[i].mosi_pin = qemu_get_be32(f);
2176 s->chan[i].bit = qemu_get_be32(f);
2177 }
2178
2179 return 0;
2180 }
2181
2182 static void s3c_spi_bitbang_cs(void *opaque, int line, int level)
2183 {
2184 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2185 int ch = line;
2186 if (s->chan[ch].cs_pin || level) {
2187 if (s->chan[ch].bit && s->txrx[ch] && !s->btxrx[ch]) {
2188 s->chan[ch].txbuf <<= 8 - s->chan[ch].bit;
2189 s->chan[ch].rxbuf = s->txrx[ch](s->opaque[ch], s->chan[ch].txbuf);
2190 }
2191 } else if (!s->chan[ch].cs_pin || !level)
2192 s->chan[ch].bit = 0;
2193
2194 /* SSn is active low. */
2195 s->chan[ch].cs_pin = !level;
2196 }
2197
2198 static void s3c_spi_bitbang_clk(void *opaque, int line, int level)
2199 {
2200 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2201 int ch = line;
2202 if (!s->chan[ch].cs_pin)
2203 goto done;
2204
2205 /* Detect CLK rising edge */
2206 if (s->chan[ch].clk_pin || !level)
2207 goto done;
2208
2209 if (s->btxrx[ch]) {
2210 qemu_set_irq(s->chan[ch].miso,
2211 s->btxrx[ch](s->opaque[ch], s->chan[ch].mosi_pin));
2212 goto done;
2213 }
2214
2215 s->chan[ch].txbuf <<= 1;
2216 s->chan[ch].txbuf |= s->chan[ch].mosi_pin;
2217
2218 qemu_set_irq(s->chan[ch].miso, (s->chan[ch].rxbuf >> 7) & 1);
2219 s->chan[ch].rxbuf <<= 1;
2220
2221 if (++ s->chan[ch].bit == 8) {
2222 if (s->txrx[ch])
2223 s->chan[ch].rxbuf = s->txrx[ch](s->opaque[ch], s->chan[ch].txbuf);
2224 s->chan[ch].bit = 0;
2225 }
2226
2227 done:
2228 s->chan[ch].clk_pin = level;
2229 }
2230
2231 static void s3c_spi_bitbang_mosi(void *opaque, int line, int level)
2232 {
2233 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *) opaque;
2234 int ch = line;
2235 s->chan[ch].mosi_pin = level;
2236 }
2237
2238 static const struct {
2239 int cs, clk, miso, mosi;
2240 } s3c_spi_pins[2] = {
2241 { S3C_GPG(2), S3C_GPE(13), S3C_GPE(11), S3C_GPE(12) },
2242 { S3C_GPG(3), S3C_GPG(7), S3C_GPG(5), S3C_GPG(6) },
2243 };
2244
2245 static void s3c_spi_bitbang_init(struct s3c_spi_state_s *s,
2246 struct s3c_gpio_state_s *gpio)
2247 {
2248 int i;
2249 qemu_irq *cs = qemu_allocate_irqs(s3c_spi_bitbang_cs, s, 2);
2250 qemu_irq *clk = qemu_allocate_irqs(s3c_spi_bitbang_clk, s, 2);
2251 qemu_irq *mosi = qemu_allocate_irqs(s3c_spi_bitbang_mosi, s, 2);
2252
2253 for (i = 0; i < 2; i ++) {
2254 s3c_gpio_out_set(gpio, s3c_spi_pins[i].cs, cs[i]);
2255 s3c_gpio_out_set(gpio, s3c_spi_pins[i].clk, clk[i]);
2256 s->chan[i].miso = s3c_gpio_in_get(gpio)[s3c_spi_pins[i].miso];
2257 s3c_gpio_out_set(gpio, s3c_spi_pins[i].mosi, mosi[i]);
2258 }
2259 }
2260
2261 struct s3c_spi_state_s *s3c_spi_init(target_phys_addr_t base,
2262 qemu_irq irq0, qemu_irq drq0, qemu_irq irq1, qemu_irq drq1,
2263 struct s3c_gpio_state_s *gpio)
2264 {
2265 int iomemtype;
2266 struct s3c_spi_state_s *s = (struct s3c_spi_state_s *)
2267 qemu_mallocz(sizeof(struct s3c_spi_state_s));
2268
2269 s->base = base;
2270 s->chan[0].irq = irq0;
2271 s->chan[0].drq = drq0;
2272 s->chan[1].irq = irq1;
2273 s->chan[1].drq = drq1;
2274
2275 s3c_spi_reset(s);
2276
2277 iomemtype = cpu_register_io_memory(0, s3c_spi_readfn,
2278 s3c_spi_writefn, s);
2279 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
2280
2281 s3c_spi_bitbang_init(s, gpio);
2282
2283 register_savevm("s3c24xx_spi", 0, 0, s3c_spi_save, s3c_spi_load, s);
2284
2285 return s;
2286 }
2287
2288 void s3c_spi_attach(struct s3c_spi_state_s *s, int ch,
2289 uint8_t (*txrx)(void *opaque, uint8_t value),
2290 uint8_t (*btxrx)(void *opaque, uint8_t value), void *opaque)
2291 {
2292 if (ch & ~1)
2293 cpu_abort(cpu_single_env, "%s: No channel %i\n", __FUNCTION__, ch);
2294 s->txrx[ch] = txrx;
2295 s->btxrx[ch] = btxrx;
2296 s->opaque[ch] = opaque;
2297 }
2298
2299 /* IIS-BUS interface */
2300 static inline void s3c_i2s_update(struct s3c_i2s_state_s *s)
2301 {
2302 s->tx_en =
2303 (s->control & (1 << 0)) && !(s->control & (1 << 3)) &&
2304 (s->mode & (1 << 7)) && (s->fcontrol & (1 << 13));
2305 s->rx_en =
2306 (s->control & (1 << 0)) && !(s->control & (1 << 2)) &&
2307 (s->mode & (1 << 6)) && (s->fcontrol & (1 << 12));
2308 s->control &= ~0xc0;
2309 /* The specs are unclear about the FIFO-ready flags logic.
2310 * Implement semantics that make most sense. */
2311 if (s->tx_en && s->tx_len)
2312 s->control |= (1 << 7);
2313 if (s->rx_en && s->rx_len)
2314 s->control |= (1 << 6);
2315
2316 qemu_set_irq(s->dma[S3C_RQ_I2SSDO], (s->control >> 5) &
2317 (s->control >> 7) & (s->fcontrol >> 15) & 1);
2318 qemu_set_irq(s->dma[S3C_RQ_I2SSDI0], (s->control >> 4) &
2319 (s->control >> 6) & (s->fcontrol >> 14) & 1);
2320 qemu_set_irq(s->dma[S3C_RQ_I2SSDI1], (s->control >> 4) &
2321 (s->control >> 6) & (s->fcontrol >> 14) & 1);
2322 }
2323
2324 static void s3c_i2s_reset(struct s3c_i2s_state_s *s)
2325 {
2326 s->control = 0x100;
2327 s->mode = 0x000;
2328 s->prescaler = 0x000;
2329 s->fcontrol = 0x0000;
2330 s->tx_len = 0;
2331 s->rx_len = 0;
2332 s3c_i2s_update(s);
2333 }
2334
2335 #define S3C_IISCON 0x00 /* IIS Control register */
2336 #define S3C_IISMOD 0x04 /* IIS Mode register */
2337 #define S3C_IISPSR 0x08 /* IIS Prescaler register */
2338 #define S3C_IISFCON 0x0c /* IIS FIFO Interface register */
2339 #define S3C_IISFIFO 0x10 /* IIS FIFO register */
2340
2341 static uint32_t s3c_i2s_read(void *opaque, target_phys_addr_t addr)
2342 {
2343 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *) opaque;
2344 uint32_t ret;
2345
2346 switch (addr) {
2347 case S3C_IISCON:
2348 return s->control;
2349 case S3C_IISMOD:
2350 return s->mode;
2351 case S3C_IISPSR:
2352 return s->prescaler;
2353 case S3C_IISFCON:
2354 return s->fcontrol |
2355 (MAX(32 - s->tx_len, 0) << 6) |
2356 MIN(s->rx_len, 32);
2357 case S3C_IISFIFO:
2358 if (s->rx_len > 0) {
2359 s->rx_len --;
2360 s3c_i2s_update(s);
2361 s->cycle ^= 1;
2362 if (s->cycle) {
2363 s->buffer = (uint16_t) (ret = s->codec_in(s->opaque));
2364 return ret >> 16;
2365 } else
2366 return s->buffer;
2367 }
2368 default:
2369 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2370 break;
2371 }
2372 return 0;
2373 }
2374
2375 static void s3c_i2s_write(void *opaque, target_phys_addr_t addr,
2376 uint32_t value)
2377 {
2378 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *) opaque;
2379
2380 switch (addr) {
2381 case S3C_IISCON:
2382 s->control = (s->control & 0x100) | (value & 0x03f);
2383 s3c_i2s_update(s);
2384 break;
2385 case S3C_IISMOD:
2386 s->mode = value & 0x1ff;
2387 s3c_i2s_update(s);
2388 break;
2389 case S3C_IISPSR:
2390 s->prescaler = value & 0x3ff;
2391 break;
2392 case S3C_IISFCON:
2393 s->fcontrol = value & 0xf000;
2394 s3c_i2s_update(s);
2395 break;
2396 case S3C_IISFIFO:
2397 if (s->tx_len && s->tx_en) {
2398 s->tx_len --;
2399 s3c_i2s_update(s);
2400 if (s->cycle)
2401 s->codec_out(s->opaque, value | ((uint32_t) s->buffer << 16));
2402 else
2403 s->buffer = (uint16_t) value;
2404 s->cycle ^= 1;
2405 }
2406 break;
2407 default:
2408 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2409 }
2410 }
2411
2412 static CPUReadMemoryFunc *s3c_i2s_readfn[] = {
2413 s3c_i2s_read,
2414 s3c_i2s_read,
2415 s3c_i2s_read,
2416 };
2417
2418 static CPUWriteMemoryFunc *s3c_i2s_writefn[] = {
2419 s3c_i2s_write,
2420 s3c_i2s_write,
2421 s3c_i2s_write,
2422 };
2423
2424 static void s3c_i2s_save(QEMUFile *f, void *opaque)
2425 {
2426 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *) opaque;
2427 qemu_put_be16s(f, &s->control);
2428 qemu_put_be16s(f, &s->mode);
2429 qemu_put_be16s(f, &s->prescaler);
2430 qemu_put_be16s(f, &s->fcontrol);
2431
2432 qemu_put_be32(f, s->tx_en);
2433 qemu_put_be32(f, s->rx_en);
2434 qemu_put_be32(f, s->tx_len);
2435 qemu_put_be32(f, s->rx_len);
2436 qemu_put_be16(f, s->buffer);
2437 qemu_put_be32(f, s->cycle);
2438 }
2439
2440 static int s3c_i2s_load(QEMUFile *f, void *opaque, int version_id)
2441 {
2442 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *) opaque;
2443 qemu_get_be16s(f, &s->control);
2444 qemu_get_be16s(f, &s->mode);
2445 qemu_get_be16s(f, &s->prescaler);
2446 qemu_get_be16s(f, &s->fcontrol);
2447
2448 s->tx_en = qemu_get_be32(f);
2449 s->rx_en = qemu_get_be32(f);
2450 s->tx_len = qemu_get_be32(f);
2451 s->rx_len = qemu_get_be32(f);
2452 s->buffer = qemu_get_be16(f);
2453 s->cycle = qemu_get_be32(f);
2454
2455 return 0;
2456 }
2457
2458 static void s3c_i2s_data_req(void *opaque, int tx, int rx)
2459 {
2460 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *) opaque;
2461 s->tx_len = tx;
2462 s->rx_len = rx;
2463 s3c_i2s_update(s);
2464 }
2465
2466 struct s3c_i2s_state_s *s3c_i2s_init(target_phys_addr_t base, qemu_irq *dma)
2467 {
2468 int iomemtype;
2469 struct s3c_i2s_state_s *s = (struct s3c_i2s_state_s *)
2470 qemu_mallocz(sizeof(struct s3c_i2s_state_s));
2471
2472 s->base = base;
2473 s->dma = dma;
2474 s->data_req = s3c_i2s_data_req;
2475
2476 s3c_i2s_reset(s);
2477
2478 iomemtype = cpu_register_io_memory(0, s3c_i2s_readfn,
2479 s3c_i2s_writefn, s);
2480 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
2481
2482 register_savevm("s3c24xx_iis", 0, 0, s3c_i2s_save, s3c_i2s_load, s);
2483
2484 return s;
2485 }
2486
2487 /* Watchdog Timer */
2488 struct s3c_wdt_state_s {
2489 target_phys_addr_t base;
2490 qemu_irq irq;
2491 uint16_t control;
2492 uint16_t data;
2493 uint16_t count;
2494 QEMUTimer *tm;
2495 int64_t timestamp;
2496 };
2497
2498 static void s3c_wdt_start(struct s3c_wdt_state_s *s)
2499 {
2500 int enable = s->control & (1 << 5);
2501 int prescaler = (s->control >> 8) + 1;
2502 int divider = prescaler << (((s->control >> 3) & 3) + 4);
2503 if (enable) {
2504 s->timestamp = qemu_get_clock(vm_clock);
2505 qemu_mod_timer(s->tm, s->timestamp + muldiv64(divider * s->count,
2506 ticks_per_sec, S3C_PCLK_FREQ));
2507 } else
2508 qemu_del_timer(s->tm);
2509 }
2510
2511 static void s3c_wdt_stop(struct s3c_wdt_state_s *s)
2512 {
2513 int prescaler = (s->control >> 8) + 1;
2514 int divider = prescaler << (((s->control >> 3) & 3) + 4);
2515 int diff;
2516
2517 diff = muldiv64(qemu_get_clock(vm_clock) - s->timestamp, S3C_PCLK_FREQ,
2518 ticks_per_sec) / divider;
2519 s->count -= MIN(s->count, diff);
2520 s->timestamp = qemu_get_clock(vm_clock);
2521 }
2522
2523 static void s3c_wdt_reset(struct s3c_wdt_state_s *s)
2524 {
2525 s->control = 0x8021;
2526 s->data = 0x8000;
2527 s->count = 0x8000;
2528 s3c_wdt_start(s);
2529 }
2530
2531 static void s3c_wdt_timeout(void *opaque)
2532 {
2533 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *) opaque;
2534 if (s->control & (1 << 0)) {
2535 qemu_system_reset_request();
2536 return;
2537 }
2538 if (s->control & (1 << 2))
2539 qemu_irq_raise(s->irq);
2540 s->count = s->data;
2541 s3c_wdt_start(s);
2542 }
2543
2544 #define S3C_WTCON 0x00 /* Watchdog timer control register */
2545 #define S3C_WTDAT 0x04 /* Watchdog timer data register */
2546 #define S3C_WTCNT 0x08 /* Watchdog timer count register */
2547
2548 static uint32_t s3c_wdt_read(void *opaque, target_phys_addr_t addr)
2549 {
2550 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *) opaque;
2551
2552 switch (addr) {
2553 case S3C_WTCON:
2554 return s->control;
2555 case S3C_WTDAT:
2556 return s->data;
2557 case S3C_WTCNT:
2558 s3c_wdt_stop(s);
2559 return s->count;
2560 default:
2561 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2562 break;
2563 }
2564 return 0;
2565 }
2566
2567 static void s3c_wdt_write(void *opaque, target_phys_addr_t addr,
2568 uint32_t value)
2569 {
2570 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *) opaque;
2571
2572 switch (addr) {
2573 case S3C_WTCON:
2574 s3c_wdt_stop(s);
2575 s->control = value;
2576 s3c_wdt_start(s);
2577 break;
2578 case S3C_WTDAT:
2579 s->data = value;
2580 break;
2581 case S3C_WTCNT:
2582 s->count = value;
2583 s3c_wdt_start(s);
2584 break;
2585 default:
2586 printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
2587 }
2588 }
2589
2590 static CPUReadMemoryFunc *s3c_wdt_readfn[] = {
2591 s3c_wdt_read,
2592 s3c_wdt_read,
2593 s3c_wdt_read,
2594 };
2595
2596 static CPUWriteMemoryFunc *s3c_wdt_writefn[] = {
2597 s3c_wdt_write,
2598 s3c_wdt_write,
2599 s3c_wdt_write,
2600 };
2601
2602 static void s3c_wdt_save(QEMUFile *f, void *opaque)
2603 {
2604 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *) opaque;
2605
2606 s3c_wdt_stop(s);
2607 qemu_put_be16s(f, &s->control);
2608 qemu_put_be16s(f, &s->data);
2609 qemu_put_be16s(f, &s->count);
2610 qemu_put_be64s(f, &s->timestamp);
2611 }
2612
2613 static int s3c_wdt_load(QEMUFile *f, void *opaque, int version_id)
2614 {
2615 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *) opaque;
2616
2617 qemu_get_be16s(f, &s->control);
2618 qemu_get_be16s(f, &s->data);
2619 qemu_get_be16s(f, &s->count);
2620 qemu_get_be64s(f, &s->timestamp);
2621 s3c_wdt_start(s);
2622
2623 return 0;
2624 }
2625
2626 struct s3c_wdt_state_s *s3c_wdt_init(target_phys_addr_t base, qemu_irq irq)
2627 {
2628 int iomemtype;
2629 struct s3c_wdt_state_s *s = (struct s3c_wdt_state_s *)
2630 qemu_mallocz(sizeof(struct s3c_wdt_state_s));
2631
2632 s->base = base;
2633 s->irq = irq;
2634 s->tm = qemu_new_timer(vm_clock, s3c_wdt_timeout, s);
2635
2636 s3c_wdt_reset(s);
2637
2638 iomemtype = cpu_register_io_memory(0, s3c_wdt_readfn,
2639 s3c_wdt_writefn, s);
2640 cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
2641
2642 register_savevm("s3c24xx_wdt", 0, 0, s3c_wdt_save, s3c_wdt_load, s);
2643
2644 return s;
2645 }
2646
2647 /* On-chip UARTs */
2648 static struct {
2649 target_phys_addr_t base;
2650 int irq[3];
2651 int dma[1];
2652 } s3c2410_uart[] = {
2653 {
2654 0x50000000,
2655 { S3C_PICS_RXD0, S3C_PICS_TXD0, S3C_PICS_ERR0 },
2656 { S3C_RQ_UART0 },
2657 },
2658 {
2659 0x50004000,
2660 { S3C_PICS_RXD1, S3C_PICS_TXD1, S3C_PICS_ERR1 },
2661 { S3C_RQ_UART1 },
2662 },
2663 {
2664 0x50008000,
2665 { S3C_PICS_RXD2, S3C_PICS_TXD2, S3C_PICS_ERR2 },
2666 { S3C_RQ_UART2 },
2667 },
2668 { 0, { 0, 0, 0 }, { 0 } }
2669 };
2670
2671 /* General CPU reset */
2672 static void s3c2410_reset(void *opaque)
2673 {
2674 struct s3c_state_s *s = (struct s3c_state_s *) opaque;
2675 int i;
2676 s3c_mc_reset(s);
2677 s3c_pic_reset(s->pic);
2678 s3c_dma_reset(s->dma);
2679 s3c_gpio_reset(s->io);
2680 s3c_lcd_reset(s->lcd);
2681 s3c_timers_reset(s->timers);
2682 s3c_mmci_reset(s->mmci);
2683 s3c_adc_reset(s->adc);
2684 s3c_i2c_reset(s->i2c);
2685 s3c_i2s_reset(s->i2s);
2686 s3c_rtc_reset(s->rtc);
2687 s3c_spi_reset(s->spi);
2688 s3c_udc_reset(s->udc);
2689 s3c_wdt_reset(s->wdt);
2690 s3c_clkpwr_reset(s);
2691 // s3c_nand_reset(s);
2692 s->nand->reset(s->nand);
2693 for (i = 0; s3c2410_uart[i].base; i ++)
2694 s3c_uart_reset(s->uart[i]);
2695 cpu_reset(s->env);
2696 }
2697
2698 struct s3c_state_s * g_s3c;
2699
2700 /* Initialise an S3C24XX microprocessor. */
2701 struct s3c_state_s *s3c24xx_init(
2702 uint32_t cpu_id,
2703 unsigned int sdram_size,
2704 uint32_t sram_address,
2705 SDState *mmc)
2706 {
2707 struct s3c_state_s *s;
2708 int iomemtype, i;
2709 s = (struct s3c_state_s *) qemu_mallocz(sizeof(struct s3c_state_s));
2710
2711 s->cpu_id = cpu_id;
2712
2713 s->env = cpu_init("arm920t");
2714 if (!s->env) {
2715 fprintf(stderr, "Unable to initialize ARM920T\n");
2716 exit(2);
2717 }
2718 register_savevm("s3c24xx", 0, 0,
2719 cpu_save, cpu_load, s->env);
2720
2721 cpu_register_physical_memory(S3C_RAM_BASE, sdram_size,
2722 qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
2723
2724 /* If OM pins are 00, SRAM is mapped at 0x0 instead. */
2725 cpu_register_physical_memory(sram_address, S3C_SRAM_SIZE,
2726 qemu_ram_alloc(S3C_SRAM_SIZE) | IO_MEM_RAM);
2727
2728 s->mc_base = 0x48000000;
2729 s3c_mc_reset(s);
2730 iomemtype = cpu_register_io_memory(0, s3c_mc_readfn, s3c_mc_writefn, s);
2731 cpu_register_physical_memory(s->mc_base, 0xffffff, iomemtype);
2732 register_savevm("s3c24xx_mc", 0, 0, s3c_mc_save, s3c_mc_load, s);
2733
2734 s->pic = s3c_pic_init(0x4a000000, arm_pic_init_cpu(s->env));
2735 s->irq = s3c_pic_get(s->pic);
2736
2737 s->dma = s3c_dma_init(0x4b000000, &s->irq[S3C_PIC_DMA0]);
2738 s->drq = s3c_dma_get(s->dma);
2739
2740 s->clkpwr_base = 0x4c000000;
2741 s3c_clkpwr_reset(s);
2742 iomemtype = cpu_register_io_memory(0, s3c_clkpwr_readfn,
2743 s3c_clkpwr_writefn, s);
2744 cpu_register_physical_memory(s->clkpwr_base, 0xffffff, iomemtype);
2745 register_savevm("s3c24xx_clkpwr", 0, 0,
2746 s3c_clkpwr_save, s3c_clkpwr_load, s);
2747
2748 s->lcd = s3c_lcd_init(0x4d000000, s->irq[S3C_PIC_LCD]);
2749
2750 if (s->cpu_id == S3C_CPU_2440)
2751 s->nand = s3c2440_nand_init();
2752 else
2753 s->nand = s3c2410_nand_init();
2754
2755 for (i = 0; s3c2410_uart[i].base; i ++) {
2756 s->uart[i] = s3c_uart_init(s3c2410_uart[i].base,
2757 &s->irq[s3c2410_uart[i].irq[0]],
2758 &s->drq[s3c2410_uart[i].dma[0]]);
2759 if (serial_hds[i])
2760 s3c_uart_attach(s->uart[i], serial_hds[i]);
2761 }
2762
2763 s->timers = s3c_timers_init(0x51000000, &s->irq[S3C_PIC_TIMER0], s->drq);
2764
2765 s->udc = s3c_udc_init(0x52000000, s->irq[S3C_PIC_USBD], s->drq);
2766
2767 s->wdt = s3c_wdt_init(0x53000000, s->irq[S3C_PIC_WDT]);
2768
2769 s->i2c = s3c_i2c_init(0x54000000, s->irq[S3C_PIC_IIC]);
2770
2771 s->i2s = s3c_i2s_init(0x55000000, s->drq);
2772
2773 s->io = s3c_gpio_init(0x56000000, s->irq, s->cpu_id);
2774
2775 s->rtc = s3c_rtc_init(0x57000000, s->irq[S3C_PIC_RTC]);
2776
2777 s->adc = s3c_adc_init(0x58000000, s->irq[S3C_PICS_ADC],
2778 s->irq[S3C_PICS_TC]);
2779
2780 s->spi = s3c_spi_init(0x59000000,
2781 s->irq[S3C_PIC_SPI0], s->drq[S3C_RQ_SPI0],
2782 s->irq[S3C_PIC_SPI1], s->drq[S3C_RQ_SPI1], s->io);
2783
2784 s->mmci = s3c_mmci_init(0x5a000000, 0x2410, mmc,
2785 s->irq[S3C_PIC_SDI], s->drq);
2786
2787 if (usb_enabled) {
2788 usb_ohci_init_pxa(0x49000000, 3, -1, s->irq[S3C_PIC_USBH]);
2789 }
2790
2791 qemu_register_reset(s3c2410_reset, s);
2792
2793 s->nand->setwp(s->nand, 1);
2794 //s3c_nand_setwp(s, 1);
2795
2796 /* Power on reset */
2797 s3c_gpio_setpwrstat(s->io, 1);
2798 return s;
2799 }