Merge branch 'master' into verilog-ams
[sverilog.git] / PGenerate.cc
blob03fcfb286f8cbfb3be9209891ca8a1974a7e4ce1
1 /*
2 * Copyright (c) 2006 Stephen Williams (steve@icarus.com)
4 * This source code is free software; you can redistribute it
5 * and/or modify it in source code form under the terms of the GNU
6 * General Public License as published by the Free Software
7 * Foundation; either version 2 of the License, or (at your option)
8 * any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
19 #ifdef HAVE_CVS_IDENT
20 #ident "$Id: PGenerate.cc,v 1.4 2007/06/02 03:42:12 steve Exp $"
21 #endif
23 # include "PGenerate.h"
24 # include "PWire.h"
26 PGenerate::PGenerate(unsigned id)
27 : id_number(id)
29 parent = 0;
32 PGenerate::~PGenerate()
36 PWire* PGenerate::get_wire(perm_string name) const
38 map<perm_string,PWire*>::const_iterator obj = wires.find(name);
39 if (obj == wires.end())
40 return 0;
41 else
42 return (*obj).second;
45 void PGenerate::add_gate(PGate*gate)
47 gates.push_back(gate);
50 void PGenerate::add_behavior(PProcess*proc)
52 behaviors.push_back(proc);