Merge branch 'master' into verilog-ams
[sverilog.git] / PWire.h
blob9ff5975521ea0a3710538910dc7719242a43879c
1 #ifndef __PWire_H
2 #define __PWire_H
3 /*
4 * Copyright (c) 1998-2007 Stephen Williams (steve@icarus.com)
6 * This source code is free software; you can redistribute it
7 * and/or modify it in source code form under the terms of the GNU
8 * General Public License as published by the Free Software
9 * Foundation; either version 2 of the License, or (at your option)
10 * any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
21 #ifdef HAVE_CVS_IDENT
22 #ident "$Id: PWire.h,v 1.21 2007/05/24 04:07:11 steve Exp $"
23 #endif
25 # include "netlist.h"
26 # include "LineInfo.h"
27 # include <map>
28 # include "svector.h"
29 # include "StringHeap.h"
31 #ifdef HAVE_IOSFWD
32 # include <iosfwd>
33 #else
34 class ostream;
35 #endif
37 class PExpr;
38 class Design;
39 class discipline_t;
42 * The different type of PWire::set_range() calls.
44 enum PWSRType {SR_PORT, SR_NET, SR_BOTH};
47 * Wires include nets, registers and ports. A net or register becomes
48 * a port by declaration, so ports are not separate. The module
49 * identifies a port by keeping it in its port list.
51 * The hname parameter to the constructor is a hierarchical name. It
52 * is the name of the wire within a module, so does not include the
53 * current scope or any instances. Modules contain all the wires, so
54 * from that perspective, sub-scopes within the module are a part of
55 * the wire name.
57 class PWire : public LineInfo {
59 public:
60 PWire(perm_string name,
61 NetNet::Type t,
62 NetNet::PortType pt,
63 ivl_variable_type_t dt);
65 // Return a hierarchical name.
66 perm_string basename() const;
68 NetNet::Type get_wire_type() const;
69 bool set_wire_type(NetNet::Type);
71 NetNet::PortType get_port_type() const;
72 bool set_port_type(NetNet::PortType);
74 void set_signed(bool flag);
75 bool get_signed() const;
76 bool get_isint() const;
78 bool set_data_type(ivl_variable_type_t dt);
79 ivl_variable_type_t get_data_type() const;
81 void set_range(PExpr*msb, PExpr*lsb, PWSRType type);
83 void set_memory_idx(PExpr*ldx, PExpr*rdx);
85 void set_discipline(discipline_t*);
86 discipline_t* get_discipline(void) const;
88 map<perm_string,PExpr*> attributes;
90 // Write myself to the specified stream.
91 void dump(ostream&out, unsigned ind=4) const;
93 NetNet* elaborate_sig(Design*, NetScope*scope) const;
95 private:
96 perm_string name_;
97 NetNet::Type type_;
98 NetNet::PortType port_type_;
99 ivl_variable_type_t data_type_;
100 bool signed_;
101 bool isint_; // original type of integer
103 // These members hold expressions for the bit width of the
104 // wire. If they do not exist, the wire is 1 bit wide.
105 PExpr*port_msb_;
106 PExpr*port_lsb_;
107 bool port_set_;
108 PExpr*net_msb_;
109 PExpr*net_lsb_;
110 bool net_set_;
111 unsigned error_cnt_;
113 // If this wire is actually a memory, these indices will give
114 // me the size and address range of the memory.
115 PExpr*lidx_;
116 PExpr*ridx_;
118 discipline_t*discipline_;
120 private: // not implemented
121 PWire(const PWire&);
122 PWire& operator= (const PWire&);
125 #endif