| blob | d7180f4b5707cbc4ef1ba3184699c69a14c6c5f0 |
1 /*
2 * Copyright (c) 1998-2008 Stephen Williams (steve@icarus.com)
3 *
4 * This source code is free software; you can redistribute it
5 * and/or modify it in source code form under the terms of the GNU
6 * General Public License as published by the Free Software
7 * Foundation; either version 2 of the License, or (at your option)
8 * any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
18 */
22 /*
23 * Elaboration takes as input a complete parse tree and the name of a
24 * root module, and generates as output the elaborated design. This
25 * elaborated design is presented as a Module, which does not
26 * reference any other modules. It is entirely self contained.
27 */
29 # include <typeinfo>
30 # include <cstdlib>
31 # include <sstream>
32 # include <list>
46 {
60 }
62 }
66 {
69 }
71 /*
72 * Elaborate the continuous assign. (This is *not* the procedural
73 * assign.) Elaborate the lvalue and rvalue, and do the assignment.
74 */
76 {
88 /* Elaborate the l-value. */
92 }
100 }
102 /* Handle the special case that the rval is simply an
103 identifier. Get the rval as a NetNet, then use NetBUFZ
104 objects to connect it to the l-value. This is necessary to
105 direct drivers. This is how I attach strengths to the
106 assignment operation. */
114 }
116 /* If either lval or rid are real then both must be real. */
124 }
133 }
136 /* If the right hand net is the same type as the left
137 side net (i.e., WIRE/WIRE) then it is enough to just
138 connect them together. Otherwise, put a bufz between
139 them to carry strengths from the rval.
141 While we are at it, handle the case where the r-value
142 is not as wide as the l-value by padding with a
143 constant-0. */
151 /* If the device is linked to itself, a driver is
152 needed. Should I print a warning here? */
156 /* If the nets are different type (i.e., reg vs. tri) then
157 a driver is needed. */
161 /* If there is a delay, then I need a driver to carry
162 it. */
166 /* If there is a strength to be carried, then I need a
167 driver to carry that strength. */
174 /* If the r-value is more narrow then the l-value, pad
175 it to the desired width. */
198 }
210 }
214 /* Don't need a driver, presumably because the
215 r-value already has the needed drivers. Just
216 hook things up. If the r-value is too narrow
217 for the l-value, then sign extend it or zero
218 extend it, whichever makes sense. */
224 }
229 /* Do need a driver. Use BUFZ objects to carry the
230 strength and delays. */
238 else
242 else
246 else
249 }
262 }
265 }
267 /* Elaborate the r-value. Account for the initial decays,
268 which are going to be attached to the last gate before the
269 generated NetNet. */
279 }
285 }
290 /* If either lval or rval are real then both must be real. */
298 }
300 /* If the r-value insists on being smaller then the l-value
301 (perhaps it is explicitly sized) the pad it out to be the
302 right width so that something is connected to all the bits
303 of the l-value. */
307 /* If, on the other hand, the r-value insists on being
308 LARGER then the l-value, use a part select to chop it down
309 down to size. */
321 }
323 /* If there is a rise/fall/decay time, then attach that delay
324 to the drivers for this net. */
327 }
334 }
336 /*
337 * Elaborate a Builtin gate. These normally get translated into
338 * NetLogic nodes that reflect the particular logic function.
339 */
341 {
350 /* If the Verilog source has a range specification for the
351 gates, then I am expected to make more than one
352 gate. Figure out how many are desired. */
365 }
372 }
382 else
392 }
393 }
395 /* Now we have a gate count. Elaborate the output expression
396 only. We do it early so that we can see if we can make a
397 wide gate instead of an array of gates. */
404 }
408 /* Detect the special case that the l-value width exactly
409 matches the gate count. In this case, we will make a single
410 gate that has the desired vector width. */
417 "Collapsed gate array into single wide "
419 }
421 /* Allocate all the netlist nodes for the gates. */
425 /* Calculate the gate delays from the delay expressions
426 given in the source. For logic gates, the decay time
427 is meaningless because it can never go to high
428 impedance. However, the bufif devices can generate
429 'bz output, so we will pretend that anything can.
431 If only one delay value expression is given (i.e., #5
432 nand(foo,...)) then rise, fall and decay times are
433 all the same value. If two values are given, rise and
434 fall times are use, and the decay time is the minimum
435 of the rise and fall times. Finally, if all three
436 values are given, they are taken as specified. */
446 /* Now make as many gates as the bit count dictates. Give each
447 a unique name, and set the delay times. */
450 ostringstream tmp;
454 else
630 instance_width);
670 }
681 }
691 }
701 }
711 }
721 }
728 }
734 /* The logic devices have some uniform processing. Then
735 all may have output delays and output drive strength. */
743 }
747 }
752 /* The gates have all been allocated, this loop runs through
753 the parameters and attaches the ports of the objects. */
762 }
764 ? lval_sig
772 /* Handle the case where there is one gate that
773 carries the whole vector width. */
778 NetReplicate*rep
781 instance_width,
782 instance_width);
794 }
804 }
809 /* Handle the case where a single bit is connected
810 repetitively to all the instances. */
816 /* Handle the general case that each bit of the
817 value is connected to a different instance. In
818 this case, the output is handled slightly
819 different from the inputs. */
824 count);
827 /* Connect the concat to the signal. */
830 /* Connect the outputs of the gates to the concat. */
840 }
843 /* Use part selects to get the bits
844 connected to the inputs of out gate. */
856 }
864 }
866 }
867 }
872 {
893 }
905 }
917 }
922 }
927 }
929 /*
930 * Instantiate a module by recursively elaborating it. Set the path of
931 * the recursive elaboration so that signal names get properly
932 * set. Connect the ports of the instantiated module to the signals of
933 * the parameters. This is done with BUFZ gates so that they look just
934 * like continuous assignment connections.
935 */
937 {
945 }
947 // This is the array of pin expressions, shuffled to match the
948 // order of the declaration. If the source instantiation uses
949 // bind by order, this is the same as the source list.Otherwise,
950 // the source list is rearranged by name binding into this list.
953 // If the instance has a pins_ member, then we know we are
954 // binding by name. Therefore, make up a pins array that
955 // reflects the positions of the named ports.
959 // Scan the bindings, matching them with port names.
962 // Given a binding, look at the module port names
963 // for the position that matches the binding name.
966 // If the port name doesn't exist, the find_port
967 // method will return the port count. Detect that
968 // as an error.
975 }
977 // If I already bound something to this port, then
978 // the pins array will already have a pointer
979 // value where I want to place this expression.
983 endl;
986 }
988 // OK, do the binding by placing the expression in
989 // the right place.
991 }
996 /* Handle the special case that no ports are
997 connected. It is possible that this is an empty
998 connect-by-name list, so we'll allow it and assume
999 that is the case. */
1006 /* Otherwise, this is a positional list of port
1007 connections. In this case, the port count must be
1008 right. Check that is is, the get the pin list. */
1017 }
1019 // No named bindings, just use the positional list I
1020 // already have.
1023 }
1025 // Elaborate these instances of the module. The recursive
1026 // elaboration causes the module to generate a netlist with
1027 // the ports represented by NetNet objects. I will find them
1028 // later.
1033 }
1037 // Now connect the ports of the newly elaborated designs to
1038 // the expressions that are the instantiation parameters. Scan
1039 // the pins, elaborate the expressions attached to them, and
1040 // bind them to the port of the elaborated module.
1042 // This can get rather complicated because the port can be
1043 // unconnected (meaning an empty parameter is passed) connected
1044 // to a concatenation, or connected to an internally
1045 // unconnected port.
1049 // Skip unconnected module ports. This happens when a
1050 // null parameter is passed in.
1054 // While we're here, look to see if this
1055 // unconnected (from the outside) port is an
1056 // input. If so, consider printing a port binding
1057 // warning.
1075 }
1076 }
1079 }
1082 // Inside the module, the port is zero or more signals
1083 // that were already elaborated. List all those signals
1084 // and the NetNet equivalents, for all the instances.
1092 }
1094 // Count the internal vector bits of the port.
1098 // Scan the instances from MSB to LSB. The port
1099 // will be assembled in that order as well.
1102 // Scan the module sub-ports for this instance...
1114 }
1115 }
1117 // If I find that the port is unconnected inside the
1118 // module, then there is nothing to connect. Skip the
1119 // argument.
1122 }
1124 // We know by design that each instance has the same
1125 // width port. Therefore, the prts_pin_count must be an
1126 // even multiple of the instance count.
1133 // Elaborate the expression that connects to the
1134 // module[s] port. sig is the thing outside the module
1135 // that connects to the port.
1141 /* Input to module. elaborate the expression to
1142 the desired width. If this in an instance
1143 array, then let the net determine it's own
1144 width. We use that, then, to decide how to hook
1145 it up.
1147 NOTE that this also handles the case that the
1148 port is actually empty on the inside. We assume
1149 in that case that the port is input. */
1152 desired_vector_width,
1159 }
1163 /* Inout to/from module. This is a more
1164 complicated case, where the expression must be
1165 an lnet, but also an r-value net.
1167 Normally, this winds up being the same as if we
1168 just elaborated as an lnet, as passing a simple
1169 identifier elaborates to the same NetNet in
1170 both cases so the extra elaboration has no
1171 effect. But if the expression passed to the
1172 inout port is a part select, aspecial part
1173 select must be created that can paqss data in
1174 both directions.
1176 Use the elaborate_bi_net method to handle all
1177 the possible cases. */
1189 }
1194 /* Port type must be OUTPUT here. */
1196 /* Output from module. Elaborate the port
1197 expression as the l-value of a continuous
1198 assignment, as the port will continuous assign
1199 into the port. */
1211 }
1213 }
1217 #ifndef NDEBUG
1221 }
1222 #endif
1224 /* If we are working with an instance array, then the
1225 signal width must match the port width exactly. */
1236 }
1242 }
1244 // Check that the parts have matching pin counts. If
1245 // not, they are different widths. Note that idx is 0
1246 // based, but users count parameter positions from 1.
1268 }
1272 }
1274 // Connect the sig expression that is the context of the
1275 // module instance to the ports of the elaborated module.
1277 // The prts_pin_count variable is the total width of the
1278 // port and is the maximum number of connections to
1279 // make. sig is the elaborated expression that connects
1280 // to that port. If sig has too few pins, then reduce
1281 // the number of connections to make.
1283 // Connect this many of the port pins. If the expression
1284 // is too small, then reduce the number of connects.
1289 // The spin_modulus is the width of the signal (not the
1290 // port) if this is an instance array. This causes
1291 // signals wide enough for a single instance to be
1292 // connected to all the instances.
1297 // Now scan the concatenation that makes up the port,
1298 // connecting pins until we run out of port pins or sig
1299 // pins. The sig object is the NetNet that is connected
1300 // to the port from the outside, and the prts object is
1301 // an array of signals to be connected to the sig.
1308 // The simplest case, there are no
1309 // parts/concatenations on the inside of the
1310 // module, so the port and sig need simply be
1311 // connected directly.
1323 }
1325 // The signal width is exactly the width of a
1326 // single instance of the port. In this case,
1327 // connect the sig to all the ports identically.
1334 prts_vector_width,
1341 }
1352 }
1362 }
1379 }
1381 }
1383 }
1385 /*
1386 * From a UDP definition in the source, make a NetUDP
1387 * object. Elaborate the pin expressions as netlists, then connect
1388 * those networks to the pins.
1389 */
1392 {
1399 /* When the parser notices delay expressions in front of a
1400 module or primitive, it interprets them as parameter
1401 overrides. Correct that misconception here. */
1403 PDelays tmp_del;
1415 }
1425 }
1435 }
1437 }
1457 // This is the array of pin expressions, shuffled to match the
1458 // order of the declaration. If the source instantiation uses
1459 // bind by order, this is the same as the source
1460 // list. Otherwise, the source list is rearranged by name
1461 // binding into this list.
1464 // Detect binding by name. If I am binding by name, then make
1465 // up a pins array that reflects the positions of the named
1466 // ports. If this is simply positional binding in the first
1467 // place, then get the binding from the base class.
1472 // Scan the bindings, matching them with port names.
1475 // Given a binding, look at the module port names
1476 // for the position that matches the binding name.
1479 // If the port name doesn't exist, the find_port
1480 // method will return the port count. Detect that
1481 // as an error.
1488 }
1490 // If I already bound something to this port, then
1491 // the (*exp) array will already have a pointer
1492 // value where I want to place this expression.
1496 endl;
1499 }
1501 // OK, do the binding by placing the expression in
1502 // the right place.
1504 }
1508 /* Otherwise, this is a positional list of port
1509 connections. In this case, the port count must be
1510 right. Check that is is, the get the pin list. */
1519 }
1521 // No named bindings, just use the positional list I
1522 // already have.
1525 }
1528 /* Handle the output port of the primitive special. It is an
1529 output port (the only output port) so must be passed an
1530 l-value net. */
1546 }
1547 }
1549 /* Run through the pins, making netlists for the pin
1550 expressions and connecting them to the pin in question. All
1551 of this is independent of the nature of the UDP. */
1561 }
1564 }
1566 // All done. Add the object to the design.
1568 }
1572 {
1573 // Look for the module type
1583 }
1587 {
1588 // Look for the module type
1593 }
1595 // Try a primitive type
1601 }
1605 }
1608 {
1609 // Look for the module type
1614 }
1616 // Try a primitive type
1621 // Not a module or primitive that I know about yet, so try to
1622 // load a library module file (which parses some new Verilog
1623 // code) and try again.
1626 // Try again to find the module type
1631 }
1633 // Try again to find a primitive type
1637 }
1640 // Not a module or primitive that I know about or can find by
1641 // any means, so give up.
1645 }
1649 {
1655 }
1659 {
1662 }
1664 /*
1665 * This function elaborates delay expressions. This is a little
1666 * different from normal elaboration because the result may need to be
1667 * scaled.
1668 */
1670 {
1673 /* If the delay expression is a real constant or vector
1674 constant, then evaluate it, scale it to the local time
1675 units, and return an adjusted NetEConst. */
1687 }
1698 }
1701 /* The expression is not constant, so generate an expanded
1702 expression that includes the necessary scale shifts, and
1703 return that expression. */
1710 }
1714 }
1721 }
1725 }
1728 }
1731 {
1734 /* elaborate the lval. This detects any part selects and mux
1735 expressions that might exist. */
1739 /* If there is an internal delay expression, elaborate it. */
1747 /* Elaborate the r-value expression, then try to evaluate it. */
1749 /* Find out what the r-value width is going to be. We guess it
1750 will be the l-value width, but it may turn out to be
1751 something else based on self-determined widths inside. */
1756 /* Now elaborate to the expected width. Pass the lwidth to
1757 prune any constant result to fit with the lvalue at hand. */
1763 /* Rewrite delayed assignments as assignments that are
1764 delayed. For example, a = #<d> b; becomes:
1766 begin
1767 tmp = b;
1768 #<d> a = tmp;
1769 end
1771 If the delay is an event delay, then the transform is
1772 similar, with the event delay replacing the time delay. It
1773 is an event delay if the event_ member has a value.
1775 This rewriting of the expression allows me to not bother to
1776 actually and literally represent the delayed assign in the
1777 netlist. The compound statement is exactly equivalent. */
1789 //XXXX delete rv;
1791 }
1801 /* Generate an assignment of the l-value to the temporary... */
1807 /* Generate an assignment of the temporary to the r-value... */
1811 /* Generate the delay statement with the final
1812 assignment attached to it. If this is an event delay,
1813 elaborate the PEventStatement. Otherwise, create the
1814 right NetPDelay object. */
1820 "unable to elaborate event expression."
1824 }
1831 }
1833 /* And build up the complex statement. */
1839 }
1841 /* Based on the specific type of the l-value, do cleanup
1842 processing on the r-value. */
1845 // The r-value is a real. Casting will happen in the
1846 // code generator, so leave it.
1853 }
1859 }
1861 /*
1862 * Elaborate non-blocking assignments. The statement is of the general
1863 * form:
1864 *
1865 * <lval> <= #<delay> <rval> ;
1866 */
1868 {
1876 }
1878 /* Elaborate the l-value. */
1884 /* Elaborate and precalculate the r-value. */
1889 /* Handle the (common) case that the r-value is a vector. This
1890 includes just about everything but reals. In this case, we
1891 need to pad the r-value to match the width of the l-value.
1893 If in this case the l-val is a variable (i.e. real) then
1894 the width to pad to will be 0, so this code is harmless. */
1901 }
1907 /* All done with this node. Mark its line number and check it in. */
1912 }
1915 /*
1916 * This is the elaboration method for a begin-end block. Try to
1917 * elaborate the entire block, even if it fails somewhere. This way I
1918 * get all the error messages out of it. Then, if I detected a failure
1919 * then pass the failure up.
1920 */
1922 {
1938 }
1943 }
1950 // Handle the special case that the block contains only one
1951 // statement. There is no need to keep the block node. Also,
1952 // don't elide named blocks, because they might be referenced
1953 // elsewhere.
1958 }
1963 // If the statement fails to elaborate, then simply
1964 // ignore it. Presumably, the elaborate for the
1965 // statement already generated an error message and
1966 // marked the error count in the design so no need to
1967 // do any of that here.
1970 }
1972 // If the result turns out to be a noop, then skip it.
1977 }
1980 }
1983 }
1985 /*
1986 * Elaborate a case statement.
1987 */
1989 {
1997 }
1999 /* Count the items in the case statement. Note that there may
2000 be some cases that have multiple guards. Count each as a
2001 separate item. */
2008 else
2010 }
2015 /* Iterate over all the case items (guard/statement pairs)
2016 elaborating them. If the guard has no expression, then this
2017 is a "default" cause. Otherwise, the guard has one or more
2018 expressions, and each guard is a case. */
2026 /* If there are no expressions, then this is the
2027 default case. */
2037 /* If there are one or more expressions, then
2038 iterate over the guard expressions, elaborating
2039 a separate case for each. (Yes, the statement
2040 will be elaborated again for each.) */
2051 }
2052 }
2055 }
2058 {
2065 // Elaborate and try to evaluate the conditional expression.
2072 }
2074 // If the condition of the conditional statement is constant,
2075 // then look at the value and elaborate either the if statement
2076 // or the else statement. I don't need both. If there is no
2077 // else_ statement, the use an empty block as a noop.
2083 }
2097 }
2100 else
2102 }
2104 // If the condition expression is more than 1 bits, then
2105 // generate a comparison operator to get the result down to
2106 // one bit. Turn <e> into <e> != 0;
2112 }
2114 // Make sure the condition expression evaluates to a condition.
2117 // Well, I actually need to generate code to handle the
2118 // conditional, so elaborate.
2122 // Detect the special cases that the if or else statements are
2123 // empty blocks. If this is the case, remove the blocks as
2124 // null statements.
2129 }
2130 }
2136 }
2137 }
2142 }
2145 {
2148 else
2150 }
2152 /*
2153 * A call to a system task involves elaborating all the parameters,
2154 * then passing the list to the NetSTask object.
2155 *XXXX
2156 * There is a single special case in the call to a system
2157 * task. Normally, an expression cannot take an unindexed
2158 * memory. However, it is possible to take a system task parameter a
2159 * memory if the expression is trivial.
2160 */
2162 {
2167 /* Catch the special case that the system task has no
2168 parameters. The "()" string will be parsed as a single
2169 empty parameter, when we really mean no parameters at all. */
2179 /* Attempt to pre-evaluate the parameters. It may be
2180 possible to at least partially reduce the
2181 expression. */
2183 }
2188 }
2190 /*
2191 * A call to a user defined task is different from a call to a system
2192 * task because a user task in a netlist has no parameters: the
2193 * assignments are done by the calling thread. For example:
2194 *
2195 * task foo;
2196 * input a;
2197 * output b;
2198 * [...]
2199 * endtask;
2200 *
2201 * [...] foo(x, y);
2202 *
2203 * is really:
2204 *
2205 * task foo;
2206 * reg a;
2207 * reg b;
2208 * [...]
2209 * endtask;
2210 *
2211 * [...]
2212 * begin
2213 * a = x;
2214 * foo;
2215 * y = b;
2216 * end
2217 */
2219 {
2227 }
2235 }
2246 }
2255 }
2259 /* Handle tasks with no parameters specially. There is no need
2260 to make a sequential block to hold the generated code. */
2265 }
2270 /* Detect the case where the definition of the task is known
2271 empty. In this case, we need not bother with calls to the
2272 task, all the assignments, etc. Just return a no-op. */
2277 }
2279 /* Generate assignment statement statements for the input and
2280 INOUT ports of the task. These are managed by writing
2281 assignments with the task port the l-value and the passed
2282 expression the r-value. We know by definition that the port
2283 is a reg type, so this elaboration is pretty obvious. */
2300 }
2302 /* Generate the task call proper... */
2308 /* Generate assignment statements for the output and INOUT
2309 ports of the task. The l-value in this case is the
2310 expression passed as a parameter, and the r-value is the
2311 port to be copied out.
2313 We know by definition that the r-value of this copy-out is
2314 the port, which is a reg. The l-value, however, may be any
2315 expression that can be a target to a procedural
2316 assignment, including a memory word. */
2322 /* Skip input ports. */
2328 /* Elaborate an l-value version of the port expression
2329 for output and inout ports. If the expression does
2330 not exist then quietly skip it, but if the expression
2331 is not a valid l-value print an error message. Note
2332 that the elaborate_lval method already printed a
2333 detailed message. */
2341 }
2344 }
2352 /* Generate the assignment statement. */
2356 }
2359 }
2361 /*
2362 * Elaborate a procedural continuous assign. This really looks very
2363 * much like other procedural assignments, at this point, but there
2364 * is no delay to worry about. The code generator will take care of
2365 * the differences between continuous assign and normal assignments.
2366 */
2368 {
2393 }
2397 }
2400 {
2410 }
2412 /*
2413 * Elaborate the delay statement (of the form #<expr> <statement>) as a
2414 * NetPDelay object. If the expression is constant, evaluate it now
2415 * and make a constant delay. If not, then pass an elaborated
2416 * expression to the constructor of NetPDelay so that the code
2417 * generator knows to evaluate the expression at run time.
2418 */
2420 {
2428 }
2430 /* This call evaluates the delay expression to a NetEConst, if
2431 possible. This includes transforming NetECReal values to
2432 integers, and applying the proper scaling. */
2439 else
2447 else
2449 }
2451 }
2453 /*
2454 * The disable statement is not yet supported.
2455 */
2457 {
2468 }
2483 }
2488 }
2490 /*
2491 * An event statement is an event delay of some sort, attached to a
2492 * statement. Some Verilog examples are:
2493 *
2494 * @(posedge CLK) $display("clock rise");
2495 * @event_1 $display("event triggered.");
2496 * @(data or negedge clk) $display("data or clock fall.");
2497 *
2498 * The elaborated netlist uses the NetEvent, NetEvWait and NetEvProbe
2499 * classes. The NetEvWait class represents the part of the netlist
2500 * that is executed by behavioral code. The process starts waiting on
2501 * the NetEvent when it executes the NetEvWait step. Net NetEvProbe
2502 * and NetEvTrig are structural and behavioral equivalents that
2503 * trigger the event, and awakens any processes blocking in the
2504 * associated wait.
2505 *
2506 * The basic data structure is:
2507 *
2508 * NetEvWait ---/---> NetEvent <----\---- NetEvProbe
2509 * ... | | ...
2510 * NetEvWait ---+ +---- NetEvProbe
2511 * | ...
2512 * +---- NetEvTrig
2513 *
2514 * That is, many NetEvWait statements may wait on a single NetEvent
2515 * object, and Many NetEvProbe objects may trigger the NetEvent
2516 * object. The many NetEvWait objects pointing to the NetEvent object
2517 * reflects the possibility of different places in the code blocking
2518 * on the same named event, like so:
2519 *
2520 * event foo;
2521 * [...]
2522 * always begin @foo <statement1>; @foo <statement2> end
2523 *
2524 * This tends to not happen with signal edges. The multiple probes
2525 * pointing to the same event reflect the possibility of many
2526 * expressions in the same blocking statement, like so:
2527 *
2528 * wire reset, clk;
2529 * [...]
2530 * always @(reset or posedge clk) <stmt>;
2531 *
2532 * Conjunctions like this cause a NetEvent object be created to
2533 * represent the overall conjunction, and NetEvProbe objects for each
2534 * event expression.
2535 *
2536 * If the NetEvent object represents a named event from the source,
2537 * then there are NetEvTrig objects that represent the trigger
2538 * statements instead of the NetEvProbe objects representing signals.
2539 * For example:
2540 *
2541 * event foo;
2542 * always @foo <stmt>;
2543 * initial begin
2544 * [...]
2545 * -> foo;
2546 * [...]
2547 * -> foo;
2548 * [...]
2549 * end
2550 *
2551 * Each trigger statement in the source generates a separate NetEvTrig
2552 * object in the netlist. Those trigger objects are elaborated
2553 * elsewhere.
2554 *
2555 * Additional complications arise when named events show up in
2556 * conjunctions. An example of such a case is:
2557 *
2558 * event foo;
2559 * wire bar;
2560 * always @(foo or posedge bar) <stmt>;
2561 *
2562 * Since there is by definition a NetEvent object for the foo object,
2563 * this is handled by allowing the NetEvWait object to point to
2564 * multiple NetEvent objects. All the NetEvProbe based objects are
2565 * collected and pointed as the synthetic NetEvent object, and all the
2566 * named events are added into the list of NetEvent object that the
2567 * NetEvWait object can refer to.
2568 */
2572 {
2580 }
2582 /* Create a single NetEvent and NetEvWait. Then, create a
2583 NetEvProbe for each conjunctive event in the event
2584 list. The NetEvProbe objects all refer back to the NetEvent
2585 object. */
2594 /* If there are no expressions, this is a signal that it is an
2595 @* statement. Generate an expression to use. */
2599 /* For synthesis we want just the inputs, but for the rest we
2600 * want inputs and outputs that may cause a value to change. */
2605 }
2613 }
2620 }
2637 /* If the expression is an identifier that matches a
2638 named event, then handle this case all at once at
2639 skip the rest of the expression handling. */
2652 }
2653 }
2656 /* So now we have a normal event expression. Elaborate
2657 the sub-expression as a net and decide how to handle
2658 the edge. */
2670 }
2695 }
2702 }
2704 /* If there was at least one conjunction that was an
2705 expression (and not a named event) then add this
2706 event. Otherwise, we didn't use it so delete it. */
2710 /* NOTE: This event that I am adding to the wait may be
2711 a duplicate of another event somewhere else. However,
2712 I don't know that until all the modules are hooked
2713 up, so it is best to leave find_similar_event to
2714 after elaboration. */
2717 }
2720 }
2722 /*
2723 * This is the special case of the event statement, the wait
2724 * statement. This is elaborated into a slightly more complicated
2725 * statement that uses non-wait statements:
2726 *
2727 * wait (<expr>) <statement>
2728 *
2729 * becomes
2730 *
2731 * begin
2732 * while (1 !== <expr>)
2733 * @(<expr inputs>) <noop>;
2734 * <statement>;
2735 * end
2736 */
2739 {
2748 }
2752 /* Elaborate wait expression. Don't eval yet, we will do that
2753 shortly, after we apply a reduction or. */
2760 }
2762 // If the condition expression is more than 1 bits, then
2763 // generate a reduction operator to get the result down to
2764 // one bit. In other words, Turn <e> into |<e>;
2770 }
2776 }
2778 /* precalculate as much as possible of the wait expression. */
2781 /* Detect the unusual case that the wait expression is
2782 constant. Constant true is OK (it becomes transparent) but
2783 constant false is almost certainly not what is intended. */
2789 /* Constant true -- wait(1) <s1> reduces to <s1>. */
2794 }
2796 /* Otherwise, false. wait(0) blocks permanently. */
2803 /* Create an event wait and an otherwise unreferenced
2804 event variable to force a perpetual wait. */
2815 }
2817 /* Invert the sense of the test with an exclusive NOR. In
2818 other words, if this adjusted expression returns TRUE, then
2819 wait. */
2837 }
2844 }
2858 /* If there is no real substatement (i.e., "wait (foo) ;") then
2859 we are done. */
2863 /* Create a sequential block to combine the wait loop and the
2864 delayed statement. */
2871 }
2875 {
2885 }
2891 }
2893 /*
2894 * Forever statements are represented directly in the netlist. It is
2895 * theoretically possible to use a while structure with a constant
2896 * expression to represent the loop, but why complicate the code
2897 * generators so?
2898 */
2900 {
2906 }
2908 /*
2909 * Force is like a procedural assignment, most notably procedural
2910 * continuous assignment:
2911 *
2912 * force <lval> = <rval>
2913 *
2914 * The <lval> can be anything that a normal behavioral assignment can
2915 * take, plus net signals. This is a little bit more lax then the
2916 * other procedural assignments.
2917 */
2919 {
2944 }
2948 }
2950 /*
2951 * elaborate the for loop as the equivalent while loop. This eases the
2952 * task for the target code generator. The structure is:
2953 *
2954 * begin : top
2955 * name1_ = expr1_;
2956 * while (cond_) begin : body
2957 * statement_;
2958 * name2_ = expr2_;
2959 * end
2960 * end
2961 */
2963 {
2975 /* make the expression, and later the initial assignment to
2976 the condition variable. The statement in the for loop is
2977 very specifically an assignment. */
2984 }
2988 /* Calculate the width of the initialization as if this were
2989 any other assignment statement. */
2994 /* Make the r-value of the initial assignment, and size it
2995 properly. Then use it to build the assignment statement. */
3004 }
3006 /* Based on the specific type of the l-value, do cleanup
3007 processing on the r-value. */
3013 }
3023 /* Elaborate the statement that is contained in the for
3024 loop. If there is an error, this will return 0 and I should
3025 skip the append. No need to worry, the error has been
3026 reported so it's OK that the netlist is bogus. */
3032 /* Elaborate the increment assignment statement at the end of
3033 the for loop. This is also a very specific assignment
3034 statement. Put this into the "body" block. */
3041 }
3046 /* Make the rvalue of the increment expression, and size it
3047 for the lvalue. */
3055 /* Elaborate the condition expression. Try to evaluate it too,
3056 in case it is a constant. This is an interesting case
3057 worthy of a warning. */
3062 }
3067 }
3070 /* All done, build up the loop. */
3076 }
3078 /*
3079 * (See the PTask::elaborate methods for basic common stuff.)
3080 *
3081 * The return value of a function is represented as a reg variable
3082 * within the scope of the function that has the name of the
3083 * function. So for example with the function:
3084 *
3085 * function [7:0] incr;
3086 * input [7:0] in1;
3087 * incr = in1 + 1;
3088 * endfunction
3089 *
3090 * The scope of the function is <parent>.incr and there is a reg
3091 * variable <parent>.incr.incr. The elaborate_1 method is called with
3092 * the scope of the function, so the return reg is easily located.
3093 *
3094 * The function parameters are all inputs, except for the synthetic
3095 * output parameter that is the return value. The return value goes
3096 * into port 0, and the parameters are all the remaining ports.
3097 */
3100 {
3108 }
3118 }
3121 }
3124 {
3134 }
3137 {
3146 }
3151 // If the expression is a constant, handle certain special
3152 // iteration counts.
3165 }
3166 }
3170 }
3172 /*
3173 * A task definition is elaborated by elaborating the statement that
3174 * it contains, and connecting its ports to NetNet objects. The
3175 * netlist doesn't really need the array of parameters once elaboration
3176 * is complete, but this is the best place to store them.
3177 *
3178 * The first elaboration pass finds the reg objects that match the
3179 * port names, and creates the NetTaskDef object. The port names are
3180 * in the form task.port.
3181 *
3182 * task foo;
3183 * output blah;
3184 * begin <body> end
3185 * endtask
3186 *
3187 * So in the foo example, the PWire objects that represent the ports
3188 * of the task will include a foo.blah for the blah port. This port is
3189 * bound to a NetNet object by looking up the name. All of this is
3190 * handled by the PTask::elaborate_sig method and the results stashed
3191 * in the created NetTaskDef attached to the scope.
3192 *
3193 * Elaboration pass 2 for the task definition causes the statement of
3194 * the task to be elaborated and attached to the NetTaskDef object
3195 * created in pass 1.
3196 *
3197 * NOTE: I am not sure why I bothered to prepend the task name to the
3198 * port name when making the port list. It is not really useful, but
3199 * that is what I did in pform_make_task_ports, so there it is.
3200 */
3203 {
3204 // Elaborate any processes that are part of this scope that
3205 // aren't the definition itself. This can happen, for example,
3206 // with variable initialization statements in this scope.
3224 }
3225 }
3228 }
3231 {
3246 }
3253 }
3258 }
3260 /*
3261 * The while loop is fairly directly represented in the netlist.
3262 */
3264 {
3268 }
3271 {
3275 }
3285 }
3288 // Evaluate the attributes for this process, if there
3289 // are any. These attributes are to be attached to the
3290 // NetProcTop object.
3304 /* Detect the special case that this is a combinational
3305 always block. We want to attach an _ivl_schedule_push
3306 attribute to this process so that it starts up and
3307 gets into its wait statement before non-combinational
3308 code is executed. */
3331 }
3340 /* If this is an always block and we have no or zero delay then
3341 * a runtime infinite loop will happen. If we possible have some
3342 * delay then print a warning that an infinite loop is possible.
3343 */
3360 }
3361 }
3364 }
3367 {
3371 /* Do not elaborate specify delay paths if this feature is
3372 turned off. */
3384 /* Elaborate the delay values themselves. Remember to scale
3385 them for the timescale/precision of the scope. */
3403 }
3405 }
3420 }
3428 // FIXME: Look for constant expressions here?
3430 // Get a net form.
3433 }
3435 /* Create all the various paths from the path specifier. */
3447 }
3455 }
3463 }
3467 conditional);
3470 // The presence of the data_source_expression indicates
3471 // that this is an edge sensitive path. If so, then set
3472 // the edges. Note that edge==0 is BOTH edges.
3476 }
3502 }
3513 }
3522 }
3526 }
3529 }
3535 }
3537 }
3539 /*
3540 * When a module is instantiated, it creates the scope then uses this
3541 * method to elaborate the contents of the module.
3542 */
3544 {
3548 // Elaborate specparams
3582 }
3587 }
3588 }
3590 // Elaborate within the generate blocks.
3595 }
3597 // Elaborate functions.
3606 }
3608 // Elaborate the task definitions. This is done before the
3609 // behaviors so that task calls may reference these, and after
3610 // the signals so that the tasks can reference them.
3619 }
3621 // Get all the gates of the module and elaborate them by
3622 // connecting them to the signals. The gate may be simple or
3623 // complex.
3631 }
3633 // Elaborate the behaviors, making processes out of them. This
3634 // involves scanning the PProcess* list, creating a NetProcTop
3635 // for each process.
3638 // Elaborate the specify paths of the module.
3644 }
3647 }
3650 {
3653 // Handle the special case that this is a CASE scheme. In this
3654 // case the PGenerate itself does not have the generated
3655 // item. Look instead for the case ITEM that has a scope
3656 // generated for it.
3669 }
3670 }
3672 }
3679 // Check that this scope is one that is contained in the
3680 // container that the caller passed in.
3684 // If this was an unnamed generate block, replace its
3685 // temporary name with a name generated using the naming
3686 // scheme defined in the Verilog-2005 standard.
3693 }
3694 }
3700 }
3703 }
3706 {
3719 }
3722 }
3725 {
3728 // Elaborate the behaviors, making processes out of them. This
3729 // involves scanning the PProcess* list, creating a NetProcTop
3730 // for each process.
3735 }
3738 }
3743 };
3746 {
3751 // This is the output design. I fill it in as I scan the root
3752 // module and elaborate what I find.
3755 // Scan the root modules, and elaborate their scopes.
3760 // Look for the root module in the list.
3769 }
3771 // Get the module definition for this root instance.
3774 // Make the root scope.
3784 // Recursively elaborate from this root scope down. This
3785 // does a lot of the grunt work of creating sub-scopes, etc.
3789 }
3795 }
3797 // Errors already? Probably missing root modules. Just give up
3798 // now and return nothing.
3802 // This method recurses through the scopes, looking for
3803 // defparam assignments to apply to the parameters in the
3804 // various scopes. This needs to be done after all the scopes
3805 // and basic parameters are taken care of because the defparam
3806 // can assign to a parameter declared *after* it.
3810 // At this point, all parameter overrides are done. Scan the
3811 // scopes and evaluate the parameters all the way down to
3812 // constants.
3815 // With the parameters evaluated down to constants, we have
3816 // what we need to elaborate signals and memories. This pass
3817 // creates all the NetNet and NetMemory objects for declared
3818 // objects.
3826 }
3827 }
3829 // Now that the structure and parameters are taken care of,
3830 // run through the pform again and generate the full netlist.
3836 }
3842 }
3845 }