gpxe/src/drivers/net/3c90x.c

   1 /*
   2  * 3c90x.c -- This file implements the 3c90x driver for etherboot.  Written
   3  * by Greg Beeley, Greg.Beeley@LightSys.org.  Modified by Steve Smith,
   4  * Steve.Smith@Juno.Com. Alignment bug fix Neil Newell (nn@icenoir.net).
   5  *
   6  * This program Copyright (C) 1999 LightSys Technology Services, Inc.
   7  * Portions Copyright (C) 1999 Steve Smith
   8  *
   9  * This program may be re-distributed in source or binary form, modified,
  10  * sold, or copied for any purpose, provided that the above copyright message
  11  * and this text are included with all source copies or derivative works, and
  12  * provided that the above copyright message and this text are included in the
  13  * documentation of any binary-only distributions.  This program is distributed
  14  * WITHOUT ANY WARRANTY, without even the warranty of FITNESS FOR A PARTICULAR
  15  * PURPOSE or MERCHANTABILITY.  Please read the associated documentation
  16  * "3c90x.txt" before compiling and using this driver.
  17  *
  18  * --------
  19  *
  20  * Program written with the assistance of the 3com documentation for
  21  * the 3c905B-TX card, as well as with some assistance from the 3c59x
  22  * driver Donald Becker wrote for the Linux kernel, and with some assistance
  23  * from the remainder of the Etherboot distribution.
  24  *
  25  * REVISION HISTORY:
  26  *
  27  * v0.10        1-26-1998       GRB     Initial implementation.
  28  * v0.90        1-27-1998       GRB     System works.
  29  * v1.00pre1    2-11-1998       GRB     Got prom boot issue fixed.
  30  * v2.0         9-24-1999       SCS     Modified for 3c905 (from 3c905b code)
  31  *                                      Re-wrote poll and transmit for
  32  *                                      better error recovery and heavy
  33  *                                      network traffic operation
  34  * v2.01    5-26-2003 NN Fixed driver alignment issue which
  35  *                  caused system lockups if driver structures
  36  *                  not 8-byte aligned.
  37  * v2.02   11-28-2007 GSt Got polling working again by replacing
  38  *                      "for(i=0;i<40000;i++);" with "mdelay(1);"
  39  *
  40  */
  41
  42 #include "etherboot.h"
  43 #include "nic.h"
  44 #include <gpxe/pci.h>
  45 #include <gpxe/ethernet.h>
  46
  47 static struct nic_operations a3c90x_operations;
  48
  49 #define XCVR_MAGIC      (0x5A00)
  50 /** any single transmission fails after 16 collisions or other errors
  51  ** this is the number of times to retry the transmission -- this should
  52  ** be plenty
  53  **/
  54 #define XMIT_RETRIES    250
  55
  56 /*** Register definitions for the 3c905 ***/
  57 enum Registers
  58     {
  59     regPowerMgmtCtrl_w = 0x7c,        /** 905B Revision Only                 **/
  60     regUpMaxBurst_w = 0x7a,           /** 905B Revision Only                 **/
  61     regDnMaxBurst_w = 0x78,           /** 905B Revision Only                 **/
  62     regDebugControl_w = 0x74,         /** 905B Revision Only                 **/
  63     regDebugData_l = 0x70,            /** 905B Revision Only                 **/
  64     regRealTimeCnt_l = 0x40,          /** Universal                          **/
  65     regUpBurstThresh_b = 0x3e,        /** 905B Revision Only                 **/
  66     regUpPoll_b = 0x3d,               /** 905B Revision Only                 **/
  67     regUpPriorityThresh_b = 0x3c,     /** 905B Revision Only                 **/
  68     regUpListPtr_l = 0x38,            /** Universal                          **/
  69     regCountdown_w = 0x36,            /** Universal                          **/
  70     regFreeTimer_w = 0x34,            /** Universal                          **/
  71     regUpPktStatus_l = 0x30,          /** Universal with Exception, pg 130   **/
  72     regTxFreeThresh_b = 0x2f,         /** 90X Revision Only                  **/
  73     regDnPoll_b = 0x2d,               /** 905B Revision Only                 **/
  74     regDnPriorityThresh_b = 0x2c,     /** 905B Revision Only                 **/
  75     regDnBurstThresh_b = 0x2a,        /** 905B Revision Only                 **/
  76     regDnListPtr_l = 0x24,            /** Universal with Exception, pg 107   **/
  77     regDmaCtrl_l = 0x20,              /** Universal with Exception, pg 106   **/
  78                                       /**                                    **/
  79     regIntStatusAuto_w = 0x1e,        /** 905B Revision Only                 **/
  80     regTxStatus_b = 0x1b,             /** Universal with Exception, pg 113   **/
  81     regTimer_b = 0x1a,                /** Universal                          **/
  82     regTxPktId_b = 0x18,              /** 905B Revision Only                 **/
  83     regCommandIntStatus_w = 0x0e,     /** Universal (Command Variations)     **/
  84     };
  85
  86 /** following are windowed registers **/
  87 enum Registers7
  88     {
  89     regPowerMgmtEvent_7_w = 0x0c,     /** 905B Revision Only                 **/
  90     regVlanEtherType_7_w = 0x04,      /** 905B Revision Only                 **/
  91     regVlanMask_7_w = 0x00,           /** 905B Revision Only                 **/
  92     };
  93
  94 enum Registers6
  95     {
  96     regBytesXmittedOk_6_w = 0x0c,     /** Universal                          **/
  97     regBytesRcvdOk_6_w = 0x0a,        /** Universal                          **/
  98     regUpperFramesOk_6_b = 0x09,      /** Universal                          **/
  99     regFramesDeferred_6_b = 0x08,     /** Universal                          **/
 100     regFramesRecdOk_6_b = 0x07,       /** Universal with Exceptions, pg 142  **/
 101     regFramesXmittedOk_6_b = 0x06,    /** Universal                          **/
 102     regRxOverruns_6_b = 0x05,         /** Universal                          **/
 103     regLateCollisions_6_b = 0x04,     /** Universal                          **/
 104     regSingleCollisions_6_b = 0x03,   /** Universal                          **/
 105     regMultipleCollisions_6_b = 0x02, /** Universal                          **/
 106     regSqeErrors_6_b = 0x01,          /** Universal                          **/
 107     regCarrierLost_6_b = 0x00,        /** Universal                          **/
 108     };
 109
 110 enum Registers5
 111     {
 112     regIndicationEnable_5_w = 0x0c,   /** Universal                          **/
 113     regInterruptEnable_5_w = 0x0a,    /** Universal                          **/
 114     regTxReclaimThresh_5_b = 0x09,    /** 905B Revision Only                 **/
 115     regRxFilter_5_b = 0x08,           /** Universal                          **/
 116     regRxEarlyThresh_5_w = 0x06,      /** Universal                          **/
 117     regTxStartThresh_5_w = 0x00,      /** Universal                          **/
 118     };
 119
 120 enum Registers4
 121     {
 122     regUpperBytesOk_4_b = 0x0d,       /** Universal                          **/
 123     regBadSSD_4_b = 0x0c,             /** Universal                          **/
 124     regMediaStatus_4_w = 0x0a,        /** Universal with Exceptions, pg 201  **/
 125     regPhysicalMgmt_4_w = 0x08,       /** Universal                          **/
 126     regNetworkDiagnostic_4_w = 0x06,  /** Universal with Exceptions, pg 203  **/
 127     regFifoDiagnostic_4_w = 0x04,     /** Universal with Exceptions, pg 196  **/
 128     regVcoDiagnostic_4_w = 0x02,      /** Undocumented?                      **/
 129     };
 130
 131 enum Registers3
 132     {
 133     regTxFree_3_w = 0x0c,             /** Universal                          **/
 134     regRxFree_3_w = 0x0a,             /** Universal with Exceptions, pg 125  **/
 135     regResetMediaOptions_3_w = 0x08,  /** Media Options on B Revision,       **/
 136                                       /** Reset Options on Non-B Revision    **/
 137     regMacControl_3_w = 0x06,         /** Universal with Exceptions, pg 199  **/
 138     regMaxPktSize_3_w = 0x04,         /** 905B Revision Only                 **/
 139     regInternalConfig_3_l = 0x00,     /** Universal, different bit           **/
 140                                       /** definitions, pg 59                 **/
 141     };
 142
 143 enum Registers2
 144     {
 145     regResetOptions_2_w = 0x0c,       /** 905B Revision Only                 **/
 146     regStationMask_2_3w = 0x06,       /** Universal with Exceptions, pg 127  **/
 147     regStationAddress_2_3w = 0x00,    /** Universal with Exceptions, pg 127  **/
 148     };
 149
 150 enum Registers1
 151     {
 152     regRxStatus_1_w = 0x0a,           /** 90X Revision Only, Pg 126          **/
 153     };
 154
 155 enum Registers0
 156     {
 157     regEepromData_0_w = 0x0c,         /** Universal                          **/
 158     regEepromCommand_0_w = 0x0a,      /** Universal                          **/
 159     regBiosRomData_0_b = 0x08,        /** 905B Revision Only                 **/
 160     regBiosRomAddr_0_l = 0x04,        /** 905B Revision Only                 **/
 161     };
 162
 163
 164 /*** The names for the eight register windows ***/
 165 enum Windows
 166     {
 167     winPowerVlan7 = 0x07,
 168     winStatistics6 = 0x06,
 169     winTxRxControl5 = 0x05,
 170     winDiagnostics4 = 0x04,
 171     winTxRxOptions3 = 0x03,
 172     winAddressing2 = 0x02,
 173     winUnused1 = 0x01,
 174     winEepromBios0 = 0x00,
 175     };
 176
 177
 178 /*** Command definitions for the 3c90X ***/
 179 enum Commands
 180     {
 181     cmdGlobalReset = 0x00,             /** Universal with Exceptions, pg 151 **/
 182     cmdSelectRegisterWindow = 0x01,    /** Universal                         **/
 183     cmdEnableDcConverter = 0x02,       /**                                   **/
 184     cmdRxDisable = 0x03,               /**                                   **/
 185     cmdRxEnable = 0x04,                /** Universal                         **/
 186     cmdRxReset = 0x05,                 /** Universal                         **/
 187     cmdStallCtl = 0x06,                /** Universal                         **/
 188     cmdTxEnable = 0x09,                /** Universal                         **/
 189     cmdTxDisable = 0x0A,               /**                                   **/
 190     cmdTxReset = 0x0B,                 /** Universal                         **/
 191     cmdRequestInterrupt = 0x0C,        /**                                   **/
 192     cmdAcknowledgeInterrupt = 0x0D,    /** Universal                         **/
 193     cmdSetInterruptEnable = 0x0E,      /** Universal                         **/
 194     cmdSetIndicationEnable = 0x0F,     /** Universal                         **/
 195     cmdSetRxFilter = 0x10,             /** Universal                         **/
 196     cmdSetRxEarlyThresh = 0x11,        /**                                   **/
 197     cmdSetTxStartThresh = 0x13,        /**                                   **/
 198     cmdStatisticsEnable = 0x15,        /**                                   **/
 199     cmdStatisticsDisable = 0x16,       /**                                   **/
 200     cmdDisableDcConverter = 0x17,      /**                                   **/
 201     cmdSetTxReclaimThresh = 0x18,      /**                                   **/
 202     cmdSetHashFilterBit = 0x19,        /**                                   **/
 203     };
 204
 205
 206 /*** Values for int status register bitmask **/
 207 #define INT_INTERRUPTLATCH      (1<<0)
 208 #define INT_HOSTERROR           (1<<1)
 209 #define INT_TXCOMPLETE          (1<<2)
 210 #define INT_RXCOMPLETE          (1<<4)
 211 #define INT_RXEARLY             (1<<5)
 212 #define INT_INTREQUESTED        (1<<6)
 213 #define INT_UPDATESTATS         (1<<7)
 214 #define INT_LINKEVENT           (1<<8)
 215 #define INT_DNCOMPLETE          (1<<9)
 216 #define INT_UPCOMPLETE          (1<<10)
 217 #define INT_CMDINPROGRESS       (1<<12)
 218 #define INT_WINDOWNUMBER        (7<<13)
 219
 220
 221 /*** TX descriptor ***/
 222 typedef struct
 223     {
 224     unsigned int        DnNextPtr;
 225     unsigned int        FrameStartHeader;
 226     unsigned int        HdrAddr;
 227     unsigned int        HdrLength;
 228     unsigned int        DataAddr;
 229     unsigned int        DataLength;
 230     }
 231     TXD __attribute__ ((aligned(8))); /* 64-bit aligned for bus mastering */
 232
 233 /*** RX descriptor ***/
 234 typedef struct
 235     {
 236     unsigned int        UpNextPtr;
 237     unsigned int        UpPktStatus;
 238     unsigned int        DataAddr;
 239     unsigned int        DataLength;
 240     }
 241     RXD __attribute__ ((aligned(8))); /* 64-bit aligned for bus mastering */
 242
 243 /*** Global variables ***/
 244 static struct
 245     {
 246     unsigned int        is3c556;
 247     unsigned char       isBrev;
 248     unsigned char       CurrentWindow;
 249     unsigned int        IOAddr;
 250     unsigned char       HWAddr[ETH_ALEN];
 251     TXD                 TransmitDPD;
 252     RXD                 ReceiveUPD;
 253     }
 254     INF_3C90X;
 255
 256
 257 /*** a3c90x_internal_IssueCommand: sends a command to the 3c90x card
 258  ***/
 259 static int
 260 a3c90x_internal_IssueCommand(int ioaddr, int cmd, int param)
 261     {
 262     unsigned int val;
 263
 264         /** Build the cmd. **/
 265         val = cmd;
 266         val <<= 11;
 267         val |= param;
 268
 269         /** Send the cmd to the cmd register **/
 270         outw(val, ioaddr + regCommandIntStatus_w);
 271
 272         /** Wait for the cmd to complete, if necessary **/
 273         while (inw(ioaddr + regCommandIntStatus_w) & INT_CMDINPROGRESS);
 274
 275     return 0;
 276     }
 277
 278
 279 /*** a3c90x_internal_SetWindow: selects a register window set.
 280  ***/
 281 static int
 282 a3c90x_internal_SetWindow(int ioaddr, int window)
 283     {
 284
 285         /** Window already as set? **/
 286         if (INF_3C90X.CurrentWindow == window) return 0;
 287
 288         /** Issue the window command. **/
 289         a3c90x_internal_IssueCommand(ioaddr, cmdSelectRegisterWindow, window);
 290         INF_3C90X.CurrentWindow = window;
 291
 292     return 0;
 293     }
 294
 295
 296 /*** a3c90x_internal_ReadEeprom - read data from the serial eeprom.
 297  ***/
 298 static unsigned short
 299 a3c90x_internal_ReadEeprom(int ioaddr, int address)
 300     {
 301     unsigned short val;
 302
 303         /** Select correct window **/
 304         a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winEepromBios0);
 305
 306         /** Make sure the eeprom isn't busy **/
 307         while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
 308
 309         /** Read the value. **/
 310         if (INF_3C90X.is3c556)
 311          {
 312              outw(address + (0x230), ioaddr + regEepromCommand_0_w);
 313          }
 314         else
 315          {
 316              outw(address + ((0x02)<<6), ioaddr + regEepromCommand_0_w);
 317          }
 318
 319         while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
 320         val = inw(ioaddr + regEepromData_0_w);
 321
 322     return val;
 323     }
 324
 325
 326 #if 0
 327 /*** a3c90x_internal_WriteEepromWord - write a physical word of
 328  *** data to the onboard serial eeprom (not the BIOS prom, but the
 329  *** nvram in the card that stores, among other things, the MAC
 330  *** address).
 331  ***/
 332 static int
 333 a3c90x_internal_WriteEepromWord(int ioaddr, int address, unsigned short value)
 334     {
 335         /** Select register window **/
 336         a3c90x_internal_SetWindow(ioaddr, winEepromBios0);
 337
 338         /** Verify Eeprom not busy **/
 339         while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
 340
 341         /** Issue WriteEnable, and wait for completion. **/
 342         outw(0x30, ioaddr + regEepromCommand_0_w);
 343         while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
 344
 345         /** Issue EraseRegister, and wait for completion. **/
 346         outw(address + ((0x03)<<6), ioaddr + regEepromCommand_0_w);
 347         while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
 348
 349         /** Send the new data to the eeprom, and wait for completion. **/
 350         outw(value, ioaddr + regEepromData_0_w);
 351         outw(0x30, ioaddr + regEepromCommand_0_w);
 352         while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
 353
 354         /** Burn the new data into the eeprom, and wait for completion. **/
 355         outw(address + ((0x01)<<6), ioaddr + regEepromCommand_0_w);
 356         while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
 357
 358     return 0;
 359     }
 360 #endif
 361
 362 #if 0
 363 /*** a3c90x_internal_WriteEeprom - write data to the serial eeprom,
 364  *** and re-compute the eeprom checksum.
 365  ***/
 366 static int
 367 a3c90x_internal_WriteEeprom(int ioaddr, int address, unsigned short value)
 368     {
 369     int cksum = 0,v;
 370     int i;
 371     int maxAddress, cksumAddress;
 372
 373         if (INF_3C90X.isBrev)
 374             {
 375             maxAddress=0x1f;
 376             cksumAddress=0x20;
 377             }
 378         else
 379             {
 380             maxAddress=0x16;
 381             cksumAddress=0x17;
 382             }
 383
 384         /** Write the value. **/
 385         if (a3c90x_internal_WriteEepromWord(ioaddr, address, value) == -1)
 386             return -1;
 387
 388         /** Recompute the checksum. **/
 389         for(i=0;i<=maxAddress;i++)
 390             {
 391             v = a3c90x_internal_ReadEeprom(ioaddr, i);
 392             cksum ^= (v & 0xFF);
 393             cksum ^= ((v>>8) & 0xFF);
 394             }
 395         /** Write the checksum to the location in the eeprom **/
 396         if (a3c90x_internal_WriteEepromWord(ioaddr, cksumAddress, cksum) == -1)
 397             return -1;
 398
 399     return 0;
 400     }
 401 #endif
 402
 403 /*** a3c90x_reset: exported function that resets the card to its default
 404  *** state.  This is so the Linux driver can re-set the card up the way
 405  *** it wants to.  If CFG_3C90X_PRESERVE_XCVR is defined, then the reset will
 406  *** not alter the selected transceiver that we used to download the boot
 407  *** image.
 408  ***/
 409 static void a3c90x_reset(void)
 410     {
 411 #ifdef  CFG_3C90X_PRESERVE_XCVR
 412     int cfg;
 413     /** Read the current InternalConfig value. **/
 414     a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3);
 415     cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l);
 416 #endif
 417
 418     /** Send the reset command to the card **/
 419     printf("Issuing RESET:\n");
 420     a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdGlobalReset, 0);
 421
 422     /** wait for reset command to complete **/
 423     while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS);
 424
 425     /** global reset command resets station mask, non-B revision cards
 426      ** require explicit reset of values
 427      **/
 428     a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winAddressing2);
 429     outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0);
 430     outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2);
 431     outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4);
 432
 433 #ifdef  CFG_3C90X_PRESERVE_XCVR
 434     /** Re-set the original InternalConfig value from before reset **/
 435     a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3);
 436     outl(cfg, INF_3C90X.IOAddr + regInternalConfig_3_l);
 437
 438     /** enable DC converter for 10-Base-T **/
 439     if ((cfg&0x0300) == 0x0300)
 440         {
 441         a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdEnableDcConverter, 0);
 442         }
 443 #endif
 444
 445     /** Issue transmit reset, wait for command completion **/
 446     a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxReset, 0);
 447     while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
 448         ;
 449     if (! INF_3C90X.isBrev)
 450         outb(0x01, INF_3C90X.IOAddr + regTxFreeThresh_b);
 451     a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxEnable, 0);
 452
 453     /**
 454      ** reset of the receiver on B-revision cards re-negotiates the link
 455      ** takes several seconds (a computer eternity)
 456      **/
 457     if (INF_3C90X.isBrev)
 458         a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxReset, 0x04);
 459     else
 460         a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxReset, 0x00);
 461     while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS);
 462         ;
 463     a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxEnable, 0);
 464
 465     a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
 466                                  cmdSetInterruptEnable, 0);
 467     /** enable rxComplete and txComplete **/
 468     a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
 469                                  cmdSetIndicationEnable, 0x0014);
 470     /** acknowledge any pending status flags **/
 471     a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
 472                                  cmdAcknowledgeInterrupt, 0x661);
 473
 474     return;
 475     }
 476
 477
 478
 479 /*** a3c90x_transmit: exported function that transmits a packet.  Does not
 480  *** return any particular status.  Parameters are:
 481  *** d[6] - destination address, ethernet;
 482  *** t - protocol type (ARP, IP, etc);
 483  *** s - size of the non-header part of the packet that needs transmitted;
 484  *** p - the pointer to the packet data itself.
 485  ***/
 486 static void
 487 a3c90x_transmit(struct nic *nic __unused, const char *d, unsigned int t,
 488                 unsigned int s, const char *p)
 489     {
 490
 491     struct eth_hdr
 492         {
 493         unsigned char dst_addr[ETH_ALEN];
 494         unsigned char src_addr[ETH_ALEN];
 495         unsigned short type;
 496         } hdr;
 497
 498     unsigned char status;
 499     unsigned i, retries;
 500     tick_t ct;
 501
 502     for (retries=0; retries < XMIT_RETRIES ; retries++)
 503         {
 504         /** Stall the download engine **/
 505         a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdStallCtl, 2);
 506
 507         /** Make sure the card is not waiting on us **/
 508         inw(INF_3C90X.IOAddr + regCommandIntStatus_w);
 509         inw(INF_3C90X.IOAddr + regCommandIntStatus_w);
 510
 511         while (inw(INF_3C90X.IOAddr+regCommandIntStatus_w) &
 512                INT_CMDINPROGRESS)
 513             ;
 514
 515         /** Set the ethernet packet type **/
 516         hdr.type = htons(t);
 517
 518         /** Copy the destination address **/
 519         memcpy(hdr.dst_addr, d, ETH_ALEN);
 520
 521         /** Copy our MAC address **/
 522         memcpy(hdr.src_addr, INF_3C90X.HWAddr, ETH_ALEN);
 523
 524         /** Setup the DPD (download descriptor) **/
 525         INF_3C90X.TransmitDPD.DnNextPtr = 0;
 526         /** set notification for transmission completion (bit 15) **/
 527         INF_3C90X.TransmitDPD.FrameStartHeader = (s + sizeof(hdr)) | 0x8000;
 528         INF_3C90X.TransmitDPD.HdrAddr = virt_to_bus(&hdr);
 529         INF_3C90X.TransmitDPD.HdrLength = sizeof(hdr);
 530         INF_3C90X.TransmitDPD.DataAddr = virt_to_bus(p);
 531         INF_3C90X.TransmitDPD.DataLength = s + (1<<31);
 532
 533         /** Send the packet **/
 534         outl(virt_to_bus(&(INF_3C90X.TransmitDPD)),
 535              INF_3C90X.IOAddr + regDnListPtr_l);
 536
 537         /** End Stall and Wait for upload to complete. **/
 538         a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdStallCtl, 3);
 539         while(inl(INF_3C90X.IOAddr + regDnListPtr_l) != 0)
 540             ;
 541
 542         /** Wait for NIC Transmit to Complete **/
 543         ct = currticks();
 544
 545         while (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w)&0x0004) &&
 546                 ct + 10*USECS_IN_MSEC < currticks());
 547                 ;
 548
 549         if (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w)&0x0004))
 550             {
 551             printf("3C90X: Tx Timeout\n");
 552             continue;
 553             }
 554
 555         status = inb(INF_3C90X.IOAddr + regTxStatus_b);
 556
 557         /** acknowledge transmit interrupt by writing status **/
 558         outb(0x00, INF_3C90X.IOAddr + regTxStatus_b);
 559
 560         /** successful completion (sans "interrupt Requested" bit) **/
 561         if ((status & 0xbf) == 0x80)
 562             return;
 563
 564            printf("3C90X: Status (%hhX)\n", status);
 565         /** check error codes **/
 566         if (status & 0x02)
 567             {
 568             printf("3C90X: Tx Reclaim Error (%hhX)\n", status);
 569             a3c90x_reset();
 570             }
 571         else if (status & 0x04)
 572             {
 573             printf("3C90X: Tx Status Overflow (%hhX)\n", status);
 574             for (i=0; i<32; i++)
 575                 outb(0x00, INF_3C90X.IOAddr + regTxStatus_b);
 576             /** must re-enable after max collisions before re-issuing tx **/
 577             a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxEnable, 0);
 578             }
 579         else if (status & 0x08)
 580             {
 581             printf("3C90X: Tx Max Collisions (%hhX)\n", status);
 582             /** must re-enable after max collisions before re-issuing tx **/
 583             a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxEnable, 0);
 584             }
 585         else if (status & 0x10)
 586             {
 587             printf("3C90X: Tx Underrun (%hhX)\n", status);
 588             a3c90x_reset();
 589             }
 590         else if (status & 0x20)
 591             {
 592             printf("3C90X: Tx Jabber (%hhX)\n", status);
 593             a3c90x_reset();
 594             }
 595         else if ((status & 0x80) != 0x80)
 596             {
 597             printf("3C90X: Internal Error - Incomplete Transmission (%hhX)\n",
 598                    status);
 599             a3c90x_reset();
 600             }
 601         }
 602
 603     /** failed after RETRY attempts **/
 604     printf("Failed to send after %d retries\n", retries);
 605     return;
 606
 607     }
 608
 609
 610
 611 /*** a3c90x_poll: exported routine that waits for a certain length of time
 612  *** for a packet, and if it sees none, returns 0.  This routine should
 613  *** copy the packet to nic->packet if it gets a packet and set the size
 614  *** in nic->packetlen.  Return 1 if a packet was found.
 615  ***/
 616 static int
 617 a3c90x_poll(struct nic *nic, int retrieve)
 618     {
 619     int errcode;
 620
 621     if (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w)&0x0010))
 622         {
 623         return 0;
 624         }
 625
 626     if ( ! retrieve ) return 1;
 627
 628     /** we don't need to acknowledge rxComplete -- the upload engine
 629      ** does it for us.
 630      **/
 631
 632     /** Build the up-load descriptor **/
 633     INF_3C90X.ReceiveUPD.UpNextPtr = 0;
 634     INF_3C90X.ReceiveUPD.UpPktStatus = 0;
 635     INF_3C90X.ReceiveUPD.DataAddr = virt_to_bus(nic->packet);
 636     INF_3C90X.ReceiveUPD.DataLength = 1536 + (1<<31);
 637
 638     /** Submit the upload descriptor to the NIC **/
 639     outl(virt_to_bus(&(INF_3C90X.ReceiveUPD)),
 640          INF_3C90X.IOAddr + regUpListPtr_l);
 641
 642     /** Wait for upload completion (upComplete(15) or upError (14)) **/
 643     mdelay(1);
 644     while((INF_3C90X.ReceiveUPD.UpPktStatus & ((1<<14) | (1<<15))) == 0)
 645         mdelay(1);
 646
 647     /** Check for Error (else we have good packet) **/
 648     if (INF_3C90X.ReceiveUPD.UpPktStatus & (1<<14))
 649         {
 650         errcode = INF_3C90X.ReceiveUPD.UpPktStatus;
 651         if (errcode & (1<<16))
 652             printf("3C90X: Rx Overrun (%hX)\n",errcode>>16);
 653         else if (errcode & (1<<17))
 654             printf("3C90X: Runt Frame (%hX)\n",errcode>>16);
 655         else if (errcode & (1<<18))
 656             printf("3C90X: Alignment Error (%hX)\n",errcode>>16);
 657         else if (errcode & (1<<19))
 658             printf("3C90X: CRC Error (%hX)\n",errcode>>16);
 659         else if (errcode & (1<<20))
 660             printf("3C90X: Oversized Frame (%hX)\n",errcode>>16);
 661         else
 662             printf("3C90X: Packet error (%hX)\n",errcode>>16);
 663         return 0;
 664         }
 665
 666     /** Ok, got packet.  Set length in nic->packetlen. **/
 667     nic->packetlen = (INF_3C90X.ReceiveUPD.UpPktStatus & 0x1FFF);
 668
 669     return 1;
 670     }
 671
 672
 673
 674 /*** a3c90x_disable: exported routine to disable the card.  What's this for?
 675  *** the eepro100.c driver didn't have one, so I just left this one empty too.
 676  *** Ideas anyone?
 677  *** Must turn off receiver at least so stray packets will not corrupt memory
 678  *** [Ken]
 679  ***/
 680 static void
 681 a3c90x_disable ( struct nic *nic __unused ) {
 682         a3c90x_reset();
 683         /* Disable the receiver and transmitter. */
 684         outw(cmdRxDisable, INF_3C90X.IOAddr + regCommandIntStatus_w);
 685         outw(cmdTxDisable, INF_3C90X.IOAddr + regCommandIntStatus_w);
 686 }
 687
 688 static void a3c90x_irq(struct nic *nic __unused, irq_action_t action __unused)
 689 {
 690   switch ( action ) {
 691   case DISABLE :
 692     break;
 693   case ENABLE :
 694     break;
 695   case FORCE :
 696     break;
 697   }
 698 }
 699
 700 /*** a3c90x_probe: exported routine to probe for the 3c905 card and perform
 701  *** initialization.  If this routine is called, the pci functions did find the
 702  *** card.  We just have to init it here.
 703  ***/
 704 static int a3c90x_probe ( struct nic *nic, struct pci_device *pci ) {
 705
 706     int i, c;
 707     unsigned short eeprom[0x21];
 708     unsigned int cfg;
 709     unsigned int mopt;
 710     unsigned int mstat;
 711     unsigned short linktype;
 712 #define HWADDR_OFFSET   10
 713
 714     if (pci->ioaddr == 0)
 715           return 0;
 716
 717     adjust_pci_device(pci);
 718
 719     nic->ioaddr = pci->ioaddr;
 720     nic->irqno = 0;
 721
 722     INF_3C90X.is3c556 = (pci->device == 0x6055);
 723     INF_3C90X.IOAddr = pci->ioaddr & ~3;
 724     INF_3C90X.CurrentWindow = 255;
 725     switch (a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, 0x03))
 726         {
 727         case 0x9000: /** 10 Base TPO             **/
 728         case 0x9001: /** 10/100 T4               **/
 729         case 0x9050: /** 10/100 TPO              **/
 730         case 0x9051: /** 10 Base Combo           **/
 731                 INF_3C90X.isBrev = 0;
 732                 break;
 733
 734         case 0x9004: /** 10 Base TPO             **/
 735         case 0x9005: /** 10 Base Combo           **/
 736         case 0x9006: /** 10 Base TPO and Base2   **/
 737         case 0x900A: /** 10 Base FL              **/
 738         case 0x9055: /** 10/100 TPO              **/
 739         case 0x9056: /** 10/100 T4               **/
 740         case 0x905A: /** 10 Base FX              **/
 741         default:
 742                 INF_3C90X.isBrev = 1;
 743                 break;
 744         }
 745
 746     /** Load the EEPROM contents **/
 747     if (INF_3C90X.isBrev)
 748         {
 749         for(i=0;i<=0x20;i++)
 750             {
 751             eeprom[i] = a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, i);
 752             }
 753
 754 #ifdef  CFG_3C90X_BOOTROM_FIX
 755         /** Set xcvrSelect in InternalConfig in eeprom. **/
 756         /* only necessary for 3c905b revision cards with boot PROM bug!!! */
 757         a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x13, 0x0160);
 758 #endif
 759
 760 #ifdef  CFG_3C90X_XCVR
 761         if (CFG_3C90X_XCVR == 255)
 762             {
 763             /** Clear the LanWorks register **/
 764             a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x16, 0);
 765             }
 766         else
 767             {
 768             /** Set the selected permanent-xcvrSelect in the
 769              ** LanWorks register
 770              **/
 771             a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x16,
 772                             XCVR_MAGIC + ((CFG_3C90X_XCVR) & 0x000F));
 773             }
 774 #endif
 775         }
 776     else
 777         {
 778         for(i=0;i<=0x17;i++)
 779             {
 780             eeprom[i] = a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, i);
 781             }
 782         }
 783
 784     /** Print identification message **/
 785     printf("\n\n3C90X Driver 2.02 "
 786            "Copyright 1999 LightSys Technology Services, Inc.\n"
 787            "Portions Copyright 1999 Steve Smith\n");
 788     printf("Provided with ABSOLUTELY NO WARRANTY.\n");
 789 #ifdef  CFG_3C90X_BOOTROM_FIX
 790     if (INF_3C90X.isBrev)
 791         {
 792         printf("NOTE: 3c905b bootrom fix enabled; has side "
 793            "effects.  See 3c90x.txt for info.\n");
 794         }
 795 #endif
 796     printf("-------------------------------------------------------"
 797            "------------------------\n");
 798
 799     /** Retrieve the Hardware address and print it on the screen. **/
 800     INF_3C90X.HWAddr[0] = eeprom[HWADDR_OFFSET + 0]>>8;
 801     INF_3C90X.HWAddr[1] = eeprom[HWADDR_OFFSET + 0]&0xFF;
 802     INF_3C90X.HWAddr[2] = eeprom[HWADDR_OFFSET + 1]>>8;
 803     INF_3C90X.HWAddr[3] = eeprom[HWADDR_OFFSET + 1]&0xFF;
 804     INF_3C90X.HWAddr[4] = eeprom[HWADDR_OFFSET + 2]>>8;
 805     INF_3C90X.HWAddr[5] = eeprom[HWADDR_OFFSET + 2]&0xFF;
 806
 807     DBG ( "MAC Address = %s\n", eth_ntoa ( INF_3C90X.HWAddr ) );
 808
 809     /** 3C556: Invert MII power **/
 810     if (INF_3C90X.is3c556) {
 811         unsigned int tmp;
 812         a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winAddressing2);
 813         tmp = inw(INF_3C90X.IOAddr + regResetOptions_2_w);
 814         tmp |= 0x4000;
 815         outw(tmp, INF_3C90X.IOAddr + regResetOptions_2_w);
 816     }
 817
 818     /* Test if the link is good, if not continue */
 819     a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winDiagnostics4);
 820     mstat = inw(INF_3C90X.IOAddr + regMediaStatus_4_w);
 821     if((mstat & (1<<11)) == 0) {
 822         printf("Valid link not established\n");
 823         return 0;
 824     }
 825
 826     /** Program the MAC address into the station address registers **/
 827     a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winAddressing2);
 828     outw(htons(eeprom[HWADDR_OFFSET + 0]), INF_3C90X.IOAddr + regStationAddress_2_3w);
 829     outw(htons(eeprom[HWADDR_OFFSET + 1]), INF_3C90X.IOAddr + regStationAddress_2_3w+2);
 830     outw(htons(eeprom[HWADDR_OFFSET + 2]), INF_3C90X.IOAddr + regStationAddress_2_3w+4);
 831     outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0);
 832     outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2);
 833     outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4);
 834
 835     /** Fill in our entry in the etherboot arp table **/
 836     for(i=0;i<ETH_ALEN;i++)
 837         nic->node_addr[i] = (eeprom[HWADDR_OFFSET + i/2] >> (8*((i&1)^1))) & 0xff;
 838
 839     /** Read the media options register, print a message and set default
 840      ** xcvr.
 841      **
 842      ** Uses Media Option command on B revision, Reset Option on non-B
 843      ** revision cards -- same register address
 844      **/
 845     a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3);
 846     mopt = inw(INF_3C90X.IOAddr + regResetMediaOptions_3_w);
 847
 848     /** mask out VCO bit that is defined as 10baseFL bit on B-rev cards **/
 849     if (! INF_3C90X.isBrev)
 850         {
 851         mopt &= 0x7F;
 852         }
 853
 854     printf("Connectors present: ");
 855     c = 0;
 856     linktype = 0x0008;
 857     if (mopt & 0x01)
 858         {
 859         printf("%s100Base-T4",(c++)?", ":"");
 860         linktype = 0x0006;
 861         }
 862     if (mopt & 0x04)
 863         {
 864         printf("%s100Base-FX",(c++)?", ":"");
 865         linktype = 0x0005;
 866         }
 867     if (mopt & 0x10)
 868         {
 869         printf("%s10Base-2",(c++)?", ":"");
 870         linktype = 0x0003;
 871         }
 872     if (mopt & 0x20)
 873         {
 874         printf("%sAUI",(c++)?", ":"");
 875         linktype = 0x0001;
 876         }
 877     if (mopt & 0x40)
 878         {
 879         printf("%sMII",(c++)?", ":"");
 880         linktype = 0x0006;
 881         }
 882     if ((mopt & 0xA) == 0xA)
 883         {
 884         printf("%s10Base-T / 100Base-TX",(c++)?", ":"");
 885         linktype = 0x0008;
 886         }
 887     else if ((mopt & 0xA) == 0x2)
 888         {
 889         printf("%s100Base-TX",(c++)?", ":"");
 890         linktype = 0x0008;
 891         }
 892     else if ((mopt & 0xA) == 0x8)
 893         {
 894         printf("%s10Base-T",(c++)?", ":"");
 895         linktype = 0x0008;
 896         }
 897     printf(".\n");
 898
 899     /** Determine transceiver type to use, depending on value stored in
 900      ** eeprom 0x16
 901      **/
 902     if (INF_3C90X.isBrev)
 903         {
 904         if ((eeprom[0x16] & 0xFF00) == XCVR_MAGIC)
 905             {
 906             /** User-defined **/
 907             linktype = eeprom[0x16] & 0x000F;
 908             }
 909         }
 910     else
 911         {
 912 #ifdef  CFG_3C90X_XCVR
 913             if (CFG_3C90X_XCVR != 255)
 914                 linktype = CFG_3C90X_XCVR;
 915 #endif  /* CFG_3C90X_XCVR */
 916
 917             /** I don't know what MII MAC only mode is!!! **/
 918             if (linktype == 0x0009)
 919                 {
 920                 if (INF_3C90X.isBrev)
 921                         printf("WARNING: MII External MAC Mode only supported on B-revision "
 922                                "cards!!!!\nFalling Back to MII Mode\n");
 923                 linktype = 0x0006;
 924                 }
 925         }
 926
 927     /** enable DC converter for 10-Base-T **/
 928     if (linktype == 0x0003)
 929         {
 930         a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdEnableDcConverter, 0);
 931         }
 932
 933     /** Set the link to the type we just determined. **/
 934     a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3);
 935     cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l);
 936     cfg &= ~(0xF<<20);
 937     cfg |= (linktype<<20);
 938     outl(cfg, INF_3C90X.IOAddr + regInternalConfig_3_l);
 939
 940     /** Now that we set the xcvr type, reset the Tx and Rx, re-enable. **/
 941     a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxReset, 0x00);
 942     while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
 943         ;
 944
 945     if (!INF_3C90X.isBrev)
 946         outb(0x01, INF_3C90X.IOAddr + regTxFreeThresh_b);
 947
 948     a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxEnable, 0);
 949
 950     /**
 951      ** reset of the receiver on B-revision cards re-negotiates the link
 952      ** takes several seconds (a computer eternity)
 953      **/
 954     if (INF_3C90X.isBrev)
 955         a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxReset, 0x04);
 956     else
 957         a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxReset, 0x00);
 958     while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
 959         ;
 960
 961     /** Set the RX filter = receive only individual pkts & multicast & bcast. **/
 962     a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdSetRxFilter, 0x01 + 0x02 + 0x04);
 963     a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxEnable, 0);
 964
 965
 966     /**
 967      ** set Indication and Interrupt flags , acknowledge any IRQ's
 968      **/
 969     a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdSetInterruptEnable, 0);
 970     a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
 971                                  cmdSetIndicationEnable, 0x0014);
 972     a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
 973                                  cmdAcknowledgeInterrupt, 0x661);
 974
 975     /** Set our exported functions **/
 976     nic->nic_op = &a3c90x_operations;
 977     return 1;
 978 }
 979
 980 static struct nic_operations a3c90x_operations = {
 981         .connect        = dummy_connect,
 982         .poll           = a3c90x_poll,
 983         .transmit       = a3c90x_transmit,
 984         .irq            = a3c90x_irq,
 985
 986 };
 987
 988 static struct pci_device_id a3c90x_nics[] = {
 989 /* Original 90x revisions: */
 990 PCI_ROM(0x10b7, 0x6055, "3c556",         "3C556"),              /* Huricane */
 991 PCI_ROM(0x10b7, 0x9000, "3c905-tpo",     "3Com900-TPO"),        /* 10 Base TPO */
 992 PCI_ROM(0x10b7, 0x9001, "3c905-t4",      "3Com900-Combo"),      /* 10/100 T4 */
 993 PCI_ROM(0x10b7, 0x9050, "3c905-tpo100",  "3Com905-TX"),         /* 100 Base TX / 10/100 TPO */
 994 PCI_ROM(0x10b7, 0x9051, "3c905-combo",   "3Com905-T4"),         /* 100 Base T4 / 10 Base Combo */
 995 /* Newer 90xB revisions: */
 996 PCI_ROM(0x10b7, 0x9004, "3c905b-tpo",    "3Com900B-TPO"),       /* 10 Base TPO */
 997 PCI_ROM(0x10b7, 0x9005, "3c905b-combo",  "3Com900B-Combo"),     /* 10 Base Combo */
 998 PCI_ROM(0x10b7, 0x9006, "3c905b-tpb2",   "3Com900B-2/T"),       /* 10 Base TP and Base2 */
 999 PCI_ROM(0x10b7, 0x900a, "3c905b-fl",     "3Com900B-FL"),        /* 10 Base FL */
1000 PCI_ROM(0x10b7, 0x9055, "3c905b-tpo100", "3Com905B-TX"),        /* 10/100 TPO */
1001 PCI_ROM(0x10b7, 0x9056, "3c905b-t4",     "3Com905B-T4"),        /* 10/100 T4 */
1002 PCI_ROM(0x10b7, 0x9058, "3c905b-9058",   "3Com905B-9058"),      /* Cyclone 10/100/BNC */
1003 PCI_ROM(0x10b7, 0x905a, "3c905b-fx",     "3Com905B-FL"),        /* 100 Base FX / 10 Base FX */
1004 /* Newer 90xC revision: */
1005 PCI_ROM(0x10b7, 0x9200, "3c905c-tpo",    "3Com905C-TXM"),       /* 10/100 TPO (3C905C-TXM) */
1006 PCI_ROM(0x10b7, 0x9202, "3c920b-emb-ati", "3c920B-EMB-WNM (ATI Radeon 9100 IGP)"),      /* 3c920B-EMB-WNM (ATI Radeon 9100 IGP) */
1007 PCI_ROM(0x10b7, 0x9210, "3c920b-emb-wnm","3Com20B-EMB WNM"),
1008 PCI_ROM(0x10b7, 0x9800, "3c980",         "3Com980-Cyclone"),    /* Cyclone */
1009 PCI_ROM(0x10b7, 0x9805, "3c9805",        "3Com9805"),           /* Dual Port Server Cyclone */
1010 PCI_ROM(0x10b7, 0x7646, "3csoho100-tx",  "3CSOHO100-TX"),       /* Hurricane */
1011 PCI_ROM(0x10b7, 0x4500, "3c450",         "3Com450 HomePNA Tornado"),
1012 PCI_ROM(0x10b7, 0x1201, "3c982a",        "3Com982A"),
1013 PCI_ROM(0x10b7, 0x1202, "3c982b",        "3Com982B"),
1014 };
1015
1016 PCI_DRIVER ( a3c90x_driver, a3c90x_nics, PCI_NO_CLASS );
1017
1018 DRIVER ( "3C90X", nic_driver, pci_driver, a3c90x_driver,
1019          a3c90x_probe, a3c90x_disable );
1020
1021 /*
1022  * Local variables:
1023  *  c-basic-offset: 8
1024  *  c-indent-level: 8
1025  *  tab-width: 8
1026  * End:
1027  */