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Adding debian version 3.70~pre8+dfsg-1.
[syslinux-debian/hramrach.git] / gpxe / src / drivers / net / amd8111e.c
blob1c41add12a86365db6a8ae595cec0b3222313414
1 /* Advanced Micro Devices Inc. AMD8111E Linux Network Driver
2 * Copyright (C) 2004 Advanced Micro Devices
3 * Copyright (C) 2005 Liu Tao <liutao1980@gmail.com> [etherboot port]
4 *
5 * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ]
6 * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c]
7 * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ]
8 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
9 * Copyright 1993 United States Government as represented by the
10 * Director, National Security Agency.[ pcnet32.c ]
11 * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ]
12 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
13 *
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
28 * USA
29 */
30
31 #include "etherboot.h"
32 #include "nic.h"
33 #include "mii.h"
34 #include <gpxe/pci.h>
35 #include <gpxe/ethernet.h>
36 #include "string.h"
37 #include "stdint.h"
38 #include "amd8111e.h"
39
40
41 /* driver definitions */
42 #define NUM_TX_SLOTS 2
43 #define NUM_RX_SLOTS 4
44 #define TX_SLOTS_MASK 1
45 #define RX_SLOTS_MASK 3
46
47 #define TX_BUF_LEN 1536
48 #define RX_BUF_LEN 1536
49
50 #define TX_PKT_LEN_MAX (ETH_FRAME_LEN - ETH_HLEN)
51 #define RX_PKT_LEN_MIN 60
52 #define RX_PKT_LEN_MAX ETH_FRAME_LEN
53
54 #define TX_TIMEOUT 3000
55 #define TX_PROCESS_TIME 10
56 #define TX_RETRY (TX_TIMEOUT / TX_PROCESS_TIME)
57
58 #define PHY_RW_RETRY 10
59
60
61 struct amd8111e_tx_desc {
62 u16 buf_len;
63 u16 tx_flags;
64 u16 tag_ctrl_info;
65 u16 tag_ctrl_cmd;
66 u32 buf_phy_addr;
67 u32 reserved;
68 };
69
70 struct amd8111e_rx_desc {
71 u32 reserved;
72 u16 msg_len;
73 u16 tag_ctrl_info;
74 u16 buf_len;
75 u16 rx_flags;
76 u32 buf_phy_addr;
77 };
78
79 struct eth_frame {
80 u8 dst_addr[ETH_ALEN];
81 u8 src_addr[ETH_ALEN];
82 u16 type;
83 u8 data[ETH_FRAME_LEN - ETH_HLEN];
84 } __attribute__((packed));
85
86 struct amd8111e_priv {
87 struct amd8111e_tx_desc tx_ring[NUM_TX_SLOTS];
88 struct amd8111e_rx_desc rx_ring[NUM_RX_SLOTS];
89 unsigned char tx_buf[NUM_TX_SLOTS][TX_BUF_LEN];
90 unsigned char rx_buf[NUM_RX_SLOTS][RX_BUF_LEN];
91 unsigned long tx_idx, rx_idx;
92 int tx_consistent;
93
94 char opened;
95 char link;
96 char speed;
97 char duplex;
98 int ext_phy_addr;
99 u32 ext_phy_id;
100
101 struct pci_device *pdev;
102 struct nic *nic;
103 void *mmio;
104 };
105
106 static struct amd8111e_priv amd8111e;
107
108
109 /********************************************************
110 * locale functions *
111 ********************************************************/
112 static void amd8111e_init_hw_default(struct amd8111e_priv *lp);
113 static int amd8111e_start(struct amd8111e_priv *lp);
114 static int amd8111e_read_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 *val);
115 #if 0
116 static int amd8111e_write_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 val);
117 #endif
118 static void amd8111e_probe_ext_phy(struct amd8111e_priv *lp);
119 static void amd8111e_disable_interrupt(struct amd8111e_priv *lp);
120 static void amd8111e_enable_interrupt(struct amd8111e_priv *lp);
121 static void amd8111e_force_interrupt(struct amd8111e_priv *lp);
122 static int amd8111e_get_mac_address(struct amd8111e_priv *lp);
123 static int amd8111e_init_rx_ring(struct amd8111e_priv *lp);
124 static int amd8111e_init_tx_ring(struct amd8111e_priv *lp);
125 static int amd8111e_wait_tx_ring(struct amd8111e_priv *lp, unsigned int index);
126 static void amd8111e_wait_link(struct amd8111e_priv *lp);
127 static void amd8111e_poll_link(struct amd8111e_priv *lp);
128 static void amd8111e_restart(struct amd8111e_priv *lp);
129
130
131 /*
132 * This function clears necessary the device registers.
133 */
134 static void amd8111e_init_hw_default(struct amd8111e_priv *lp)
135 {
136 unsigned int reg_val;
137 void *mmio = lp->mmio;
138
139 /* stop the chip */
140 writel(RUN, mmio + CMD0);
141
142 /* Clear RCV_RING_BASE_ADDR */
143 writel(0, mmio + RCV_RING_BASE_ADDR0);
144
145 /* Clear XMT_RING_BASE_ADDR */
146 writel(0, mmio + XMT_RING_BASE_ADDR0);
147 writel(0, mmio + XMT_RING_BASE_ADDR1);
148 writel(0, mmio + XMT_RING_BASE_ADDR2);
149 writel(0, mmio + XMT_RING_BASE_ADDR3);
150
151 /* Clear CMD0 */
152 writel(CMD0_CLEAR, mmio + CMD0);
153
154 /* Clear CMD2 */
155 writel(CMD2_CLEAR, mmio + CMD2);
156
157 /* Clear CMD7 */
158 writel(CMD7_CLEAR, mmio + CMD7);
159
160 /* Clear DLY_INT_A and DLY_INT_B */
161 writel(0x0, mmio + DLY_INT_A);
162 writel(0x0, mmio + DLY_INT_B);
163
164 /* Clear FLOW_CONTROL */
165 writel(0x0, mmio + FLOW_CONTROL);
166
167 /* Clear INT0 write 1 to clear register */
168 reg_val = readl(mmio + INT0);
169 writel(reg_val, mmio + INT0);
170
171 /* Clear STVAL */
172 writel(0x0, mmio + STVAL);
173
174 /* Clear INTEN0 */
175 writel(INTEN0_CLEAR, mmio + INTEN0);
176
177 /* Clear LADRF */
178 writel(0x0, mmio + LADRF);
179
180 /* Set SRAM_SIZE & SRAM_BOUNDARY registers */
181 writel(0x80010, mmio + SRAM_SIZE);
182
183 /* Clear RCV_RING0_LEN */
184 writel(0x0, mmio + RCV_RING_LEN0);
185
186 /* Clear XMT_RING0/1/2/3_LEN */
187 writel(0x0, mmio + XMT_RING_LEN0);
188 writel(0x0, mmio + XMT_RING_LEN1);
189 writel(0x0, mmio + XMT_RING_LEN2);
190 writel(0x0, mmio + XMT_RING_LEN3);
191
192 /* Clear XMT_RING_LIMIT */
193 writel(0x0, mmio + XMT_RING_LIMIT);
194
195 /* Clear MIB */
196 writew(MIB_CLEAR, mmio + MIB_ADDR);
197
198 /* Clear LARF */
199 writel( 0, mmio + LADRF);
200 writel( 0, mmio + LADRF + 4);
201
202 /* SRAM_SIZE register */
203 reg_val = readl(mmio + SRAM_SIZE);
204
205 /* Set default value to CTRL1 Register */
206 writel(CTRL1_DEFAULT, mmio + CTRL1);
207
208 /* To avoid PCI posting bug */
209 readl(mmio + CMD2);
210 }
211
212 /*
213 * This function initializes the device registers and starts the device.
214 */
215 static int amd8111e_start(struct amd8111e_priv *lp)
216 {
217 struct nic *nic = lp->nic;
218 void *mmio = lp->mmio;
219 int i, reg_val;
220
221 /* stop the chip */
222 writel(RUN, mmio + CMD0);
223
224 /* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */
225 writew(0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
226
227 /* enable the port manager and set auto negotiation always */
228 writel(VAL1 | EN_PMGR, mmio + CMD3 );
229 writel(XPHYANE | XPHYRST, mmio + CTRL2);
230
231 /* set control registers */
232 reg_val = readl(mmio + CTRL1);
233 reg_val &= ~XMTSP_MASK;
234 writel(reg_val | XMTSP_128 | CACHE_ALIGN, mmio + CTRL1);
235
236 /* initialize tx and rx ring base addresses */
237 amd8111e_init_tx_ring(lp);
238 amd8111e_init_rx_ring(lp);
239 writel(virt_to_bus(lp->tx_ring), mmio + XMT_RING_BASE_ADDR0);
240 writel(virt_to_bus(lp->rx_ring), mmio + RCV_RING_BASE_ADDR0);
241 writew(NUM_TX_SLOTS, mmio + XMT_RING_LEN0);
242 writew(NUM_RX_SLOTS, mmio + RCV_RING_LEN0);
243
244 /* set default IPG to 96 */
245 writew(DEFAULT_IPG, mmio + IPG);
246 writew(DEFAULT_IPG - IFS1_DELTA, mmio + IFS1);
247
248 /* AutoPAD transmit, Retransmit on Underflow */
249 writel(VAL0 | APAD_XMT | REX_RTRY | REX_UFLO, mmio + CMD2);
250
251 /* JUMBO disabled */
252 writel(JUMBO, mmio + CMD3);
253
254 /* Setting the MAC address to the device */
255 for(i = 0; i < ETH_ALEN; i++)
256 writeb(nic->node_addr[i], mmio + PADR + i);
257
258 /* set RUN bit to start the chip, interrupt not enabled */
259 writel(VAL2 | RDMD0 | VAL0 | RUN, mmio + CMD0);
260
261 /* To avoid PCI posting bug */
262 readl(mmio + CMD0);
263 return 0;
264 }
265
266 /*
267 This function will read the PHY registers.
268 */
269 static int amd8111e_read_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 *val)
270 {
271 void *mmio = lp->mmio;
272 unsigned int reg_val;
273 unsigned int retry = PHY_RW_RETRY;
274
275 reg_val = readl(mmio + PHY_ACCESS);
276 while (reg_val & PHY_CMD_ACTIVE)
277 reg_val = readl(mmio + PHY_ACCESS);
278
279 writel(PHY_RD_CMD | ((phy_addr & 0x1f) << 21) | ((reg & 0x1f) << 16),
280 mmio + PHY_ACCESS);
281 do {
282 reg_val = readl(mmio + PHY_ACCESS);
283 udelay(30); /* It takes 30 us to read/write data */
284 } while (--retry && (reg_val & PHY_CMD_ACTIVE));
285
286 if (reg_val & PHY_RD_ERR) {
287 *val = 0;
288 return -1;
289 }
290
291 *val = reg_val & 0xffff;
292 return 0;
293 }
294
295 /*
296 This function will write into PHY registers.
297 */
298 #if 0
299 static int amd8111e_write_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 val)
300 {
301 void *mmio = lp->mmio;
302 unsigned int reg_val;
303 unsigned int retry = PHY_RW_RETRY;
304
305 reg_val = readl(mmio + PHY_ACCESS);
306 while (reg_val & PHY_CMD_ACTIVE)
307 reg_val = readl(mmio + PHY_ACCESS);
308
309 writel(PHY_WR_CMD | ((phy_addr & 0x1f) << 21) | ((reg & 0x1f) << 16) | val,
310 mmio + PHY_ACCESS);
311 do {
312 reg_val = readl(mmio + PHY_ACCESS);
313 udelay(30); /* It takes 30 us to read/write the data */
314 } while (--retry && (reg_val & PHY_CMD_ACTIVE));
315
316 if(reg_val & PHY_RD_ERR)
317 return -1;
318
319 return 0;
320 }
321 #endif
322
323 static void amd8111e_probe_ext_phy(struct amd8111e_priv *lp)
324 {
325 int i;
326
327 lp->ext_phy_id = 0;
328 lp->ext_phy_addr = 1;
329
330 for (i = 0x1e; i >= 0; i--) {
331 u32 id1, id2;
332
333 if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
334 continue;
335 if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
336 continue;
337 lp->ext_phy_id = (id1 << 16) | id2;
338 lp->ext_phy_addr = i;
339 break;
340 }
341
342 if (lp->ext_phy_id)
343 printf("Found MII PHY ID 0x%08x at address 0x%02x\n",
344 (unsigned int) lp->ext_phy_id, lp->ext_phy_addr);
345 else
346 printf("Couldn't detect MII PHY, assuming address 0x01\n");
347 }
348
349 static void amd8111e_disable_interrupt(struct amd8111e_priv *lp)
350 {
351 void *mmio = lp->mmio;
352 unsigned int int0;
353
354 writel(INTREN, mmio + CMD0);
355 writel(INTEN0_CLEAR, mmio + INTEN0);
356 int0 = readl(mmio + INT0);
357 writel(int0, mmio + INT0);
358 readl(mmio + INT0);
359 }
360
361 static void amd8111e_enable_interrupt(struct amd8111e_priv *lp)
362 {
363 void *mmio = lp->mmio;
364
365 writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
366 writel(VAL0 | INTREN, mmio + CMD0);
367 readl(mmio + CMD0);
368 }
369
370 static void amd8111e_force_interrupt(struct amd8111e_priv *lp)
371 {
372 void *mmio = lp->mmio;
373
374 writel(VAL0 | UINTCMD, mmio + CMD0);
375 readl(mmio + CMD0);
376 }
377
378 static int amd8111e_get_mac_address(struct amd8111e_priv *lp)
379 {
380 struct nic *nic = lp->nic;
381 void *mmio = lp->mmio;
382 int i;
383
384 /* BIOS should have set mac address to PADR register,
385 * so we read PADR to get it.
386 */
387 for (i = 0; i < ETH_ALEN; i++)
388 nic->node_addr[i] = readb(mmio + PADR + i);
389
390 DBG ( "Ethernet addr: %s\n", eth_ntoa ( nic->node_addr ) );
391
392 return 0;
393 }
394
395 static int amd8111e_init_rx_ring(struct amd8111e_priv *lp)
396 {
397 int i;
398
399 lp->rx_idx = 0;
400
401 /* Initilaizing receive descriptors */
402 for (i = 0; i < NUM_RX_SLOTS; i++) {
403 lp->rx_ring[i].buf_phy_addr = cpu_to_le32(virt_to_bus(lp->rx_buf[i]));
404 lp->rx_ring[i].buf_len = cpu_to_le16(RX_BUF_LEN);
405 wmb();
406 lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
407 }
408
409 return 0;
410 }
411
412 static int amd8111e_init_tx_ring(struct amd8111e_priv *lp)
413 {
414 int i;
415
416 lp->tx_idx = 0;
417 lp->tx_consistent = 1;
418
419 /* Initializing transmit descriptors */
420 for (i = 0; i < NUM_TX_SLOTS; i++) {
421 lp->tx_ring[i].tx_flags = 0;
422 lp->tx_ring[i].buf_phy_addr = 0;
423 lp->tx_ring[i].buf_len = 0;
424 }
425
426 return 0;
427 }
428
429 static int amd8111e_wait_tx_ring(struct amd8111e_priv *lp, unsigned int index)
430 {
431 volatile u16 status;
432 int retry = TX_RETRY;
433
434 status = le16_to_cpu(lp->tx_ring[index].tx_flags);
435 while (--retry && (status & OWN_BIT)) {
436 mdelay(TX_PROCESS_TIME);
437 status = le16_to_cpu(lp->tx_ring[index].tx_flags);
438 }
439 if (status & OWN_BIT) {
440 printf("Error: tx slot %d timeout, stat = 0x%x\n", index, status);
441 amd8111e_restart(lp);
442 return -1;
443 }
444
445 return 0;
446 }
447
448 static void amd8111e_wait_link(struct amd8111e_priv *lp)
449 {
450 unsigned int status;
451 u32 reg_val;
452
453 do {
454 /* read phy to update STAT0 register */
455 amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMCR, &reg_val);
456 amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMSR, &reg_val);
457 amd8111e_read_phy(lp, lp->ext_phy_addr, MII_ADVERTISE, &reg_val);
458 amd8111e_read_phy(lp, lp->ext_phy_addr, MII_LPA, &reg_val);
459 status = readl(lp->mmio + STAT0);
460 } while (!(status & AUTONEG_COMPLETE) || !(status & LINK_STATS));
461 }
462
463 static void amd8111e_poll_link(struct amd8111e_priv *lp)
464 {
465 unsigned int status, speed;
466 u32 reg_val;
467
468 if (!lp->link) {
469 /* read phy to update STAT0 register */
470 amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMCR, &reg_val);
471 amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMSR, &reg_val);
472 amd8111e_read_phy(lp, lp->ext_phy_addr, MII_ADVERTISE, &reg_val);
473 amd8111e_read_phy(lp, lp->ext_phy_addr, MII_LPA, &reg_val);
474 status = readl(lp->mmio + STAT0);
475
476 if (status & LINK_STATS) {
477 lp->link = 1;
478 speed = (status & SPEED_MASK) >> 7;
479 if (speed == PHY_SPEED_100)
480 lp->speed = 1;
481 else
482 lp->speed = 0;
483 if (status & FULL_DPLX)
484 lp->duplex = 1;
485 else
486 lp->duplex = 0;
487
488 printf("Link is up: %s Mbps %s duplex\n",
489 lp->speed ? "100" : "10", lp->duplex ? "full" : "half");
490 }
491 } else {
492 status = readl(lp->mmio + STAT0);
493 if (!(status & LINK_STATS)) {
494 lp->link = 0;
495 printf("Link is down\n");
496 }
497 }
498 }
499
500 static void amd8111e_restart(struct amd8111e_priv *lp)
501 {
502 printf("\nStarting nic...\n");
503 amd8111e_disable_interrupt(lp);
504 amd8111e_init_hw_default(lp);
505 amd8111e_probe_ext_phy(lp);
506 amd8111e_get_mac_address(lp);
507 amd8111e_start(lp);
508
509 printf("Waiting link up...\n");
510 lp->link = 0;
511 amd8111e_wait_link(lp);
512 amd8111e_poll_link(lp);
513 }
514
515
516 /********************************************************
517 * Interface Functions *
518 ********************************************************/
519
520 static void amd8111e_transmit(struct nic *nic, const char *dst_addr,
521 unsigned int type, unsigned int size, const char *packet)
522 {
523 struct amd8111e_priv *lp = nic->priv_data;
524 struct eth_frame *frame;
525 unsigned int index;
526
527 /* check packet size */
528 if (size > TX_PKT_LEN_MAX) {
529 printf("amd8111e_transmit(): too large packet, drop\n");
530 return;
531 }
532
533 /* get tx slot */
534 index = lp->tx_idx;
535 if (amd8111e_wait_tx_ring(lp, index))
536 return;
537
538 /* fill frame */
539 frame = (struct eth_frame *)lp->tx_buf[index];
540 memset(frame->data, 0, TX_PKT_LEN_MAX);
541 memcpy(frame->dst_addr, dst_addr, ETH_ALEN);
542 memcpy(frame->src_addr, nic->node_addr, ETH_ALEN);
543 frame->type = htons(type);
544 memcpy(frame->data, packet, size);
545
546 /* start xmit */
547 lp->tx_ring[index].buf_len = cpu_to_le16(ETH_HLEN + size);
548 lp->tx_ring[index].buf_phy_addr = cpu_to_le32(virt_to_bus(frame));
549 wmb();
550 lp->tx_ring[index].tx_flags =
551 cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT | ADD_FCS_BIT | LTINT_BIT);
552 writel(VAL1 | TDMD0, lp->mmio + CMD0);
553 readl(lp->mmio + CMD0);
554
555 /* update slot pointer */
556 lp->tx_idx = (lp->tx_idx + 1) & TX_SLOTS_MASK;
557 }
558
559 static int amd8111e_poll(struct nic *nic, int retrieve)
560 {
561 /* return true if there's an ethernet packet ready to read */
562 /* nic->packet should contain data on return */
563 /* nic->packetlen should contain length of data */
564
565 struct amd8111e_priv *lp = nic->priv_data;
566 u16 status, pkt_len;
567 unsigned int index, pkt_ok;
568
569 amd8111e_poll_link(lp);
570
571 index = lp->rx_idx;
572 status = le16_to_cpu(lp->rx_ring[index].rx_flags);
573 pkt_len = le16_to_cpu(lp->rx_ring[index].msg_len) - 4; /* remove 4bytes FCS */
574
575 if (status & OWN_BIT)
576 return 0;
577
578 if (status & ERR_BIT)
579 pkt_ok = 0;
580 else if (!(status & STP_BIT))
581 pkt_ok = 0;
582 else if (!(status & ENP_BIT))
583 pkt_ok = 0;
584 else if (pkt_len < RX_PKT_LEN_MIN)
585 pkt_ok = 0;
586 else if (pkt_len > RX_PKT_LEN_MAX)
587 pkt_ok = 0;
588 else
589 pkt_ok = 1;
590
591 if (pkt_ok) {
592 if (!retrieve)
593 return 1;
594 nic->packetlen = pkt_len;
595 memcpy(nic->packet, lp->rx_buf[index], nic->packetlen);
596 }
597
598 lp->rx_ring[index].buf_phy_addr = cpu_to_le32(virt_to_bus(lp->rx_buf[index]));
599 lp->rx_ring[index].buf_len = cpu_to_le16(RX_BUF_LEN);
600 wmb();
601 lp->rx_ring[index].rx_flags = cpu_to_le16(OWN_BIT);
602 writel(VAL2 | RDMD0, lp->mmio + CMD0);
603 readl(lp->mmio + CMD0);
604
605 lp->rx_idx = (lp->rx_idx + 1) & RX_SLOTS_MASK;
606 return pkt_ok;
607 }
608
609 static void amd8111e_disable(struct nic *nic)
610 {
611 struct amd8111e_priv *lp = nic->priv_data;
612
613 /* disable interrupt */
614 amd8111e_disable_interrupt(lp);
615
616 /* stop chip */
617 amd8111e_init_hw_default(lp);
618
619 /* unmap mmio */
620 iounmap(lp->mmio);
621
622 /* update status */
623 lp->opened = 0;
624 }
625
626 static void amd8111e_irq(struct nic *nic, irq_action_t action)
627 {
628 struct amd8111e_priv *lp = nic->priv_data;
629
630 switch (action) {
631 case DISABLE:
632 amd8111e_disable_interrupt(lp);
633 break;
634 case ENABLE:
635 amd8111e_enable_interrupt(lp);
636 break;
637 case FORCE:
638 amd8111e_force_interrupt(lp);
639 break;
640 }
641 }
642
643 static struct nic_operations amd8111e_operations = {
644 .connect = dummy_connect,
645 .poll = amd8111e_poll,
646 .transmit = amd8111e_transmit,
647 .irq = amd8111e_irq,
648 };
649
650 static int amd8111e_probe(struct nic *nic, struct pci_device *pdev)
651 {
652 struct amd8111e_priv *lp = &amd8111e;
653 unsigned long mmio_start, mmio_len;
654
655 nic->ioaddr = pdev->ioaddr;
656 nic->irqno = pdev->irq;
657
658 mmio_start = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
659 mmio_len = pci_bar_size(pdev, PCI_BASE_ADDRESS_0);
660
661 memset(lp, 0, sizeof(*lp));
662 lp->pdev = pdev;
663 lp->nic = nic;
664 lp->mmio = ioremap(mmio_start, mmio_len);
665 lp->opened = 1;
666 adjust_pci_device(pdev);
667
668 nic->priv_data = lp;
669
670 amd8111e_restart(lp);
671
672 nic->nic_op = &amd8111e_operations;
673 return 1;
674 }
675
676 static struct pci_device_id amd8111e_nics[] = {
677 PCI_ROM(0x1022, 0x7462, "amd8111e", "AMD8111E"),
678 };
679
680 PCI_DRIVER ( amd8111e_driver, amd8111e_nics, PCI_NO_CLASS );
681
682 DRIVER ( "AMD8111E", nic_driver, pci_driver, amd8111e_driver,
683 amd8111e_probe, amd8111e_disable );
684
685 /*
686 * Local variables:
687 * c-basic-offset: 8
688 * c-indent-level: 8
689 * tab-width: 8
690 * End:
691 */