gpxe/src/drivers/net/davicom.c

   1 #ifdef ALLMULTI
   2 #error multicast support is not yet implemented
   3 #endif
   4 /*
   5     DAVICOM DM9009/DM9102/DM9102A Etherboot Driver      V1.00
   6
   7     This driver was ported from Marty Connor's Tulip Etherboot driver.
   8     Thanks Marty Connor (mdc@etherboot.org)
   9
  10     This davicom etherboot driver supports DM9009/DM9102/DM9102A/
  11     DM9102A+DM9801/DM9102A+DM9802 NICs.
  12
  13     This software may be used and distributed according to the terms
  14     of the GNU Public License, incorporated herein by reference.
  15
  16 */
  17
  18 /*********************************************************************/
  19 /* Revision History                                                  */
  20 /*********************************************************************/
  21
  22 /*
  23   19 OCT 2000  Sten     1.00
  24                         Different half and full duplex mode
  25                         Do the different programming for DM9801/DM9802
  26
  27   12 OCT 2000  Sten     0.90
  28                         This driver was ported from tulip driver and it
  29                         has the following difference.
  30                         Changed symbol tulip/TULIP to davicom/DAVICOM
  31                         Deleted some code that did not use in this driver.
  32                         Used chain-strcture to replace ring structure
  33                         for both TX/RX descriptor.
  34                         Allocated two tx descriptor.
  35                         According current media mode to set operating
  36                         register(CR6)
  37 */
  38
  39 \f
  40 /*********************************************************************/
  41 /* Declarations                                                      */
  42 /*********************************************************************/
  43
  44 #include "etherboot.h"
  45 #include "nic.h"
  46 #include <gpxe/pci.h>
  47 #include <gpxe/ethernet.h>
  48
  49 #undef DAVICOM_DEBUG
  50 #undef DAVICOM_DEBUG_WHERE
  51
  52 #define TX_TIME_OUT       2*TICKS_PER_SEC
  53
  54 /* Register offsets for davicom device */
  55 enum davicom_offsets {
  56    CSR0=0,     CSR1=0x08,  CSR2=0x10,  CSR3=0x18,  CSR4=0x20,  CSR5=0x28,
  57    CSR6=0x30,  CSR7=0x38,  CSR8=0x40,  CSR9=0x48, CSR10=0x50, CSR11=0x58,
  58   CSR12=0x60, CSR13=0x68, CSR14=0x70, CSR15=0x78, CSR16=0x80, CSR20=0xA0
  59 };
  60
  61 /* EEPROM Address width definitions */
  62 #define EEPROM_ADDRLEN 6
  63 #define EEPROM_SIZE    32              /* 1 << EEPROM_ADDRLEN */
  64 /* Used to be 128, but we only need to read enough to get the MAC
  65    address at bytes 20..25 */
  66
  67 /* Data Read from the EEPROM */
  68 static unsigned char ee_data[EEPROM_SIZE];
  69
  70 /* The EEPROM commands include the alway-set leading bit. */
  71 #define EE_WRITE_CMD    (5 << addr_len)
  72 #define EE_READ_CMD     (6 << addr_len)
  73 #define EE_ERASE_CMD    (7 << addr_len)
  74
  75 /* EEPROM_Ctrl bits. */
  76 #define EE_SHIFT_CLK    0x02    /* EEPROM shift clock. */
  77 #define EE_CS           0x01    /* EEPROM chip select. */
  78 #define EE_DATA_WRITE   0x04    /* EEPROM chip data in. */
  79 #define EE_WRITE_0      0x01
  80 #define EE_WRITE_1      0x05
  81 #define EE_DATA_READ    0x08    /* EEPROM chip data out. */
  82 #define EE_ENB          (0x4800 | EE_CS)
  83
  84 /* Sten 10/11 for phyxcer */
  85 #define PHY_DATA_0      0x0
  86 #define PHY_DATA_1      0x20000
  87 #define MDCLKH          0x10000
  88
  89 /* Delay between EEPROM clock transitions.  Even at 33Mhz current PCI
  90    implementations don't overrun the EEPROM clock.  We add a bus
  91    turn-around to insure that this remains true.  */
  92 #define eeprom_delay()  inl(ee_addr)
  93
  94 /* helpful macro if on a big_endian machine for changing byte order.
  95    not strictly needed on Intel
  96    Already defined in Etherboot includes
  97 #define le16_to_cpu(val) (val)
  98 */
  99
 100 /* transmit and receive descriptor format */
 101 struct txdesc {
 102   volatile unsigned long   status;         /* owner, status */
 103   unsigned long   buf1sz:11,      /* size of buffer 1 */
 104     buf2sz:11,                    /* size of buffer 2 */
 105     control:10;                   /* control bits */
 106   const unsigned char *buf1addr;  /* buffer 1 address */
 107   const unsigned char *buf2addr;  /* buffer 2 address */
 108 };
 109
 110 struct rxdesc {
 111   volatile unsigned long   status;         /* owner, status */
 112   unsigned long   buf1sz:11,      /* size of buffer 1 */
 113     buf2sz:11,                    /* size of buffer 2 */
 114     control:10;                   /* control bits */
 115   unsigned char   *buf1addr;      /* buffer 1 address */
 116   unsigned char   *buf2addr;      /* buffer 2 address */
 117 };
 118
 119 /* Size of transmit and receive buffers */
 120 #define BUFLEN 1536
 121
 122 /*********************************************************************/
 123 /* Global Storage                                                    */
 124 /*********************************************************************/
 125
 126 static struct nic_operations davicom_operations;
 127
 128 /* PCI Bus parameters */
 129 static unsigned short vendor, dev_id;
 130 static unsigned long ioaddr;
 131
 132 /* Note: transmit and receive buffers must be longword aligned and
 133    longword divisable */
 134
 135 /* transmit descriptor and buffer */
 136 #define NTXD 2
 137 #define NRXD 4
 138 struct {
 139         struct txdesc txd[NTXD] __attribute__ ((aligned(4)));
 140         unsigned char txb[BUFLEN] __attribute__ ((aligned(4)));
 141         struct rxdesc rxd[NRXD] __attribute__ ((aligned(4)));
 142         unsigned char rxb[NRXD * BUFLEN] __attribute__ ((aligned(4)));
 143 } davicom_bufs __shared;
 144 #define txd davicom_bufs.txd
 145 #define txb davicom_bufs.txb
 146 #define rxd davicom_bufs.rxd
 147 #define rxb davicom_bufs.rxb
 148 static int rxd_tail;
 149 static int TxPtr;
 150
 151 \f
 152 /*********************************************************************/
 153 /* Function Prototypes                                               */
 154 /*********************************************************************/
 155 static void whereami(const char *str);
 156 static int read_eeprom(unsigned long ioaddr, int location, int addr_len);
 157 static int davicom_probe(struct nic *nic,struct pci_device *pci);
 158 static void davicom_init_chain(struct nic *nic);        /* Sten 10/9 */
 159 static void davicom_reset(struct nic *nic);
 160 static void davicom_transmit(struct nic *nic, const char *d, unsigned int t,
 161                            unsigned int s, const char *p);
 162 static int davicom_poll(struct nic *nic, int retrieve);
 163 static void davicom_disable(struct nic *nic);
 164 #ifdef  DAVICOM_DEBUG
 165 static void davicom_more(void);
 166 #endif /* DAVICOM_DEBUG */
 167 static void davicom_wait(unsigned int nticks);
 168 static int phy_read(int);
 169 static void phy_write(int, u16);
 170 static void phy_write_1bit(u32, u32);
 171 static int phy_read_1bit(u32);
 172 static void davicom_media_chk(struct nic *);
 173
 174 \f
 175 /*********************************************************************/
 176 /* Utility Routines                                                  */
 177 /*********************************************************************/
 178 static inline void whereami(const char *str)
 179 {
 180   printf("%s\n", str);
 181   /* sleep(2); */
 182 }
 183
 184 #ifdef  DAVICOM_DEBUG
 185 static void davicom_more()
 186 {
 187   printf("\n\n-- more --");
 188   while (!iskey())
 189     /* wait */;
 190   getchar();
 191   printf("\n\n");
 192 }
 193 #endif /* DAVICOM_DEBUG */
 194
 195 static void davicom_wait(unsigned int nticks)
 196 {
 197   unsigned int to = currticks() + nticks;
 198   while (currticks() < to)
 199     /* wait */ ;
 200 }
 201
 202 \f
 203 /*********************************************************************/
 204 /* For DAVICOM phyxcer register by MII interface                     */
 205 /*********************************************************************/
 206 /*
 207   Read a word data from phy register
 208 */
 209 static int phy_read(int location)
 210 {
 211  int i, phy_addr=1;
 212  u16 phy_data;
 213  u32 io_dcr9;
 214
 215  whereami("phy_read\n");
 216
 217  io_dcr9 = ioaddr + CSR9;
 218
 219  /* Send 33 synchronization clock to Phy controller */
 220  for (i=0; i<34; i++)
 221      phy_write_1bit(io_dcr9, PHY_DATA_1);
 222
 223  /* Send start command(01) to Phy */
 224  phy_write_1bit(io_dcr9, PHY_DATA_0);
 225  phy_write_1bit(io_dcr9, PHY_DATA_1);
 226
 227  /* Send read command(10) to Phy */
 228  phy_write_1bit(io_dcr9, PHY_DATA_1);
 229  phy_write_1bit(io_dcr9, PHY_DATA_0);
 230
 231  /* Send Phy addres */
 232  for (i=0x10; i>0; i=i>>1)
 233      phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0);
 234
 235  /* Send register addres */
 236  for (i=0x10; i>0; i=i>>1)
 237      phy_write_1bit(io_dcr9, location&i ? PHY_DATA_1: PHY_DATA_0);
 238
 239  /* Skip transition state */
 240  phy_read_1bit(io_dcr9);
 241
 242  /* read 16bit data */
 243  for (phy_data=0, i=0; i<16; i++) {
 244    phy_data<<=1;
 245    phy_data|=phy_read_1bit(io_dcr9);
 246  }
 247
 248  return phy_data;
 249 }
 250
 251 /*
 252   Write a word to Phy register
 253 */
 254 static void phy_write(int location, u16 phy_data)
 255 {
 256  u16 i, phy_addr=1;
 257  u32 io_dcr9;
 258
 259  whereami("phy_write\n");
 260
 261  io_dcr9 = ioaddr + CSR9;
 262
 263  /* Send 33 synchronization clock to Phy controller */
 264  for (i=0; i<34; i++)
 265    phy_write_1bit(io_dcr9, PHY_DATA_1);
 266
 267  /* Send start command(01) to Phy */
 268  phy_write_1bit(io_dcr9, PHY_DATA_0);
 269  phy_write_1bit(io_dcr9, PHY_DATA_1);
 270
 271  /* Send write command(01) to Phy */
 272  phy_write_1bit(io_dcr9, PHY_DATA_0);
 273  phy_write_1bit(io_dcr9, PHY_DATA_1);
 274
 275  /* Send Phy addres */
 276  for (i=0x10; i>0; i=i>>1)
 277    phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0);
 278
 279  /* Send register addres */
 280  for (i=0x10; i>0; i=i>>1)
 281    phy_write_1bit(io_dcr9, location&i ? PHY_DATA_1: PHY_DATA_0);
 282
 283  /* written trasnition */
 284  phy_write_1bit(io_dcr9, PHY_DATA_1);
 285  phy_write_1bit(io_dcr9, PHY_DATA_0);
 286
 287  /* Write a word data to PHY controller */
 288  for (i=0x8000; i>0; i>>=1)
 289    phy_write_1bit(io_dcr9, phy_data&i ? PHY_DATA_1: PHY_DATA_0);
 290 }
 291
 292 /*
 293   Write one bit data to Phy Controller
 294 */
 295 static void phy_write_1bit(u32 ee_addr, u32 phy_data)
 296 {
 297  whereami("phy_write_1bit\n");
 298  outl(phy_data, ee_addr);                        /* MII Clock Low */
 299  eeprom_delay();
 300  outl(phy_data|MDCLKH, ee_addr);                 /* MII Clock High */
 301  eeprom_delay();
 302  outl(phy_data, ee_addr);                        /* MII Clock Low */
 303  eeprom_delay();
 304 }
 305
 306 /*
 307   Read one bit phy data from PHY controller
 308 */
 309 static int phy_read_1bit(u32 ee_addr)
 310 {
 311  int phy_data;
 312
 313  whereami("phy_read_1bit\n");
 314
 315  outl(0x50000, ee_addr);
 316  eeprom_delay();
 317
 318  phy_data=(inl(ee_addr)>>19) & 0x1;
 319
 320  outl(0x40000, ee_addr);
 321  eeprom_delay();
 322
 323  return phy_data;
 324 }
 325
 326 /*
 327   DM9801/DM9802 present check and program
 328 */
 329 static void HPNA_process(void)
 330 {
 331
 332  if ( (phy_read(3) & 0xfff0) == 0xb900 ) {
 333    if ( phy_read(31) == 0x4404 ) {
 334      /* DM9801 present */
 335      if (phy_read(3) == 0xb901)
 336        phy_write(16, 0x5);      /* DM9801 E4 */
 337      else
 338        phy_write(16, 0x1005); /* DM9801 E3 and others */
 339      phy_write(25, ((phy_read(24) + 3) & 0xff) | 0xf000);
 340    } else {
 341      /* DM9802 present */
 342      phy_write(16, 0x5);
 343      phy_write(25, (phy_read(25) & 0xff00) + 2);
 344    }
 345  }
 346 }
 347
 348 /*
 349   Sense media mode and set CR6
 350 */
 351 static void davicom_media_chk(struct nic * nic __unused)
 352 {
 353   unsigned long to, csr6;
 354
 355   csr6 = 0x00200000;    /* SF */
 356   outl(csr6, ioaddr + CSR6);
 357
 358 #define PCI_DEVICE_ID_DM9009            0x9009
 359   if (vendor == PCI_VENDOR_ID_DAVICOM && dev_id == PCI_DEVICE_ID_DM9009) {
 360     /* Set to 10BaseT mode for DM9009 */
 361     phy_write(0, 0);
 362   } else {
 363     /* For DM9102/DM9102A */
 364     to = currticks() + 2 * TICKS_PER_SEC;
 365     while ( ((phy_read(1) & 0x24)!=0x24) && (currticks() < to))
 366       /* wait */ ;
 367
 368     if ( (phy_read(1) & 0x24) == 0x24 ) {
 369       if (phy_read(17) & 0xa000)
 370         csr6 |= 0x00000200;     /* Full Duplex mode */
 371     } else
 372       csr6 |= 0x00040000; /* Select DM9801/DM9802 when Ethernet link failed */
 373   }
 374
 375   /* set the chip's operating mode */
 376   outl(csr6, ioaddr + CSR6);
 377
 378   /* DM9801/DM9802 present check & program */
 379   if (csr6 & 0x40000)
 380     HPNA_process();
 381 }
 382
 383 \f
 384 /*********************************************************************/
 385 /* EEPROM Reading Code                                               */
 386 /*********************************************************************/
 387 /* EEPROM routines adapted from the Linux Tulip Code */
 388 /* Reading a serial EEPROM is a "bit" grungy, but we work our way
 389    through:->.
 390 */
 391 static int read_eeprom(unsigned long ioaddr, int location, int addr_len)
 392 {
 393   int i;
 394   unsigned short retval = 0;
 395   long ee_addr = ioaddr + CSR9;
 396   int read_cmd = location | EE_READ_CMD;
 397
 398   whereami("read_eeprom\n");
 399
 400   outl(EE_ENB & ~EE_CS, ee_addr);
 401   outl(EE_ENB, ee_addr);
 402
 403   /* Shift the read command bits out. */
 404   for (i = 4 + addr_len; i >= 0; i--) {
 405     short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
 406     outl(EE_ENB | dataval, ee_addr);
 407     eeprom_delay();
 408     outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
 409     eeprom_delay();
 410   }
 411   outl(EE_ENB, ee_addr);
 412
 413   for (i = 16; i > 0; i--) {
 414     outl(EE_ENB | EE_SHIFT_CLK, ee_addr);
 415     eeprom_delay();
 416     retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
 417     outl(EE_ENB, ee_addr);
 418     eeprom_delay();
 419   }
 420
 421   /* Terminate the EEPROM access. */
 422   outl(EE_ENB & ~EE_CS, ee_addr);
 423   return retval;
 424 }
 425 \f
 426 /*********************************************************************/
 427 /* davicom_init_chain - setup the tx and rx descriptors                */
 428 /* Sten 10/9                                                         */
 429 /*********************************************************************/
 430 static void davicom_init_chain(struct nic *nic)
 431 {
 432   int i;
 433
 434   /* setup the transmit descriptor */
 435   /* Sten: Set 2 TX descriptor but use one TX buffer because
 436            it transmit a packet and wait complete every time. */
 437   for (i=0; i<NTXD; i++) {
 438     txd[i].buf1addr = (void *)virt_to_bus(&txb[0]);     /* Used same TX buffer */
 439     txd[i].buf2addr = (void *)virt_to_bus(&txd[i+1]);   /*  Point to Next TX desc */
 440     txd[i].buf1sz   = 0;
 441     txd[i].buf2sz   = 0;
 442     txd[i].control  = 0x184;           /* Begin/End/Chain */
 443     txd[i].status   = 0x00000000;      /* give ownership to Host */
 444   }
 445
 446   /* construct perfect filter frame with mac address as first match
 447      and broadcast address for all others */
 448   for (i=0; i<192; i++) txb[i] = 0xFF;
 449   txb[0] = nic->node_addr[0];
 450   txb[1] = nic->node_addr[1];
 451   txb[4] = nic->node_addr[2];
 452   txb[5] = nic->node_addr[3];
 453   txb[8] = nic->node_addr[4];
 454   txb[9] = nic->node_addr[5];
 455
 456   /* setup receive descriptor */
 457   for (i=0; i<NRXD; i++) {
 458     rxd[i].buf1addr = (void *)virt_to_bus(&rxb[i * BUFLEN]);
 459     rxd[i].buf2addr = (void *)virt_to_bus(&rxd[i+1]); /* Point to Next RX desc */
 460     rxd[i].buf1sz   = BUFLEN;
 461     rxd[i].buf2sz   = 0;        /* not used */
 462     rxd[i].control  = 0x4;              /* Chain Structure */
 463     rxd[i].status   = 0x80000000;   /* give ownership to device */
 464   }
 465
 466   /* Chain the last descriptor to first */
 467   txd[NTXD - 1].buf2addr = (void *)virt_to_bus(&txd[0]);
 468   rxd[NRXD - 1].buf2addr = (void *)virt_to_bus(&rxd[0]);
 469   TxPtr = 0;
 470   rxd_tail = 0;
 471 }
 472
 473 \f
 474 /*********************************************************************/
 475 /* davicom_reset - Reset adapter                                         */
 476 /*********************************************************************/
 477 static void davicom_reset(struct nic *nic)
 478 {
 479   unsigned long to;
 480
 481   whereami("davicom_reset\n");
 482
 483   /* Stop Tx and RX */
 484   outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
 485
 486   /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
 487   outl(0x00000001, ioaddr + CSR0);
 488
 489   davicom_wait(TICKS_PER_SEC);
 490
 491   /* TX/RX descriptor burst */
 492   outl(0x0C00000, ioaddr + CSR0);       /* Sten 10/9 */
 493
 494   /* set up transmit and receive descriptors */
 495   davicom_init_chain(nic);      /* Sten 10/9 */
 496
 497   /* Point to receive descriptor */
 498   outl(virt_to_bus(&rxd[0]), ioaddr + CSR3);
 499   outl(virt_to_bus(&txd[0]), ioaddr + CSR4);    /* Sten 10/9 */
 500
 501   /* According phyxcer media mode to set CR6,
 502      DM9102/A phyxcer can auto-detect media mode */
 503   davicom_media_chk(nic);
 504
 505   /* Prepare Setup Frame Sten 10/9 */
 506   txd[TxPtr].buf1sz = 192;
 507   txd[TxPtr].control = 0x024;           /* SF/CE */
 508   txd[TxPtr].status = 0x80000000;       /* Give ownership to device */
 509
 510   /* Start Tx */
 511   outl(inl(ioaddr + CSR6) | 0x00002000, ioaddr + CSR6);
 512   /* immediate transmit demand */
 513   outl(0, ioaddr + CSR1);
 514
 515   to = currticks() + TX_TIME_OUT;
 516   while ((txd[TxPtr].status & 0x80000000) && (currticks() < to)) /* Sten 10/9 */
 517     /* wait */ ;
 518
 519   if (currticks() >= to) {
 520     printf ("TX Setup Timeout!\n");
 521   }
 522   /* Point to next TX descriptor */
 523  TxPtr = (++TxPtr >= NTXD) ? 0:TxPtr;   /* Sten 10/9 */
 524
 525 #ifdef DAVICOM_DEBUG
 526   printf("txd.status = %X\n", txd.status);
 527   printf("ticks = %d\n", currticks() - (to - TX_TIME_OUT));
 528   davicom_more();
 529 #endif
 530
 531   /* enable RX */
 532   outl(inl(ioaddr + CSR6) | 0x00000002, ioaddr + CSR6);
 533   /* immediate poll demand */
 534   outl(0, ioaddr + CSR2);
 535 }
 536
 537 \f
 538 /*********************************************************************/
 539 /* eth_transmit - Transmit a frame                                   */
 540 /*********************************************************************/
 541 static void davicom_transmit(struct nic *nic, const char *d, unsigned int t,
 542                            unsigned int s, const char *p)
 543 {
 544   unsigned long to;
 545
 546   whereami("davicom_transmit\n");
 547
 548   /* Stop Tx */
 549   /* outl(inl(ioaddr + CSR6) & ~0x00002000, ioaddr + CSR6); */
 550
 551   /* setup ethernet header */
 552   memcpy(&txb[0], d, ETH_ALEN); /* DA 6byte */
 553   memcpy(&txb[ETH_ALEN], nic->node_addr, ETH_ALEN); /* SA 6byte*/
 554   txb[ETH_ALEN*2] = (t >> 8) & 0xFF; /* Frame type: 2byte */
 555   txb[ETH_ALEN*2+1] = t & 0xFF;
 556   memcpy(&txb[ETH_HLEN], p, s); /* Frame data */
 557
 558   /* setup the transmit descriptor */
 559   txd[TxPtr].buf1sz   = ETH_HLEN+s;
 560   txd[TxPtr].control  = 0x00000184;      /* LS+FS+CE */
 561   txd[TxPtr].status   = 0x80000000;      /* give ownership to device */
 562
 563   /* immediate transmit demand */
 564   outl(0, ioaddr + CSR1);
 565
 566   to = currticks() + TX_TIME_OUT;
 567   while ((txd[TxPtr].status & 0x80000000) && (currticks() < to))
 568     /* wait */ ;
 569
 570   if (currticks() >= to) {
 571     printf ("TX Timeout!\n");
 572   }
 573
 574   /* Point to next TX descriptor */
 575   TxPtr = (++TxPtr >= NTXD) ? 0:TxPtr;  /* Sten 10/9 */
 576
 577 }
 578 \f
 579 /*********************************************************************/
 580 /* eth_poll - Wait for a frame                                       */
 581 /*********************************************************************/
 582 static int davicom_poll(struct nic *nic, int retrieve)
 583 {
 584   whereami("davicom_poll\n");
 585
 586   if (rxd[rxd_tail].status & 0x80000000)
 587     return 0;
 588
 589   if ( ! retrieve ) return 1;
 590
 591   whereami("davicom_poll got one\n");
 592
 593   nic->packetlen = (rxd[rxd_tail].status & 0x3FFF0000) >> 16;
 594
 595   if( rxd[rxd_tail].status & 0x00008000){
 596       rxd[rxd_tail].status = 0x80000000;
 597       rxd_tail++;
 598       if (rxd_tail == NRXD) rxd_tail = 0;
 599       return 0;
 600   }
 601
 602   /* copy packet to working buffer */
 603   /* XXX - this copy could be avoided with a little more work
 604      but for now we are content with it because the optimised
 605      memcpy is quite fast */
 606
 607   memcpy(nic->packet, rxb + rxd_tail * BUFLEN, nic->packetlen);
 608
 609   /* return the descriptor and buffer to receive ring */
 610   rxd[rxd_tail].status = 0x80000000;
 611   rxd_tail++;
 612   if (rxd_tail == NRXD) rxd_tail = 0;
 613
 614   return 1;
 615 }
 616 \f
 617 /*********************************************************************/
 618 /* eth_disable - Disable the interface                               */
 619 /*********************************************************************/
 620 static void davicom_disable ( struct nic *nic ) {
 621
 622   whereami("davicom_disable\n");
 623
 624   davicom_reset(nic);
 625
 626   /* disable interrupts */
 627   outl(0x00000000, ioaddr + CSR7);
 628
 629   /* Stop the chip's Tx and Rx processes. */
 630   outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
 631
 632   /* Clear the missed-packet counter. */
 633   (volatile unsigned long)inl(ioaddr + CSR8);
 634 }
 635
 636 \f
 637 /*********************************************************************/
 638 /* eth_irq - enable, disable and force interrupts                    */
 639 /*********************************************************************/
 640 static void davicom_irq(struct nic *nic __unused, irq_action_t action __unused)
 641 {
 642   switch ( action ) {
 643   case DISABLE :
 644     break;
 645   case ENABLE :
 646     break;
 647   case FORCE :
 648     break;
 649   }
 650 }
 651
 652 \f
 653 /*********************************************************************/
 654 /* eth_probe - Look for an adapter                                   */
 655 /*********************************************************************/
 656 static int davicom_probe ( struct nic *nic, struct pci_device *pci ) {
 657
 658   unsigned int i;
 659
 660   whereami("davicom_probe\n");
 661
 662   if (pci->ioaddr == 0)
 663     return 0;
 664
 665   vendor  = pci->vendor;
 666   dev_id  = pci->device;
 667   ioaddr  = pci->ioaddr;
 668
 669   nic->ioaddr = pci->ioaddr;
 670   nic->irqno = 0;
 671
 672   /* wakeup chip */
 673   pci_write_config_dword(pci, 0x40, 0x00000000);
 674
 675   /* Stop the chip's Tx and Rx processes. */
 676   outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
 677
 678   /* Clear the missed-packet counter. */
 679   (volatile unsigned long)inl(ioaddr + CSR8);
 680
 681   /* Get MAC Address */
 682   /* read EEPROM data */
 683   for (i = 0; i < sizeof(ee_data)/2; i++)
 684     ((unsigned short *)ee_data)[i] =
 685         le16_to_cpu(read_eeprom(ioaddr, i, EEPROM_ADDRLEN));
 686
 687   /* extract MAC address from EEPROM buffer */
 688   for (i=0; i<ETH_ALEN; i++)
 689     nic->node_addr[i] = ee_data[20+i];
 690
 691   DBG ( "Davicom %s at IOADDR %4.4lx\n", eth_ntoa ( nic->node_addr ), ioaddr );
 692
 693   /* initialize device */
 694   davicom_reset(nic);
 695   nic->nic_op   = &davicom_operations;
 696   return 1;
 697 }
 698
 699 static struct nic_operations davicom_operations = {
 700         .connect        = dummy_connect,
 701         .poll           = davicom_poll,
 702         .transmit       = davicom_transmit,
 703         .irq            = davicom_irq,
 704
 705 };
 706
 707 static struct pci_device_id davicom_nics[] = {
 708 PCI_ROM(0x1282, 0x9100, "davicom9100", "Davicom 9100"),
 709 PCI_ROM(0x1282, 0x9102, "davicom9102", "Davicom 9102"),
 710 PCI_ROM(0x1282, 0x9009, "davicom9009", "Davicom 9009"),
 711 PCI_ROM(0x1282, 0x9132, "davicom9132", "Davicom 9132"), /* Needs probably some fixing */
 712 };
 713
 714 PCI_DRIVER ( davicom_driver, davicom_nics, PCI_NO_CLASS );
 715
 716 DRIVER ( "DAVICOM", nic_driver, pci_driver, davicom_driver,
 717          davicom_probe, davicom_disable );
 718
 719 /*
 720  * Local variables:
 721  *  c-basic-offset: 8
 722  *  c-indent-level: 8
 723  *  tab-width: 8
 724  * End:
 725  */