gpxe/src/drivers/net/forcedeth.c

   1 /**************************************************************************
   2 *    forcedeth.c -- Etherboot device driver for the NVIDIA nForce
   3 *                       media access controllers.
   4 *
   5 * Note: This driver is based on the Linux driver that was based on
   6 *      a cleanroom reimplementation which was based on reverse
   7 *      engineered documentation written by Carl-Daniel Hailfinger
   8 *      and Andrew de Quincey. It's neither supported nor endorsed
   9 *      by NVIDIA Corp. Use at your own risk.
  10 *
  11 *    Written 2004 by Timothy Legge <tlegge@rogers.com>
  12 *
  13 *    This program is free software; you can redistribute it and/or modify
  14 *    it under the terms of the GNU General Public License as published by
  15 *    the Free Software Foundation; either version 2 of the License, or
  16 *    (at your option) any later version.
  17 *
  18 *    This program is distributed in the hope that it will be useful,
  19 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21 *    GNU General Public License for more details.
  22 *
  23 *    You should have received a copy of the GNU General Public License
  24 *    along with this program; if not, write to the Free Software
  25 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  26 *
  27 *    Portions of this code based on:
  28 *               forcedeth: Ethernet driver for NVIDIA nForce media access controllers:
  29 *
  30 *       (C) 2003 Manfred Spraul
  31 *               See Linux Driver for full information
  32 *
  33 *       Linux Driver Version 0.30, 25 Sep 2004
  34 *       Linux Kernel 2.6.10
  35 *
  36 *
  37 *    REVISION HISTORY:
  38 *    ================
  39 *    v1.0       01-31-2004      timlegge        Initial port of Linux driver
  40 *    v1.1       02-03-2004      timlegge        Large Clean up, first release
  41 *    v1.2       05-14-2005      timlegge        Add Linux 0.22 to .030 features
  42 *
  43 *    Indent Options: indent -kr -i8
  44 ***************************************************************************/
  45
  46 /* to get some global routines like printf */
  47 #include "etherboot.h"
  48 /* to get the interface to the body of the program */
  49 #include "nic.h"
  50 /* to get the PCI support functions, if this is a PCI NIC */
  51 #include <gpxe/pci.h>
  52 /* Include timer support functions */
  53 #include <gpxe/ethernet.h>
  54 #include "mii.h"
  55
  56 #define drv_version "v1.2"
  57 #define drv_date "05-14-2005"
  58
  59 //#define TFTM_DEBUG
  60 #ifdef TFTM_DEBUG
  61 #define dprintf(x) printf x
  62 #else
  63 #define dprintf(x)
  64 #endif
  65
  66 #define ETH_DATA_LEN   1500
  67
  68 /* Condensed operations for readability. */
  69 #define virt_to_le32desc(addr)  cpu_to_le32(virt_to_bus(addr))
  70 #define le32desc_to_virt(addr)  bus_to_virt(le32_to_cpu(addr))
  71
  72 static unsigned long BASE;
  73 /* NIC specific static variables go here */
  74 #define PCI_DEVICE_ID_NVIDIA_NVENET_1           0x01c3
  75 #define PCI_DEVICE_ID_NVIDIA_NVENET_2           0x0066
  76 #define PCI_DEVICE_ID_NVIDIA_NVENET_4           0x0086
  77 #define PCI_DEVICE_ID_NVIDIA_NVENET_5           0x008c
  78 #define PCI_DEVICE_ID_NVIDIA_NVENET_3           0x00d6
  79 #define PCI_DEVICE_ID_NVIDIA_NVENET_7           0x00df
  80 #define PCI_DEVICE_ID_NVIDIA_NVENET_6           0x00e6
  81 #define PCI_DEVICE_ID_NVIDIA_NVENET_8           0x0056
  82 #define PCI_DEVICE_ID_NVIDIA_NVENET_9           0x0057
  83 #define PCI_DEVICE_ID_NVIDIA_NVENET_10          0x0037
  84 #define PCI_DEVICE_ID_NVIDIA_NVENET_11          0x0038
  85
  86
  87 /*
  88  * Hardware access:
  89  */
  90
  91 #define DEV_NEED_LASTPACKET1    0x0001  /* set LASTPACKET1 in tx flags */
  92 #define DEV_IRQMASK_1           0x0002  /* use NVREG_IRQMASK_WANTED_1 for irq mask */
  93 #define DEV_IRQMASK_2           0x0004  /* use NVREG_IRQMASK_WANTED_2 for irq mask */
  94 #define DEV_NEED_TIMERIRQ       0x0008  /* set the timer irq flag in the irq mask */
  95 #define DEV_NEED_LINKTIMER      0x0010  /* poll link settings. Relies on the timer irq */
  96
  97 enum {
  98         NvRegIrqStatus = 0x000,
  99 #define NVREG_IRQSTAT_MIIEVENT  0040
 100 #define NVREG_IRQSTAT_MASK              0x1ff
 101         NvRegIrqMask = 0x004,
 102 #define NVREG_IRQ_RX_ERROR              0x0001
 103 #define NVREG_IRQ_RX                    0x0002
 104 #define NVREG_IRQ_RX_NOBUF              0x0004
 105 #define NVREG_IRQ_TX_ERR                0x0008
 106 #define NVREG_IRQ_TX2                   0x0010
 107 #define NVREG_IRQ_TIMER                 0x0020
 108 #define NVREG_IRQ_LINK                  0x0040
 109 #define NVREG_IRQ_TX1                   0x0100
 110 #define NVREG_IRQMASK_WANTED_1          0x005f
 111 #define NVREG_IRQMASK_WANTED_2          0x0147
 112 #define NVREG_IRQ_UNKNOWN               (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR|NVREG_IRQ_TX2|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX1))
 113
 114         NvRegUnknownSetupReg6 = 0x008,
 115 #define NVREG_UNKSETUP6_VAL             3
 116
 117 /*
 118  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 119  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 120  */
 121         NvRegPollingInterval = 0x00c,
 122 #define NVREG_POLL_DEFAULT      970
 123         NvRegMisc1 = 0x080,
 124 #define NVREG_MISC1_HD          0x02
 125 #define NVREG_MISC1_FORCE       0x3b0f3c
 126
 127         NvRegTransmitterControl = 0x084,
 128 #define NVREG_XMITCTL_START     0x01
 129         NvRegTransmitterStatus = 0x088,
 130 #define NVREG_XMITSTAT_BUSY     0x01
 131
 132         NvRegPacketFilterFlags = 0x8c,
 133 #define NVREG_PFF_ALWAYS        0x7F0008
 134 #define NVREG_PFF_PROMISC       0x80
 135 #define NVREG_PFF_MYADDR        0x20
 136
 137         NvRegOffloadConfig = 0x90,
 138 #define NVREG_OFFLOAD_HOMEPHY   0x601
 139 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 140         NvRegReceiverControl = 0x094,
 141 #define NVREG_RCVCTL_START      0x01
 142         NvRegReceiverStatus = 0x98,
 143 #define NVREG_RCVSTAT_BUSY      0x01
 144
 145         NvRegRandomSeed = 0x9c,
 146 #define NVREG_RNDSEED_MASK      0x00ff
 147 #define NVREG_RNDSEED_FORCE     0x7f00
 148 #define NVREG_RNDSEED_FORCE2    0x2d00
 149 #define NVREG_RNDSEED_FORCE3    0x7400
 150
 151         NvRegUnknownSetupReg1 = 0xA0,
 152 #define NVREG_UNKSETUP1_VAL     0x16070f
 153         NvRegUnknownSetupReg2 = 0xA4,
 154 #define NVREG_UNKSETUP2_VAL     0x16
 155         NvRegMacAddrA = 0xA8,
 156         NvRegMacAddrB = 0xAC,
 157         NvRegMulticastAddrA = 0xB0,
 158 #define NVREG_MCASTADDRA_FORCE  0x01
 159         NvRegMulticastAddrB = 0xB4,
 160         NvRegMulticastMaskA = 0xB8,
 161         NvRegMulticastMaskB = 0xBC,
 162
 163         NvRegPhyInterface = 0xC0,
 164 #define PHY_RGMII               0x10000000
 165
 166         NvRegTxRingPhysAddr = 0x100,
 167         NvRegRxRingPhysAddr = 0x104,
 168         NvRegRingSizes = 0x108,
 169 #define NVREG_RINGSZ_TXSHIFT 0
 170 #define NVREG_RINGSZ_RXSHIFT 16
 171         NvRegUnknownTransmitterReg = 0x10c,
 172         NvRegLinkSpeed = 0x110,
 173 #define NVREG_LINKSPEED_FORCE 0x10000
 174 #define NVREG_LINKSPEED_10      1000
 175 #define NVREG_LINKSPEED_100     100
 176 #define NVREG_LINKSPEED_1000    50
 177         NvRegUnknownSetupReg5 = 0x130,
 178 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 179         NvRegUnknownSetupReg3 = 0x13c,
 180 #define NVREG_UNKSETUP3_VAL1    0x200010
 181         NvRegTxRxControl = 0x144,
 182 #define NVREG_TXRXCTL_KICK      0x0001
 183 #define NVREG_TXRXCTL_BIT1      0x0002
 184 #define NVREG_TXRXCTL_BIT2      0x0004
 185 #define NVREG_TXRXCTL_IDLE      0x0008
 186 #define NVREG_TXRXCTL_RESET     0x0010
 187 #define NVREG_TXRXCTL_RXCHECK   0x0400
 188         NvRegMIIStatus = 0x180,
 189 #define NVREG_MIISTAT_ERROR             0x0001
 190 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 191 #define NVREG_MIISTAT_MASK              0x000f
 192 #define NVREG_MIISTAT_MASK2             0x000f
 193         NvRegUnknownSetupReg4 = 0x184,
 194 #define NVREG_UNKSETUP4_VAL     8
 195
 196         NvRegAdapterControl = 0x188,
 197 #define NVREG_ADAPTCTL_START    0x02
 198 #define NVREG_ADAPTCTL_LINKUP   0x04
 199 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 200 #define NVREG_ADAPTCTL_RUNNING  0x100000
 201 #define NVREG_ADAPTCTL_PHYSHIFT 24
 202         NvRegMIISpeed = 0x18c,
 203 #define NVREG_MIISPEED_BIT8     (1<<8)
 204 #define NVREG_MIIDELAY  5
 205         NvRegMIIControl = 0x190,
 206 #define NVREG_MIICTL_INUSE      0x08000
 207 #define NVREG_MIICTL_WRITE      0x00400
 208 #define NVREG_MIICTL_ADDRSHIFT  5
 209         NvRegMIIData = 0x194,
 210         NvRegWakeUpFlags = 0x200,
 211 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 212 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 213 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 214 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 215 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 216 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 217 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 218 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 219 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 220 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 221 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 222
 223         NvRegPatternCRC = 0x204,
 224         NvRegPatternMask = 0x208,
 225         NvRegPowerCap = 0x268,
 226 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 227 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 228 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 229         NvRegPowerState = 0x26c,
 230 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 231 #define NVREG_POWERSTATE_VALID          0x0100
 232 #define NVREG_POWERSTATE_MASK           0x0003
 233 #define NVREG_POWERSTATE_D0             0x0000
 234 #define NVREG_POWERSTATE_D1             0x0001
 235 #define NVREG_POWERSTATE_D2             0x0002
 236 #define NVREG_POWERSTATE_D3             0x0003
 237 };
 238
 239 #define FLAG_MASK_V1 0xffff0000
 240 #define FLAG_MASK_V2 0xffffc000
 241 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 242 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 243
 244 #define NV_TX_LASTPACKET        (1<<16)
 245 #define NV_TX_RETRYERROR        (1<<19)
 246 #define NV_TX_LASTPACKET1       (1<<24)
 247 #define NV_TX_DEFERRED          (1<<26)
 248 #define NV_TX_CARRIERLOST       (1<<27)
 249 #define NV_TX_LATECOLLISION     (1<<28)
 250 #define NV_TX_UNDERFLOW         (1<<29)
 251 #define NV_TX_ERROR             (1<<30)
 252 #define NV_TX_VALID             (1<<31)
 253
 254 #define NV_TX2_LASTPACKET       (1<<29)
 255 #define NV_TX2_RETRYERROR       (1<<18)
 256 #define NV_TX2_LASTPACKET1      (1<<23)
 257 #define NV_TX2_DEFERRED         (1<<25)
 258 #define NV_TX2_CARRIERLOST      (1<<26)
 259 #define NV_TX2_LATECOLLISION    (1<<27)
 260 #define NV_TX2_UNDERFLOW        (1<<28)
 261 /* error and valid are the same for both */
 262 #define NV_TX2_ERROR            (1<<30)
 263 #define NV_TX2_VALID            (1<<31)
 264
 265 #define NV_RX_DESCRIPTORVALID   (1<<16)
 266 #define NV_RX_MISSEDFRAME       (1<<17)
 267 #define NV_RX_SUBSTRACT1        (1<<18)
 268 #define NV_RX_ERROR1            (1<<23)
 269 #define NV_RX_ERROR2            (1<<24)
 270 #define NV_RX_ERROR3            (1<<25)
 271 #define NV_RX_ERROR4            (1<<26)
 272 #define NV_RX_CRCERR            (1<<27)
 273 #define NV_RX_OVERFLOW          (1<<28)
 274 #define NV_RX_FRAMINGERR        (1<<29)
 275 #define NV_RX_ERROR             (1<<30)
 276 #define NV_RX_AVAIL             (1<<31)
 277
 278 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 279 #define NV_RX2_CHECKSUMOK1      (0x10000000)
 280 #define NV_RX2_CHECKSUMOK2      (0x14000000)
 281 #define NV_RX2_CHECKSUMOK3      (0x18000000)
 282 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 283 #define NV_RX2_SUBSTRACT1       (1<<25)
 284 #define NV_RX2_ERROR1           (1<<18)
 285 #define NV_RX2_ERROR2           (1<<19)
 286 #define NV_RX2_ERROR3           (1<<20)
 287 #define NV_RX2_ERROR4           (1<<21)
 288 #define NV_RX2_CRCERR           (1<<22)
 289 #define NV_RX2_OVERFLOW         (1<<23)
 290 #define NV_RX2_FRAMINGERR       (1<<24)
 291 /* error and avail are the same for both */
 292 #define NV_RX2_ERROR            (1<<30)
 293 #define NV_RX2_AVAIL            (1<<31)
 294
 295 /* Miscelaneous hardware related defines: */
 296 #define NV_PCI_REGSZ            0x270
 297
 298 /* various timeout delays: all in usec */
 299 #define NV_TXRX_RESET_DELAY     4
 300 #define NV_TXSTOP_DELAY1        10
 301 #define NV_TXSTOP_DELAY1MAX     500000
 302 #define NV_TXSTOP_DELAY2        100
 303 #define NV_RXSTOP_DELAY1        10
 304 #define NV_RXSTOP_DELAY1MAX     500000
 305 #define NV_RXSTOP_DELAY2        100
 306 #define NV_SETUP5_DELAY         5
 307 #define NV_SETUP5_DELAYMAX      50000
 308 #define NV_POWERUP_DELAY        5
 309 #define NV_POWERUP_DELAYMAX     5000
 310 #define NV_MIIBUSY_DELAY        50
 311 #define NV_MIIPHY_DELAY 10
 312 #define NV_MIIPHY_DELAYMAX      10000
 313
 314 #define NV_WAKEUPPATTERNS       5
 315 #define NV_WAKEUPMASKENTRIES    4
 316
 317 /* General driver defaults */
 318 #define NV_WATCHDOG_TIMEO       (5*HZ)
 319
 320 #define RX_RING         4
 321 #define TX_RING         2
 322
 323 /*
 324  * If your nic mysteriously hangs then try to reduce the limits
 325  * to 1/0: It might be required to set NV_TX_LASTPACKET in the
 326  * last valid ring entry. But this would be impossible to
 327  * implement - probably a disassembly error.
 328  */
 329 #define TX_LIMIT_STOP   63
 330 #define TX_LIMIT_START  62
 331
 332 /* rx/tx mac addr + type + vlan + align + slack*/
 333 #define RX_NIC_BUFSIZE          (ETH_DATA_LEN + 64)
 334 /* even more slack */
 335 #define RX_ALLOC_BUFSIZE        (ETH_DATA_LEN + 128)
 336
 337 #define OOM_REFILL      (1+HZ/20)
 338 #define POLL_WAIT       (1+HZ/100)
 339 #define LINK_TIMEOUT    (3*HZ)
 340
 341 /*
 342  * desc_ver values:
 343  * This field has two purposes:
 344  * - Newer nics uses a different ring layout. The layout is selected by
 345  *   comparing np->desc_ver with DESC_VER_xy.
 346  * - It contains bits that are forced on when writing to NvRegTxRxControl.
 347  */
 348 #define DESC_VER_1      0x0
 349 #define DESC_VER_2      (0x02100|NVREG_TXRXCTL_RXCHECK)
 350
 351 /* PHY defines */
 352 #define PHY_OUI_MARVELL 0x5043
 353 #define PHY_OUI_CICADA  0x03f1
 354 #define PHYID1_OUI_MASK 0x03ff
 355 #define PHYID1_OUI_SHFT 6
 356 #define PHYID2_OUI_MASK 0xfc00
 357 #define PHYID2_OUI_SHFT 10
 358 #define PHY_INIT1       0x0f000
 359 #define PHY_INIT2       0x0e00
 360 #define PHY_INIT3       0x01000
 361 #define PHY_INIT4       0x0200
 362 #define PHY_INIT5       0x0004
 363 #define PHY_INIT6       0x02000
 364 #define PHY_GIGABIT     0x0100
 365
 366 #define PHY_TIMEOUT     0x1
 367 #define PHY_ERROR       0x2
 368
 369 #define PHY_100 0x1
 370 #define PHY_1000        0x2
 371 #define PHY_HALF        0x100
 372
 373 /* FIXME: MII defines that should be added to <linux/mii.h> */
 374 #define MII_1000BT_CR   0x09
 375 #define MII_1000BT_SR   0x0a
 376 #define ADVERTISE_1000FULL      0x0200
 377 #define ADVERTISE_1000HALF      0x0100
 378 #define LPA_1000FULL    0x0800
 379 #define LPA_1000HALF    0x0400
 380
 381 /* Big endian: should work, but is untested */
 382 struct ring_desc {
 383         u32 PacketBuffer;
 384         u32 FlagLen;
 385 };
 386
 387
 388 /* Define the TX and RX Descriptor and Buffers */
 389 struct {
 390         struct ring_desc tx_ring[TX_RING];
 391         unsigned char txb[TX_RING * RX_NIC_BUFSIZE];
 392         struct ring_desc rx_ring[RX_RING];
 393         unsigned char rxb[RX_RING * RX_NIC_BUFSIZE];
 394 } forcedeth_bufs __shared;
 395 #define tx_ring forcedeth_bufs.tx_ring
 396 #define rx_ring forcedeth_bufs.rx_ring
 397 #define txb forcedeth_bufs.txb
 398 #define rxb forcedeth_bufs.rxb
 399
 400 /* Private Storage for the NIC */
 401 static struct forcedeth_private {
 402         /* General data:
 403          * Locking: spin_lock(&np->lock); */
 404         int in_shutdown;
 405         u32 linkspeed;
 406         int duplex;
 407         int phyaddr;
 408         int wolenabled;
 409         unsigned int phy_oui;
 410         u16 gigabit;
 411
 412         /* General data: RO fields */
 413         u8 *ring_addr;
 414         u32 orig_mac[2];
 415         u32 irqmask;
 416         u32 desc_ver;
 417         /* rx specific fields.
 418          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 419          */
 420         unsigned int cur_rx, refill_rx;
 421
 422         /*
 423          * tx specific fields.
 424          */
 425         unsigned int next_tx, nic_tx;
 426         u32 tx_flags;
 427 } npx;
 428
 429 static struct forcedeth_private *np;
 430
 431 static inline void pci_push(u8 * base)
 432 {
 433         /* force out pending posted writes */
 434         readl(base);
 435 }
 436
 437 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 438 {
 439         return le32_to_cpu(prd->FlagLen)
 440             & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 441 }
 442
 443 static int reg_delay(int offset, u32 mask,
 444                      u32 target, int delay, int delaymax, const char *msg)
 445 {
 446         u8 *base = (u8 *) BASE;
 447
 448         pci_push(base);
 449         do {
 450                 udelay(delay);
 451                 delaymax -= delay;
 452                 if (delaymax < 0) {
 453                         if (msg)
 454                                 printf(msg);
 455                         return 1;
 456                 }
 457         } while ((readl(base + offset) & mask) != target);
 458         return 0;
 459 }
 460
 461 #define MII_READ        (-1)
 462 #define MII_PHYSID1         0x02        /* PHYS ID 1                   */
 463 #define MII_PHYSID2         0x03        /* PHYS ID 2                   */
 464 #define MII_BMCR            0x00        /* Basic mode control register */
 465 #define MII_BMSR            0x01        /* Basic mode status register  */
 466 #define MII_ADVERTISE       0x04        /* Advertisement control reg   */
 467 #define MII_LPA             0x05        /* Link partner ability reg    */
 468
 469 #define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
 470
 471 /* Link partner ability register. */
 472 #define LPA_SLCT                0x001f  /* Same as advertise selector  */
 473 #define LPA_10HALF              0x0020  /* Can do 10mbps half-duplex   */
 474 #define LPA_10FULL              0x0040  /* Can do 10mbps full-duplex   */
 475 #define LPA_100HALF             0x0080  /* Can do 100mbps half-duplex  */
 476 #define LPA_100FULL             0x0100  /* Can do 100mbps full-duplex  */
 477 #define LPA_100BASE4            0x0200  /* Can do 100mbps 4k packets   */
 478 #define LPA_RESV                0x1c00  /* Unused...                   */
 479 #define LPA_RFAULT              0x2000  /* Link partner faulted        */
 480 #define LPA_LPACK               0x4000  /* Link partner acked us       */
 481 #define LPA_NPAGE               0x8000  /* Next page bit               */
 482
 483 /* mii_rw: read/write a register on the PHY.
 484  *
 485  * Caller must guarantee serialization
 486  */
 487 static int mii_rw(struct nic *nic __unused, int addr, int miireg,
 488                   int value)
 489 {
 490         u8 *base = (u8 *) BASE;
 491         u32 reg;
 492         int retval;
 493
 494         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
 495
 496         reg = readl(base + NvRegMIIControl);
 497         if (reg & NVREG_MIICTL_INUSE) {
 498                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
 499                 udelay(NV_MIIBUSY_DELAY);
 500         }
 501
 502         reg =
 503             (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
 504         if (value != MII_READ) {
 505                 writel(value, base + NvRegMIIData);
 506                 reg |= NVREG_MIICTL_WRITE;
 507         }
 508         writel(reg, base + NvRegMIIControl);
 509
 510         if (reg_delay(NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
 511                       NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
 512                 dprintf(("mii_rw of reg %d at PHY %d timed out.\n",
 513                          miireg, addr));
 514                 retval = -1;
 515         } else if (value != MII_READ) {
 516                 /* it was a write operation - fewer failures are detectable */
 517                 dprintf(("mii_rw wrote 0x%x to reg %d at PHY %d\n",
 518                          value, miireg, addr));
 519                 retval = 0;
 520         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
 521                 dprintf(("mii_rw of reg %d at PHY %d failed.\n",
 522                          miireg, addr));
 523                 retval = -1;
 524         } else {
 525                 retval = readl(base + NvRegMIIData);
 526                 dprintf(("mii_rw read from reg %d at PHY %d: 0x%x.\n",
 527                          miireg, addr, retval));
 528         }
 529         return retval;
 530 }
 531
 532 static int phy_reset(struct nic *nic)
 533 {
 534
 535         u32 miicontrol;
 536         unsigned int tries = 0;
 537
 538         miicontrol = mii_rw(nic, np->phyaddr, MII_BMCR, MII_READ);
 539         miicontrol |= BMCR_RESET;
 540         if (mii_rw(nic, np->phyaddr, MII_BMCR, miicontrol)) {
 541                 return -1;
 542         }
 543
 544         /* wait for 500ms */
 545         mdelay(500);
 546
 547         /* must wait till reset is deasserted */
 548         while (miicontrol & BMCR_RESET) {
 549                 mdelay(10);
 550                 miicontrol = mii_rw(nic, np->phyaddr, MII_BMCR, MII_READ);
 551                 /* FIXME: 100 tries seem excessive */
 552                 if (tries++ > 100)
 553                         return -1;
 554         }
 555         return 0;
 556 }
 557
 558 static int phy_init(struct nic *nic)
 559 {
 560         u8 *base = (u8 *) BASE;
 561         u32 phyinterface, phy_reserved, mii_status, mii_control,
 562             mii_control_1000, reg;
 563
 564         /* set advertise register */
 565         reg = mii_rw(nic, np->phyaddr, MII_ADVERTISE, MII_READ);
 566         reg |=
 567             (ADVERTISE_10HALF | ADVERTISE_10FULL | ADVERTISE_100HALF |
 568              ADVERTISE_100FULL | 0x800 | 0x400);
 569         if (mii_rw(nic, np->phyaddr, MII_ADVERTISE, reg)) {
 570                 printf("phy write to advertise failed.\n");
 571                 return PHY_ERROR;
 572         }
 573
 574         /* get phy interface type */
 575         phyinterface = readl(base + NvRegPhyInterface);
 576
 577         /* see if gigabit phy */
 578         mii_status = mii_rw(nic, np->phyaddr, MII_BMSR, MII_READ);
 579
 580         if (mii_status & PHY_GIGABIT) {
 581                 np->gigabit = PHY_GIGABIT;
 582                 mii_control_1000 =
 583                     mii_rw(nic, np->phyaddr, MII_1000BT_CR, MII_READ);
 584                 mii_control_1000 &= ~ADVERTISE_1000HALF;
 585                 if (phyinterface & PHY_RGMII)
 586                         mii_control_1000 |= ADVERTISE_1000FULL;
 587                 else
 588                         mii_control_1000 &= ~ADVERTISE_1000FULL;
 589
 590                 if (mii_rw
 591                     (nic, np->phyaddr, MII_1000BT_CR, mii_control_1000)) {
 592                         printf("phy init failed.\n");
 593                         return PHY_ERROR;
 594                 }
 595         } else
 596                 np->gigabit = 0;
 597
 598         /* reset the phy */
 599         if (phy_reset(nic)) {
 600                 printf("phy reset failed\n");
 601                 return PHY_ERROR;
 602         }
 603
 604         /* phy vendor specific configuration */
 605         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII)) {
 606                 phy_reserved =
 607                     mii_rw(nic, np->phyaddr, MII_RESV1, MII_READ);
 608                 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
 609                 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
 610                 if (mii_rw(nic, np->phyaddr, MII_RESV1, phy_reserved)) {
 611                         printf("phy init failed.\n");
 612                         return PHY_ERROR;
 613                 }
 614                 phy_reserved =
 615                     mii_rw(nic, np->phyaddr, MII_NCONFIG, MII_READ);
 616                 phy_reserved |= PHY_INIT5;
 617                 if (mii_rw(nic, np->phyaddr, MII_NCONFIG, phy_reserved)) {
 618                         printf("phy init failed.\n");
 619                         return PHY_ERROR;
 620                 }
 621         }
 622         if (np->phy_oui == PHY_OUI_CICADA) {
 623                 phy_reserved =
 624                     mii_rw(nic, np->phyaddr, MII_SREVISION, MII_READ);
 625                 phy_reserved |= PHY_INIT6;
 626                 if (mii_rw(nic, np->phyaddr, MII_SREVISION, phy_reserved)) {
 627                         printf("phy init failed.\n");
 628                         return PHY_ERROR;
 629                 }
 630         }
 631
 632         /* restart auto negotiation */
 633         mii_control = mii_rw(nic, np->phyaddr, MII_BMCR, MII_READ);
 634         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
 635         if (mii_rw(nic, np->phyaddr, MII_BMCR, mii_control)) {
 636                 return PHY_ERROR;
 637         }
 638
 639         return 0;
 640 }
 641
 642 static void start_rx(struct nic *nic __unused)
 643 {
 644         u8 *base = (u8 *) BASE;
 645
 646         dprintf(("start_rx\n"));
 647         /* Already running? Stop it. */
 648         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
 649                 writel(0, base + NvRegReceiverControl);
 650                 pci_push(base);
 651         }
 652         writel(np->linkspeed, base + NvRegLinkSpeed);
 653         pci_push(base);
 654         writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
 655         pci_push(base);
 656 }
 657
 658 static void stop_rx(void)
 659 {
 660         u8 *base = (u8 *) BASE;
 661
 662         dprintf(("stop_rx\n"));
 663         writel(0, base + NvRegReceiverControl);
 664         reg_delay(NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
 665                   NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
 666                   "stop_rx: ReceiverStatus remained busy");
 667
 668         udelay(NV_RXSTOP_DELAY2);
 669         writel(0, base + NvRegLinkSpeed);
 670 }
 671
 672 static void start_tx(struct nic *nic __unused)
 673 {
 674         u8 *base = (u8 *) BASE;
 675
 676         dprintf(("start_tx\n"));
 677         writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
 678         pci_push(base);
 679 }
 680
 681 static void stop_tx(void)
 682 {
 683         u8 *base = (u8 *) BASE;
 684
 685         dprintf(("stop_tx\n"));
 686         writel(0, base + NvRegTransmitterControl);
 687         reg_delay(NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
 688                   NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
 689                   "stop_tx: TransmitterStatus remained busy");
 690
 691         udelay(NV_TXSTOP_DELAY2);
 692         writel(0, base + NvRegUnknownTransmitterReg);
 693 }
 694
 695
 696 static void txrx_reset(struct nic *nic __unused)
 697 {
 698         u8 *base = (u8 *) BASE;
 699
 700         dprintf(("txrx_reset\n"));
 701         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->desc_ver,
 702                base + NvRegTxRxControl);
 703
 704         pci_push(base);
 705         udelay(NV_TXRX_RESET_DELAY);
 706         writel(NVREG_TXRXCTL_BIT2 | np->desc_ver, base + NvRegTxRxControl);
 707         pci_push(base);
 708 }
 709
 710 /*
 711  * alloc_rx: fill rx ring entries.
 712  * Return 1 if the allocations for the skbs failed and the
 713  * rx engine is without Available descriptors
 714  */
 715 static int alloc_rx(struct nic *nic __unused)
 716 {
 717         unsigned int refill_rx = np->refill_rx;
 718         int i;
 719         //while (np->cur_rx != refill_rx) {
 720         for (i = 0; i < RX_RING; i++) {
 721                 //int nr = refill_rx % RX_RING;
 722                 rx_ring[i].PacketBuffer =
 723                     virt_to_le32desc(&rxb[i * RX_NIC_BUFSIZE]);
 724                 wmb();
 725                 rx_ring[i].FlagLen =
 726                     cpu_to_le32(RX_NIC_BUFSIZE | NV_RX_AVAIL);
 727                 /*      printf("alloc_rx: Packet  %d marked as Available\n",
 728                    refill_rx); */
 729                 refill_rx++;
 730         }
 731         np->refill_rx = refill_rx;
 732         if (np->cur_rx - refill_rx == RX_RING)
 733                 return 1;
 734         return 0;
 735 }
 736
 737 static int update_linkspeed(struct nic *nic)
 738 {
 739         int adv, lpa;
 740         u32 newls;
 741         int newdup = np->duplex;
 742         u32 mii_status;
 743         int retval = 0;
 744         u32 control_1000, status_1000, phyreg;
 745         u8 *base = (u8 *) BASE;
 746         int i;
 747
 748         /* BMSR_LSTATUS is latched, read it twice:
 749          * we want the current value.
 750          */
 751         mii_rw(nic, np->phyaddr, MII_BMSR, MII_READ);
 752         mii_status = mii_rw(nic, np->phyaddr, MII_BMSR, MII_READ);
 753
 754 #if 1
 755         //yhlu
 756         for(i=0;i<30;i++) {
 757                 mii_status = mii_rw(nic, np->phyaddr, MII_BMSR, MII_READ);
 758                 if((mii_status & BMSR_LSTATUS) && (mii_status & BMSR_ANEGCOMPLETE)) break;
 759                 mdelay(100);
 760         }
 761 #endif
 762
 763         if (!(mii_status & BMSR_LSTATUS)) {
 764                 printf
 765                     ("no link detected by phy - falling back to 10HD.\n");
 766                 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
 767                 newdup = 0;
 768                 retval = 0;
 769                 goto set_speed;
 770         }
 771
 772         /* check auto negotiation is complete */
 773         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
 774                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
 775                 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
 776                 newdup = 0;
 777                 retval = 0;
 778                 printf("autoneg not completed - falling back to 10HD.\n");
 779                 goto set_speed;
 780         }
 781
 782         retval = 1;
 783         if (np->gigabit == PHY_GIGABIT) {
 784                 control_1000 =
 785                     mii_rw(nic, np->phyaddr, MII_1000BT_CR, MII_READ);
 786                 status_1000 =
 787                     mii_rw(nic, np->phyaddr, MII_1000BT_SR, MII_READ);
 788
 789                 if ((control_1000 & ADVERTISE_1000FULL) &&
 790                     (status_1000 & LPA_1000FULL)) {
 791                         printf
 792                             ("update_linkspeed: GBit ethernet detected.\n");
 793                         newls =
 794                             NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_1000;
 795                         newdup = 1;
 796                         goto set_speed;
 797                 }
 798         }
 799
 800         adv = mii_rw(nic, np->phyaddr, MII_ADVERTISE, MII_READ);
 801         lpa = mii_rw(nic, np->phyaddr, MII_LPA, MII_READ);
 802         dprintf(("update_linkspeed: PHY advertises 0x%hX, lpa 0x%hX.\n",
 803                  adv, lpa));
 804
 805         /* FIXME: handle parallel detection properly, handle gigabit ethernet */
 806         lpa = lpa & adv;
 807         if (lpa & LPA_100FULL) {
 808                 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_100;
 809                 newdup = 1;
 810         } else if (lpa & LPA_100HALF) {
 811                 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_100;
 812                 newdup = 0;
 813         } else if (lpa & LPA_10FULL) {
 814                 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
 815                 newdup = 1;
 816         } else if (lpa & LPA_10HALF) {
 817                 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
 818                 newdup = 0;
 819         } else {
 820                 printf("bad ability %hX - falling back to 10HD.\n", lpa);
 821                 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
 822                 newdup = 0;
 823         }
 824
 825       set_speed:
 826         if (np->duplex == newdup && np->linkspeed == newls)
 827                 return retval;
 828
 829         dprintf(("changing link setting from %d/%s to %d/%s.\n",
 830                np->linkspeed, np->duplex ? "Full-Duplex": "Half-Duplex", newls, newdup ? "Full-Duplex": "Half-Duplex"));
 831
 832         np->duplex = newdup;
 833         np->linkspeed = newls;
 834
 835         if (np->gigabit == PHY_GIGABIT) {
 836                 phyreg = readl(base + NvRegRandomSeed);
 837                 phyreg &= ~(0x3FF00);
 838                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
 839                         phyreg |= NVREG_RNDSEED_FORCE3;
 840                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
 841                         phyreg |= NVREG_RNDSEED_FORCE2;
 842                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
 843                         phyreg |= NVREG_RNDSEED_FORCE;
 844                 writel(phyreg, base + NvRegRandomSeed);
 845         }
 846
 847         phyreg = readl(base + NvRegPhyInterface);
 848         phyreg &= ~(PHY_HALF | PHY_100 | PHY_1000);
 849         if (np->duplex == 0)
 850                 phyreg |= PHY_HALF;
 851         if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
 852                 phyreg |= PHY_100;
 853         else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
 854                 phyreg |= PHY_1000;
 855         writel(phyreg, base + NvRegPhyInterface);
 856
 857         writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
 858                base + NvRegMisc1);
 859         pci_push(base);
 860         writel(np->linkspeed, base + NvRegLinkSpeed);
 861         pci_push(base);
 862
 863         return retval;
 864 }
 865
 866 #if 0 /* Not used */
 867 static void nv_linkchange(struct nic *nic)
 868 {
 869         if (update_linkspeed(nic)) {
 870 //                if (netif_carrier_ok(nic)) {
 871                 stop_rx();
 872 //=                } else {
 873                 //                      netif_carrier_on(dev);
 874                 //                    printk(KERN_INFO "%s: link up.\n", dev->name);
 875                 //          }
 876                 start_rx(nic);
 877         } else {
 878                 //        if (netif_carrier_ok(dev)) {
 879                 //              netif_carrier_off(dev);
 880                 //            printk(KERN_INFO "%s: link down.\n", dev->name);
 881                 stop_rx();
 882                 //  }
 883         }
 884 }
 885 #endif
 886
 887 static int init_ring(struct nic *nic)
 888 {
 889         int i;
 890
 891         np->next_tx = np->nic_tx = 0;
 892         for (i = 0; i < TX_RING; i++)
 893                 tx_ring[i].FlagLen = 0;
 894
 895         np->cur_rx = 0;
 896         np->refill_rx = 0;
 897         for (i = 0; i < RX_RING; i++)
 898                 rx_ring[i].FlagLen = 0;
 899         return alloc_rx(nic);
 900 }
 901
 902 static void set_multicast(struct nic *nic)
 903 {
 904
 905         u8 *base = (u8 *) BASE;
 906         u32 addr[2];
 907         u32 mask[2];
 908         u32 pff;
 909         u32 alwaysOff[2];
 910         u32 alwaysOn[2];
 911
 912         memset(addr, 0, sizeof(addr));
 913         memset(mask, 0, sizeof(mask));
 914
 915         pff = NVREG_PFF_MYADDR;
 916
 917         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
 918
 919         addr[0] = alwaysOn[0];
 920         addr[1] = alwaysOn[1];
 921         mask[0] = alwaysOn[0] | alwaysOff[0];
 922         mask[1] = alwaysOn[1] | alwaysOff[1];
 923
 924         addr[0] |= NVREG_MCASTADDRA_FORCE;
 925         pff |= NVREG_PFF_ALWAYS;
 926         stop_rx();
 927         writel(addr[0], base + NvRegMulticastAddrA);
 928         writel(addr[1], base + NvRegMulticastAddrB);
 929         writel(mask[0], base + NvRegMulticastMaskA);
 930         writel(mask[1], base + NvRegMulticastMaskB);
 931         writel(pff, base + NvRegPacketFilterFlags);
 932         start_rx(nic);
 933 }
 934
 935 /**************************************************************************
 936 RESET - Reset the NIC to prepare for use
 937 ***************************************************************************/
 938 static int forcedeth_reset(struct nic *nic)
 939 {
 940         u8 *base = (u8 *) BASE;
 941         int ret, oom, i;
 942         ret = 0;
 943         dprintf(("forcedeth: open\n"));
 944
 945         /* 1) erase previous misconfiguration */
 946         /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
 947         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
 948         writel(0, base + NvRegMulticastAddrB);
 949         writel(0, base + NvRegMulticastMaskA);
 950         writel(0, base + NvRegMulticastMaskB);
 951         writel(0, base + NvRegPacketFilterFlags);
 952
 953         writel(0, base + NvRegTransmitterControl);
 954         writel(0, base + NvRegReceiverControl);
 955
 956         writel(0, base + NvRegAdapterControl);
 957
 958         /* 2) initialize descriptor rings */
 959         oom = init_ring(nic);
 960
 961         writel(0, base + NvRegLinkSpeed);
 962         writel(0, base + NvRegUnknownTransmitterReg);
 963         txrx_reset(nic);
 964         writel(0, base + NvRegUnknownSetupReg6);
 965
 966         np->in_shutdown = 0;
 967
 968         /* 3) set mac address */
 969         {
 970                 u32 mac[2];
 971
 972                 mac[0] =
 973                     (nic->node_addr[0] << 0) + (nic->node_addr[1] << 8) +
 974                     (nic->node_addr[2] << 16) + (nic->node_addr[3] << 24);
 975                 mac[1] =
 976                     (nic->node_addr[4] << 0) + (nic->node_addr[5] << 8);
 977
 978                 writel(mac[0], base + NvRegMacAddrA);
 979                 writel(mac[1], base + NvRegMacAddrB);
 980         }
 981
 982         /* 4) give hw rings */
 983         writel((u32) virt_to_le32desc(&rx_ring[0]),
 984                base + NvRegRxRingPhysAddr);
 985         writel((u32) virt_to_le32desc(&tx_ring[0]),
 986                base + NvRegTxRingPhysAddr);
 987
 988         writel(((RX_RING - 1) << NVREG_RINGSZ_RXSHIFT) +
 989                ((TX_RING - 1) << NVREG_RINGSZ_TXSHIFT),
 990                base + NvRegRingSizes);
 991
 992         /* 5) continue setup */
 993         np->linkspeed = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
 994         np->duplex = 0;
 995         writel(np->linkspeed, base + NvRegLinkSpeed);
 996         writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
 997         writel(np->desc_ver, base + NvRegTxRxControl);
 998         pci_push(base);
 999         writel(NVREG_TXRXCTL_BIT1 | np->desc_ver, base + NvRegTxRxControl);
1000         reg_delay(NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31,
1001                   NVREG_UNKSETUP5_BIT31, NV_SETUP5_DELAY,
1002                   NV_SETUP5_DELAYMAX,
1003                   "open: SetupReg5, Bit 31 remained off\n");
1004
1005         writel(0, base + NvRegUnknownSetupReg4);
1006 //       writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1007         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
1008 #if 0
1009         printf("%d-Mbs Link, %s-Duplex\n",
1010                np->linkspeed & NVREG_LINKSPEED_10 ? 10 : 100,
1011                np->duplex ? "Full" : "Half");
1012 #endif
1013
1014         /* 6) continue setup */
1015         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
1016         writel(readl(base + NvRegTransmitterStatus),
1017                base + NvRegTransmitterStatus);
1018         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
1019         writel(NVREG_OFFLOAD_NORMAL, base + NvRegOffloadConfig);
1020
1021         writel(readl(base + NvRegReceiverStatus),
1022                base + NvRegReceiverStatus);
1023
1024         /* Get a random number */
1025         i = random();
1026         writel(NVREG_RNDSEED_FORCE | (i & NVREG_RNDSEED_MASK),
1027                base + NvRegRandomSeed);
1028         writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
1029         writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
1030         writel(NVREG_POLL_DEFAULT, base + NvRegPollingInterval);
1031         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
1032         writel((np->
1033                 phyaddr << NVREG_ADAPTCTL_PHYSHIFT) |
1034                NVREG_ADAPTCTL_PHYVALID | NVREG_ADAPTCTL_RUNNING,
1035                base + NvRegAdapterControl);
1036         writel(NVREG_MIISPEED_BIT8 | NVREG_MIIDELAY, base + NvRegMIISpeed);
1037         writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
1038         writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
1039
1040         i = readl(base + NvRegPowerState);
1041         if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
1042                 writel(NVREG_POWERSTATE_POWEREDUP | i,
1043                        base + NvRegPowerState);
1044
1045         pci_push(base);
1046         udelay(10);
1047         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID,
1048                base + NvRegPowerState);
1049
1050         writel(0, base + NvRegIrqMask);
1051         pci_push(base);
1052         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
1053         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1054         pci_push(base);
1055 /*
1056         writel(np->irqmask, base + NvRegIrqMask);
1057 */
1058         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
1059         writel(0, base + NvRegMulticastAddrB);
1060         writel(0, base + NvRegMulticastMaskA);
1061         writel(0, base + NvRegMulticastMaskB);
1062         writel(NVREG_PFF_ALWAYS | NVREG_PFF_MYADDR,
1063                base + NvRegPacketFilterFlags);
1064
1065         set_multicast(nic);
1066         /* One manual link speed update: Interrupts are enabled, future link
1067          * speed changes cause interrupts and are handled by nv_link_irq().
1068          */
1069         {
1070                 u32 miistat;
1071                 miistat = readl(base + NvRegMIIStatus);
1072                 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1073                 dprintf(("startup: got 0x%hX.\n", miistat));
1074         }
1075         ret = update_linkspeed(nic);
1076
1077         //start_rx(nic);
1078         start_tx(nic);
1079
1080         if (ret) {
1081                 //Start Connection netif_carrier_on(dev);
1082         } else {
1083                 printf("no link during initialization.\n");
1084         }
1085
1086         return ret;
1087 }
1088
1089 /*
1090  * extern void hex_dump(const char *data, const unsigned int len);
1091 */
1092 /**************************************************************************
1093 POLL - Wait for a frame
1094 ***************************************************************************/
1095 static int forcedeth_poll(struct nic *nic, int retrieve)
1096 {
1097         /* return true if there's an ethernet packet ready to read */
1098         /* nic->packet should contain data on return */
1099         /* nic->packetlen should contain length of data */
1100
1101         int len;
1102         int i;
1103         u32 Flags;
1104
1105         i = np->cur_rx % RX_RING;
1106
1107         Flags = le32_to_cpu(rx_ring[i].FlagLen);
1108         len = nv_descr_getlength(&rx_ring[i], np->desc_ver);
1109
1110         if (Flags & NV_RX_AVAIL)
1111                 return 0;       /* still owned by hardware, */
1112
1113         if (np->desc_ver == DESC_VER_1) {
1114                 if (!(Flags & NV_RX_DESCRIPTORVALID))
1115                         return 0;
1116         } else {
1117                 if (!(Flags & NV_RX2_DESCRIPTORVALID))
1118                         return 0;
1119         }
1120
1121         if (!retrieve)
1122                 return 1;
1123
1124         /* got a valid packet - forward it to the network core */
1125         nic->packetlen = len;
1126         memcpy(nic->packet, rxb + (i * RX_NIC_BUFSIZE), nic->packetlen);
1127 /*
1128  *      hex_dump(rxb + (i * RX_NIC_BUFSIZE), len);
1129 */
1130         wmb();
1131         np->cur_rx++;
1132         alloc_rx(nic);
1133         return 1;
1134 }
1135
1136
1137 /**************************************************************************
1138 TRANSMIT - Transmit a frame
1139 ***************************************************************************/
1140 static void forcedeth_transmit(struct nic *nic, const char *d,  /* Destination */
1141                                unsigned int t,  /* Type */
1142                                unsigned int s,  /* size */
1143                                const char *p)
1144 {                               /* Packet */
1145         /* send the packet to destination */
1146         u8 *ptxb;
1147         u16 nstype;
1148         u8 *base = (u8 *) BASE;
1149         int nr = np->next_tx % TX_RING;
1150
1151         /* point to the current txb incase multiple tx_rings are used */
1152         ptxb = txb + (nr * RX_NIC_BUFSIZE);
1153         //np->tx_skbuff[nr] = ptxb;
1154
1155         /* copy the packet to ring buffer */
1156         memcpy(ptxb, d, ETH_ALEN);      /* dst */
1157         memcpy(ptxb + ETH_ALEN, nic->node_addr, ETH_ALEN);      /* src */
1158         nstype = htons((u16) t);        /* type */
1159         memcpy(ptxb + 2 * ETH_ALEN, (u8 *) & nstype, 2);        /* type */
1160         memcpy(ptxb + ETH_HLEN, p, s);
1161
1162         s += ETH_HLEN;
1163         while (s < ETH_ZLEN)    /* pad to min length */
1164                 ptxb[s++] = '\0';
1165
1166         tx_ring[nr].PacketBuffer = (u32) virt_to_le32desc(ptxb);
1167
1168         wmb();
1169         tx_ring[nr].FlagLen = cpu_to_le32((s - 1) | np->tx_flags);
1170
1171         writel(NVREG_TXRXCTL_KICK | np->desc_ver, base + NvRegTxRxControl);
1172         pci_push(base);
1173         np->next_tx++;
1174 }
1175
1176 /**************************************************************************
1177 DISABLE - Turn off ethernet interface
1178 ***************************************************************************/
1179 static void forcedeth_disable ( struct nic *nic __unused ) {
1180         /* put the card in its initial state */
1181         /* This function serves 3 purposes.
1182          * This disables DMA and interrupts so we don't receive
1183          *  unexpected packets or interrupts from the card after
1184          *  etherboot has finished.
1185          * This frees resources so etherboot may use
1186          *  this driver on another interface
1187          * This allows etherboot to reinitialize the interface
1188          *  if something is something goes wrong.
1189          */
1190         u8 *base = (u8 *) BASE;
1191         np->in_shutdown = 1;
1192         stop_tx();
1193         stop_rx();
1194
1195         /* disable interrupts on the nic or we will lock up */
1196         writel(0, base + NvRegIrqMask);
1197         pci_push(base);
1198         dprintf(("Irqmask is zero again\n"));
1199
1200         /* specia op:o write back the misordered MAC address - otherwise
1201          * the next probe_nic would see a wrong address.
1202          */
1203         writel(np->orig_mac[0], base + NvRegMacAddrA);
1204         writel(np->orig_mac[1], base + NvRegMacAddrB);
1205 }
1206
1207 /**************************************************************************
1208 IRQ - Enable, Disable, or Force interrupts
1209 ***************************************************************************/
1210 static void forcedeth_irq(struct nic *nic __unused,
1211                           irq_action_t action __unused)
1212 {
1213         switch (action) {
1214         case DISABLE:
1215                 break;
1216         case ENABLE:
1217                 break;
1218         case FORCE:
1219                 break;
1220         }
1221 }
1222
1223 static struct nic_operations forcedeth_operations = {
1224         .connect        = dummy_connect,
1225         .poll           = forcedeth_poll,
1226         .transmit       = forcedeth_transmit,
1227         .irq            = forcedeth_irq,
1228
1229 };
1230
1231 /**************************************************************************
1232 PROBE - Look for an adapter, this routine's visible to the outside
1233 ***************************************************************************/
1234 #define IORESOURCE_MEM 0x00000200
1235 #define board_found 1
1236 #define valid_link 0
1237 static int forcedeth_probe ( struct nic *nic, struct pci_device *pci ) {
1238
1239         unsigned long addr;
1240         int sz;
1241         u8 *base;
1242         int i;
1243
1244         if (pci->ioaddr == 0)
1245                 return 0;
1246
1247         printf("forcedeth.c: Found %s, vendor=0x%hX, device=0x%hX\n",
1248                pci->driver_name, pci->vendor, pci->device);
1249
1250         nic->ioaddr = pci->ioaddr;
1251         nic->irqno = 0;
1252
1253         /* point to private storage */
1254         np = &npx;
1255
1256         adjust_pci_device(pci);
1257
1258         addr = pci_bar_start(pci, PCI_BASE_ADDRESS_0);
1259         sz = pci_bar_size(pci, PCI_BASE_ADDRESS_0);
1260
1261         /* BASE is used throughout to address the card */
1262         BASE = (unsigned long) ioremap(addr, sz);
1263         if (!BASE)
1264                 return 0;
1265
1266         /* handle different descriptor versions */
1267         if (pci->device == PCI_DEVICE_ID_NVIDIA_NVENET_1 ||
1268             pci->device == PCI_DEVICE_ID_NVIDIA_NVENET_2 ||
1269             pci->device == PCI_DEVICE_ID_NVIDIA_NVENET_3)
1270                 np->desc_ver = DESC_VER_1;
1271         else
1272                 np->desc_ver = DESC_VER_2;
1273
1274         //rx_ring[0] = rx_ring;
1275         //tx_ring[0] = tx_ring;
1276
1277         /* read the mac address */
1278         base = (u8 *) BASE;
1279         np->orig_mac[0] = readl(base + NvRegMacAddrA);
1280         np->orig_mac[1] = readl(base + NvRegMacAddrB);
1281
1282         nic->node_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
1283         nic->node_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
1284         nic->node_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
1285         nic->node_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
1286         nic->node_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
1287         nic->node_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
1288 #ifdef LINUX
1289         if (!is_valid_ether_addr(dev->dev_addr)) {
1290                 /*
1291                  * Bad mac address. At least one bios sets the mac address
1292                  * to 01:23:45:67:89:ab
1293                  */
1294                 printk(KERN_ERR
1295                        "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
1296                        pci_name(pci_dev), dev->dev_addr[0],
1297                        dev->dev_addr[1], dev->dev_addr[2],
1298                        dev->dev_addr[3], dev->dev_addr[4],
1299                        dev->dev_addr[5]);
1300                 printk(KERN_ERR
1301                        "Please complain to your hardware vendor. Switching to a random MAC.\n");
1302                 dev->dev_addr[0] = 0x00;
1303                 dev->dev_addr[1] = 0x00;
1304                 dev->dev_addr[2] = 0x6c;
1305                 get_random_bytes(&dev->dev_addr[3], 3);
1306         }
1307 #endif
1308
1309         DBG ( "%s: MAC Address %s\n", pci->driver_name, eth_ntoa ( nic->node_addr ) );
1310
1311         /* disable WOL */
1312         writel(0, base + NvRegWakeUpFlags);
1313         np->wolenabled = 0;
1314
1315         if (np->desc_ver == DESC_VER_1) {
1316                 np->tx_flags = NV_TX_LASTPACKET | NV_TX_VALID;
1317         } else {
1318                 np->tx_flags = NV_TX2_LASTPACKET | NV_TX2_VALID;
1319         }
1320
1321         switch (pci->device) {
1322         case 0x01C3:            // nforce
1323                 // DEV_IRQMASK_1|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
1324                 np->irqmask = NVREG_IRQMASK_WANTED_2 | NVREG_IRQ_TIMER;
1325                 //              np->need_linktimer = 1;
1326                 //              np->link_timeout = jiffies + LINK_TIMEOUT;
1327                 break;
1328         case 0x0066:
1329                 /* Fall Through */
1330         case 0x00D6:
1331                 // DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER
1332                 np->irqmask = NVREG_IRQMASK_WANTED_2;
1333                 np->irqmask |= NVREG_IRQ_TIMER;
1334                 //              np->need_linktimer = 1;
1335                 //              np->link_timeout = jiffies + LINK_TIMEOUT;
1336                 if (np->desc_ver == DESC_VER_1)
1337                         np->tx_flags |= NV_TX_LASTPACKET1;
1338                 else
1339                         np->tx_flags |= NV_TX2_LASTPACKET1;
1340                 break;
1341         case 0x0086:
1342                 /* Fall Through */
1343         case 0x008c:
1344                 /* Fall Through */
1345         case 0x00e6:
1346                 /* Fall Through */
1347         case 0x00df:
1348                 /* Fall Through */
1349         case 0x0056:
1350                 /* Fall Through */
1351         case 0x0057:
1352                 /* Fall Through */
1353         case 0x0037:
1354                 /* Fall Through */
1355         case 0x0038:
1356                 //DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ
1357                 np->irqmask = NVREG_IRQMASK_WANTED_2;
1358                 np->irqmask |= NVREG_IRQ_TIMER;
1359                 //              np->need_linktimer = 1;
1360                 //              np->link_timeout = jiffies + LINK_TIMEOUT;
1361                 if (np->desc_ver == DESC_VER_1)
1362                         np->tx_flags |= NV_TX_LASTPACKET1;
1363                 else
1364                         np->tx_flags |= NV_TX2_LASTPACKET1;
1365                 break;
1366         default:
1367                 printf
1368                         ("Your card was undefined in this driver.  Review driver_data in Linux driver and send a patch\n");
1369         }
1370
1371         /* find a suitable phy */
1372         for (i = 1; i < 32; i++) {
1373                 int id1, id2;
1374                 id1 = mii_rw(nic, i, MII_PHYSID1, MII_READ);
1375                 if (id1 < 0 || id1 == 0xffff)
1376                         continue;
1377                 id2 = mii_rw(nic, i, MII_PHYSID2, MII_READ);
1378                 if (id2 < 0 || id2 == 0xffff)
1379                         continue;
1380                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
1381                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
1382                 dprintf
1383                         (("%s: open: Found PHY %hX:%hX at address %d.\n",
1384                           pci->driver_name, id1, id2, i));
1385                 np->phyaddr = i;
1386                 np->phy_oui = id1 | id2;
1387                 break;
1388         }
1389         if (i == 32) {
1390                 /* PHY in isolate mode? No phy attached and user wants to
1391                  * test loopback? Very odd, but can be correct.
1392                  */
1393                 printf
1394                         ("%s: open: Could not find a valid PHY.\n", pci->driver_name);
1395         }
1396
1397         if (i != 32) {
1398                 /* reset it */
1399                 phy_init(nic);
1400         }
1401
1402         dprintf(("%s: forcedeth.c: subsystem: %hX:%hX bound to %s\n",
1403                  pci->driver_name, pci->vendor, pci->dev_id, pci->driver_name));
1404         if(!forcedeth_reset(nic)) return 0; // no valid link
1405
1406         /* point to NIC specific routines */
1407         nic->nic_op     = &forcedeth_operations;
1408         return 1;
1409 }
1410
1411 static struct pci_device_id forcedeth_nics[] = {
1412 PCI_ROM(0x10de, 0x01C3, "nforce", "nForce NVENET_1 Ethernet Controller"),
1413 PCI_ROM(0x10de, 0x0066, "nforce2", "nForce NVENET_2 Ethernet Controller"),
1414 PCI_ROM(0x10de, 0x00D6, "nforce3", "nForce NVENET_3 Ethernet Controller"),
1415 PCI_ROM(0x10de, 0x0086, "nforce4", "nForce NVENET_4 Ethernet Controller"),
1416 PCI_ROM(0x10de, 0x008c, "nforce5", "nForce NVENET_5 Ethernet Controller"),
1417 PCI_ROM(0x10de, 0x00e6, "nforce6", "nForce NVENET_6 Ethernet Controller"),
1418 PCI_ROM(0x10de, 0x00df, "nforce7", "nForce NVENET_7 Ethernet Controller"),
1419 PCI_ROM(0x10de, 0x0056, "nforce8", "nForce NVENET_8 Ethernet Controller"),
1420 PCI_ROM(0x10de, 0x0057, "nforce9", "nForce NVENET_9 Ethernet Controller"),
1421 PCI_ROM(0x10de, 0x0037, "nforce10", "nForce NVENET_10 Ethernet Controller"),
1422 PCI_ROM(0x10de, 0x0038, "nforce11", "nForce NVENET_11 Ethernet Controller"),
1423 };
1424
1425 PCI_DRIVER ( forcedeth_driver, forcedeth_nics, PCI_NO_CLASS );
1426
1427 DRIVER ( "forcedeth", nic_driver, pci_driver, forcedeth_driver,
1428          forcedeth_probe, forcedeth_disable );
1429
1430 /*
1431  * Local variables:
1432  *  c-basic-offset: 8
1433  *  c-indent-level: 8
1434  *  tab-width: 8
1435  * End:
1436  */