gpxe/src/drivers/net/natsemi.h

   1 #define NATSEMI_HW_TIMEOUT 400
   2
   3 #define TX_RING_SIZE 4
   4 #define NUM_RX_DESC  4
   5 #define RX_BUF_SIZE 1536
   6 #define OWN       0x80000000
   7 #define DSIZE     0x00000FFF
   8 #define CRC_SIZE  4
   9
  10 struct natsemi_tx {
  11         uint32_t link;
  12         uint32_t cmdsts;
  13         uint32_t bufptr;
  14 };
  15
  16 struct natsemi_rx {
  17         uint32_t link;
  18         uint32_t cmdsts;
  19         uint32_t bufptr;
  20 };
  21
  22 struct natsemi_private {
  23         unsigned short ioaddr;
  24         unsigned short tx_cur;
  25         unsigned short tx_dirty;
  26         unsigned short rx_cur;
  27         struct natsemi_tx tx[TX_RING_SIZE];
  28         struct natsemi_rx rx[NUM_RX_DESC];
  29
  30         /* need to add iobuf as we cannot free iobuf->data in close without this
  31          * alternatively substracting sizeof(head) and sizeof(list_head) can also
  32          * give the same.
  33          */
  34         struct io_buffer *iobuf[NUM_RX_DESC];
  35
  36         /* netdev_tx_complete needs pointer to the iobuf of the data so as to free
  37          * it from the memory.
  38          */
  39         struct io_buffer *tx_iobuf[TX_RING_SIZE];
  40         struct spi_bit_basher spibit;
  41         struct spi_device eeprom;
  42         struct nvo_block nvo;
  43 };
  44
  45 /*
  46  * Support for fibre connections on Am79C874:
  47  * This phy needs a special setup when connected to a fibre cable.
  48  * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf
  49  */
  50 #define PHYID_AM79C874  0x0022561b
  51
  52 enum {
  53         MII_MCTRL       = 0x15,         /* mode control register */
  54         MII_FX_SEL      = 0x0001,       /* 100BASE-FX (fiber) */
  55         MII_EN_SCRM     = 0x0004,       /* enable scrambler (tp) */
  56 };
  57
  58
  59
  60 /* values we might find in the silicon revision register */
  61 #define SRR_DP83815_C   0x0302
  62 #define SRR_DP83815_D   0x0403
  63 #define SRR_DP83816_A4  0x0504
  64 #define SRR_DP83816_A5  0x0505
  65
  66 /* NATSEMI: Offsets to the device registers.
  67  * Unlike software-only systems, device drivers interact with complex hardware.
  68  * It's not useful to define symbolic names for every register bit in the
  69  * device.
  70  */
  71 enum register_offsets {
  72     ChipCmd      = 0x00,
  73     ChipConfig   = 0x04,
  74     EECtrl       = 0x08,
  75     PCIBusCfg    = 0x0C,
  76     IntrStatus   = 0x10,
  77     IntrMask     = 0x14,
  78     IntrEnable   = 0x18,
  79     TxRingPtr    = 0x20,
  80     TxConfig     = 0x24,
  81     RxRingPtr    = 0x30,
  82     RxConfig     = 0x34,
  83     ClkRun       = 0x3C,
  84     WOLCmd       = 0x40,
  85     PauseCmd     = 0x44,
  86     RxFilterAddr = 0x48,
  87     RxFilterData = 0x4C,
  88     BootRomAddr  = 0x50,
  89     BootRomData  = 0x54,
  90     SiliconRev   = 0x58,
  91     StatsCtrl    = 0x5C,
  92     StatsData    = 0x60,
  93     RxPktErrs    = 0x60,
  94     RxMissed     = 0x68,
  95     RxCRCErrs    = 0x64,
  96     PCIPM        = 0x44,
  97     PhyStatus    = 0xC0,
  98     MIntrCtrl    = 0xC4,
  99     MIntrStatus  = 0xC8,
 100
 101     /* These are from the spec, around page 78... on a separate table.
 102      */
 103     PGSEL        = 0xCC,
 104     PMDCSR       = 0xE4,
 105     TSTDAT       = 0xFC,
 106     DSPCFG       = 0xF4,
 107     SDCFG        = 0x8C,
 108     BasicControl = 0x80,
 109     BasicStatus  = 0x84
 110
 111 };
 112
 113 /* the values for the 'magic' registers above (PGSEL=1) */
 114 #define PMDCSR_VAL      0x189c  /* enable preferred adaptation circuitry */
 115 #define TSTDAT_VAL      0x0
 116 #define DSPCFG_VAL      0x5040
 117 #define SDCFG_VAL       0x008c  /* set voltage thresholds for Signal Detect */
 118 #define DSPCFG_LOCK     0x20    /* coefficient lock bit in DSPCFG */
 119 #define DSPCFG_COEF     0x1000  /* see coefficient (in TSTDAT) bit in DSPCFG */
 120 #define TSTDAT_FIXED    0xe8    /* magic number for bad coefficients */
 121
 122 /* Bit in ChipCmd.
 123  */
 124 enum ChipCmdBits {
 125     ChipReset = 0x100,
 126     RxReset   = 0x20,
 127     TxReset   = 0x10,
 128     RxOff     = 0x08,
 129     RxOn      = 0x04,
 130     TxOff     = 0x02,
 131     TxOn      = 0x01
 132 };
 133
 134 enum ChipConfig_bits {
 135         CfgPhyDis               = 0x200,
 136         CfgPhyRst               = 0x400,
 137         CfgExtPhy               = 0x1000,
 138         CfgAnegEnable           = 0x2000,
 139         CfgAneg100              = 0x4000,
 140         CfgAnegFull             = 0x8000,
 141         CfgAnegDone             = 0x8000000,
 142         CfgFullDuplex           = 0x20000000,
 143         CfgSpeed100             = 0x40000000,
 144         CfgLink                 = 0x80000000,
 145 };
 146
 147
 148 /* Bits in the RxMode register.
 149  */
 150 enum rx_mode_bits {
 151     AcceptErr          = 0x20,
 152     AcceptRunt         = 0x10,
 153     AcceptBroadcast    = 0xC0000000,
 154     AcceptMulticast    = 0x00200000,
 155     AcceptAllMulticast = 0x20000000,
 156     AcceptAllPhys      = 0x10000000,
 157     AcceptMyPhys       = 0x08000000,
 158     RxFilterEnable     = 0x80000000
 159 };
 160
 161 /* Bits in network_desc.status
 162  */
 163 enum desc_status_bits {
 164     DescOwn   = 0x80000000,
 165     DescMore  = 0x40000000,
 166     DescIntr  = 0x20000000,
 167     DescNoCRC = 0x10000000,
 168     DescPktOK = 0x08000000,
 169     RxTooLong = 0x00400000
 170 };
 171
 172 /*Bits in Interrupt Mask register
 173  */
 174 enum Intr_mask_register_bits {
 175     RxOk       = 0x001,
 176     RxErr      = 0x004,
 177     TxOk       = 0x040,
 178     TxErr      = 0x100
 179 };
 180
 181 enum MIntrCtrl_bits {
 182   MICRIntEn               = 0x2,
 183 };
 184
 185 /* CFG bits [13:16] [18:23] */
 186 #define CFG_RESET_SAVE 0xfde000
 187 /* WCSR bits [0:4] [9:10] */
 188 #define WCSR_RESET_SAVE 0x61f
 189 /* RFCR bits [20] [22] [27:31] */
 190 #define RFCR_RESET_SAVE 0xf8500000;
 191
 192 /* Delay between EEPROM clock transitions.
 193    No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
 194    a delay. */
 195 #define eeprom_delay(ee_addr)   inl(ee_addr)
 196
 197 enum EEPROM_Ctrl_Bits {
 198         EE_ShiftClk   = 0x04,
 199         EE_DataIn     = 0x01,
 200         EE_ChipSelect = 0x08,
 201         EE_DataOut    = 0x02
 202 };
 203
 204 #define EE_Write0 (EE_ChipSelect)
 205 #define EE_Write1 (EE_ChipSelect | EE_DataIn)
 206
 207 /* The EEPROM commands include the alway-set leading bit. */
 208 enum EEPROM_Cmds {
 209   EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
 210 };
 211
 212 /*  EEPROM access , values are devices specific
 213  */
 214 #define EE_CS           0x08    /* EEPROM chip select */
 215 #define EE_SK           0x04    /* EEPROM shift clock */
 216 #define EE_DI           0x01    /* Data in */
 217 #define EE_DO           0x02    /* Data out */
 218
 219 /* Offsets within EEPROM (these are word offsets)
 220  */
 221 #define EE_MAC 7
 222 #define EE_REG  EECtrl
 223
 224 static const uint8_t natsemi_ee_bits[] = {
 225         [SPI_BIT_SCLK]  = EE_SK,
 226         [SPI_BIT_MOSI]  = EE_DI,
 227         [SPI_BIT_MISO]  = EE_DO,
 228         [SPI_BIT_SS(0)] = EE_CS,
 229 };
 230