1 /* ----------------------------------------------------------------------- *
3 * Pportions of this file taken from the dmidecode project
5 * Copyright (C) 2000-2002 Alan Cox <alan@redhat.com>
6 * Copyright (C) 2002-2008 Jean Delvare <khali@linux-fr.org>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * For the avoidance of doubt the "preferred form" of this code is one which
23 * is in an open unpatent encumbered format. Where cryptographic key signing
24 * forms part of the process of creating an executable the information
25 * including keys needed to generate an equivalently functional executable
26 * are deemed to be part of the source code.
32 const char *dmi_processor_type(uint8_t code
)
35 static const char *type
[] = {
41 "Video Processor" /* 0x06 */
44 if (code
>= 0x01 && code
<= 0x06)
45 return type
[code
- 0x01];
49 const char *dmi_processor_family(uint8_t code
, char *manufacturer
)
52 static const char *family
[256] = {
73 "Celeron M", /* 0x14 */
93 "Core 2 Duo", /* 0x28 */
187 "Turion 64", /* 0x86 */
192 "Third-Generation Opteron",
196 "Athlon X2", /* 0x8F */
214 "Quad-Core Xeon 3200", /* 0xA1 */
215 "Dual-Core Xeon 3000",
216 "Quad-Core Xeon 5300",
217 "Dual-Core Xeon 5100",
218 "Dual-Core Xeon 5000",
220 "Dual-Core Xeon ULV",
221 "Dual-Core Xeon 7100",
222 "Quad-Core Xeon 5400",
223 "Quad-Core Xeon", /* 0xAA */
230 "Pentium III Speedstep",
239 "Celeron D", /* 0xBA */
242 "Core Solo", /* 0xBD */
248 "Core 2 Extreme Mobile",
250 "Core 2 Solo Mobile",
256 "ESA/390 G6", /* 0xCB */
283 "Embedded Opteron Quad-Core", /* 0xE6 */
284 "Phenom Triple-Core",
285 "Turion Ultra Dual-Core Mobile",
286 "Turion Dual-Core Mobile",
288 "Sempron SI", /*0xEB */
310 /* Special case for ambiguous value 0xBE */
312 /* Best bet based on manufacturer string */
313 if (strstr(manufacturer
, "Intel") != NULL
314 || strncasecmp(manufacturer
, "Intel", 5) == 0)
316 if (strstr(manufacturer
, "AMD") != NULL
317 || strncasecmp(manufacturer
, "AMD", 3) == 0)
319 return "Core 2 or K7";
322 if (family
[code
] != NULL
) {
328 const char *dmi_processor_status(uint8_t code
)
330 static const char *status
[] = {
331 "Unknown", /* 0x00 */
348 const char *dmi_processor_upgrade(uint8_t code
)
351 static const char *upgrade
[] = {
356 "Replaceable Piggy Back",
365 "Socket A (Socket 462)",
369 "Socket 939" /* 0x12 */
378 if (code
>= 0x01 && code
<= 0x18)
379 return upgrade
[code
- 0x01];
383 void dmi_processor_cache(uint16_t code
, const char *level
, uint16_t ver
,
386 if (code
== 0xFFFF) {
388 sprintf(cache
, "Not Provided");
390 sprintf(cache
, "No %s Cache", level
);
392 sprintf(cache
, "0x%04X", code
);
395 /* Intel AP-485 revision 28, table 5 */
396 const char *cpu_flags_strings
[PROCESSOR_FLAGS_ELEMENTS
] = {
397 "FPU (Floating-point unit on-chip)", /* 0 */
398 "VME (Virtual mode extension)",
399 "DE (Debugging extension)",
400 "PSE (Page size extension)",
401 "TSC (Time stamp counter)",
402 "MSR (Model specific registers)",
403 "PAE (Physical address extension)",
404 "MCE (Machine check exception)",
405 "CX8 (CMPXCHG8 instruction supported)",
406 "APIC (On-chip APIC hardware supported)",
408 "SEP (Fast system call)",
409 "MTRR (Memory type range registers)",
410 "PGE (Page global enable)",
411 "MCA (Machine check architecture)",
412 "CMOV (Conditional move instruction supported)",
413 "PAT (Page attribute table)",
414 "PSE-36 (36-bit page size extension)",
415 "PSN (Processor serial number present and enabled)",
416 "CLFSH (CLFLUSH instruction supported)",
419 "ACPI (ACPI supported)",
420 "MMX (MMX technology supported)",
421 "FXSR (Fast floating-point save and restore)",
422 "SSE (Streaming SIMD extensions)",
423 "SSE2 (Streaming SIMD extensions 2)",
425 "HTT (Hyper-threading technology)",
426 "TM (Thermal monitor supported)",
427 "IA64 (IA64 capabilities)", /* 30 */
428 "PBE (Pending break enabled)" /* 31 */