* updated libkcddb (21.12.1 -> 21.12.2), untested
[t2-trunk.git] / architecture / riscv64 / package / u-boot / 0002-drivers-clk-sifive-fu740-prci-replace-pciaux-with-pc.patch
blob8178f10c67b0f3a5641f87ead97311a53168fc25
1 From a3a717668b8158c555490921722c04ea6c07bf1a Mon Sep 17 00:00:00 2001
2 From: Green Wan <green.wan@sifive.com>
3 Date: Mon, 28 Jun 2021 19:13:08 +0800
4 Subject: [PATCH 02/16] drivers: clk: sifive: fu740-prci: replace 'pciaux' with
5 'pcieaux'
7 Replace 'pciaux' with 'pcieaux', including name string and function
8 prefix. The old name string, 'pciaux', might cause an error if PCIe
9 driver is changed to use clk_get_by_name() with 'pcieaux' to get
10 clock.
12 Signed-off-by: Green Wan <green.wan@sifive.com>
13 Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
14 ---
15 drivers/clk/sifive/fu740-prci.c | 6 +++---
16 1 file changed, 3 insertions(+), 3 deletions(-)
18 diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c
19 index 9a642c1..b025050 100644
20 --- a/drivers/clk/sifive/fu740-prci.c
21 +++ b/drivers/clk/sifive/fu740-prci.c
22 @@ -20,7 +20,7 @@
23 #include "sifive-prci.h"
24 #include <asm/io.h>
26 -int sifive_prci_fu740_pciauxclk_enable(struct __prci_clock *pc, bool enable)
27 +int sifive_prci_fu740_pcieauxclk_enable(struct __prci_clock *pc, bool enable)
29 struct __prci_wrpll_data *pwd = pc->pwd;
30 struct __prci_data *pd = pc->pd;
31 @@ -98,7 +98,7 @@ static const struct __prci_clock_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = {
34 static const struct __prci_clock_ops sifive_fu740_prci_pcieaux_clk_ops = {
35 - .enable_clk = sifive_prci_fu740_pciauxclk_enable,
36 + .enable_clk = sifive_prci_fu740_pcieauxclk_enable,
39 /* List of clock controls provided by the PRCI */
40 @@ -150,7 +150,7 @@ struct __prci_clock __prci_init_clocks_fu740[] = {
41 .ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops,
43 [PRCI_CLK_PCIEAUX] {
44 - .name = "pciaux",
45 + .name = "pcieaux",
46 .parent_name = "",
47 .ops = &sifive_fu740_prci_pcieaux_clk_ops,
48 .pwd = &__prci_pcieaux_data,
49 --
50 2.7.4