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[t2-trunk.git] / package / base / linux / it87.patch
blobd6c03ff4afb0392591ed68f67c9aa6c287fa2062
1 # --- T2-COPYRIGHT-NOTE-BEGIN ---
2 # T2 SDE: package/*/linux/it87.patch
3 # Copyright (C) 2022 The T2 SDE Project
4 #
5 # This Copyright note is generated by scripts/Create-CopyPatch,
6 # more information can be found in the files COPYING and README.
7 #
8 # This patch file is dual-licensed. It is available under the license the
9 # patched project is licensed under, as long as it is an OpenSource license
10 # as defined at http://www.opensource.org/ (e.g. BSD, X11) or under the terms
11 # of the GNU General Public License version 2 as used by the T2 SDE.
12 # --- T2-COPYRIGHT-NOTE-END ---
13
14 --- linux-4.17/drivers/hwmon/it87.c.vanilla 2018-08-11 15:10:26.239361748 +0000
15 +++ linux-4.17/drivers/hwmon/it87.c 2018-08-11 15:12:55.575357320 +0000
16 @@ -11,10 +11,17 @@
17 * similar parts. The other devices are supported by different drivers.
18 *
19 * Supports: IT8603E Super I/O chip w/LPC interface
20 + * IT8606E Super I/O chip w/LPC interface
21 + * IT8607E Super I/O chip w/LPC interface
22 + * IT8613E Super I/O chip w/LPC interface
23 * IT8620E Super I/O chip w/LPC interface
24 * IT8622E Super I/O chip w/LPC interface
25 * IT8623E Super I/O chip w/LPC interface
26 + * IT8625E Super I/O chip w/LPC interface
27 * IT8628E Super I/O chip w/LPC interface
28 + * IT8655E Super I/O chip w/LPC interface
29 + * IT8665E Super I/O chip w/LPC interface
30 + * IT8686E Super I/O chip w/LPC interface
31 * IT8705F Super I/O chip w/LPC interface
32 * IT8712F Super I/O chip w/LPC interface
33 * IT8716F Super I/O chip w/LPC interface
34 @@ -24,6 +31,8 @@
35 * IT8726F Super I/O chip w/LPC interface
36 * IT8728F Super I/O chip w/LPC interface
37 * IT8732F Super I/O chip w/LPC interface
38 + * IT8736F Super I/O chip w/LPC interface
39 + * IT8738E Super I/O chip w/LPC interface
40 * IT8758E Super I/O chip w/LPC interface
41 * IT8771E Super I/O chip w/LPC interface
42 * IT8772E Super I/O chip w/LPC interface
43 @@ -68,16 +77,30 @@
44 #include <linux/acpi.h>
45 #include <linux/io.h>
46
47 +#ifndef IT87_DRIVER_VERSION
48 +#define IT87_DRIVER_VERSION "<not provided>"
49 +#endif
50 +
51 #define DRVNAME "it87"
52
53 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
54 + it8736, it8738,
55 it8771, it8772, it8781, it8782, it8783, it8786, it8790,
56 - it8792, it8603, it8620, it8622, it8628 };
57 + it8792, it8603, it8606, it8607, it8613, it8620, it8622, it8625,
58 + it8628, it8655, it8665, it8686 };
59
60 static unsigned short force_id;
61 -module_param(force_id, ushort, 0);
62 +module_param(force_id, ushort, 0000);
63 MODULE_PARM_DESC(force_id, "Override the detected device ID");
64
65 +static bool ignore_resource_conflict;
66 +module_param(ignore_resource_conflict, bool, 0000);
67 +MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict");
68 +
69 +static bool mmio;
70 +module_param(mmio, bool, 0000);
71 +MODULE_PARM_DESC(mmio, "Use MMIO if available");
72 +
73 static struct platform_device *it87_pdev[2];
74
75 #define REG_2E 0x2e /* The register to read/write */
76 @@ -92,10 +115,22 @@
77 #define DEVID 0x20 /* Register: Device ID */
78 #define DEVREV 0x22 /* Register: Device Revision */
79
80 +static inline void __superio_enter(int ioreg)
81 +{
82 + outb(0x87, ioreg);
83 + outb(0x01, ioreg);
84 + outb(0x55, ioreg);
85 + outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
86 +}
87 +
88 static inline int superio_inb(int ioreg, int reg)
89 {
90 + int val;
91 +
92 outb(reg, ioreg);
93 - return inb(ioreg + 1);
94 + val = inb(ioreg + 1);
95 +
96 + return val;
97 }
98
99 static inline void superio_outb(int ioreg, int reg, int val)
100 @@ -106,13 +141,7 @@
101
102 static int superio_inw(int ioreg, int reg)
103 {
104 - int val;
105 -
106 - outb(reg++, ioreg);
107 - val = inb(ioreg + 1) << 8;
108 - outb(reg, ioreg);
109 - val |= inb(ioreg + 1);
110 - return val;
111 + return (superio_inb(ioreg, reg) << 8) | superio_inb(ioreg, reg + 1);
112 }
113
114 static inline void superio_select(int ioreg, int ldn)
115 @@ -129,17 +158,16 @@
116 if (!request_muxed_region(ioreg, 2, DRVNAME))
117 return -EBUSY;
118
119 - outb(0x87, ioreg);
120 - outb(0x01, ioreg);
121 - outb(0x55, ioreg);
122 - outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
123 + __superio_enter(ioreg);
124 return 0;
125 }
126
127 -static inline void superio_exit(int ioreg)
128 +static inline void superio_exit(int ioreg, bool doexit)
129 {
130 - outb(0x02, ioreg);
131 - outb(0x02, ioreg + 1);
132 + if (doexit) {
133 + outb(0x02, ioreg);
134 + outb(0x02, ioreg + 1);
135 + }
136 release_region(ioreg, 2);
137 }
138
139 @@ -153,6 +181,8 @@
140 #define IT8726F_DEVID 0x8726
141 #define IT8728F_DEVID 0x8728
142 #define IT8732F_DEVID 0x8732
143 +#define IT8736F_DEVID 0x8736
144 +#define IT8738E_DEVID 0x8738
145 #define IT8792E_DEVID 0x8733
146 #define IT8771E_DEVID 0x8771
147 #define IT8772E_DEVID 0x8772
148 @@ -162,21 +192,36 @@
149 #define IT8786E_DEVID 0x8786
150 #define IT8790E_DEVID 0x8790
151 #define IT8603E_DEVID 0x8603
152 +#define IT8606E_DEVID 0x8606
153 +#define IT8607E_DEVID 0x8607
154 +#define IT8613E_DEVID 0x8613
155 #define IT8620E_DEVID 0x8620
156 #define IT8622E_DEVID 0x8622
157 #define IT8623E_DEVID 0x8623
158 +#define IT8625E_DEVID 0x8625
159 #define IT8628E_DEVID 0x8628
160 -#define IT87_ACT_REG 0x30
161 -#define IT87_BASE_REG 0x60
162 +#define IT8655E_DEVID 0x8655
163 +#define IT8665E_DEVID 0x8665
164 +#define IT8686E_DEVID 0x8686
165 +
166 +/* Logical device 4 (Environmental Monitor) registers */
167 +#define IT87_ACT_REG 0x30
168 +#define IT87_BASE_REG 0x60
169 +#define IT87_SPECIAL_CFG_REG 0xf3 /* special configuration register */
170
171 -/* Logical device 7 registers (IT8712F and later) */
172 +/* Global configuration registers (IT8712F and later) */
173 +#define IT87_EC_HWM_MIO_REG 0x24 /* MMIO configuration register */
174 #define IT87_SIO_GPIO1_REG 0x25
175 #define IT87_SIO_GPIO2_REG 0x26
176 #define IT87_SIO_GPIO3_REG 0x27
177 #define IT87_SIO_GPIO4_REG 0x28
178 #define IT87_SIO_GPIO5_REG 0x29
179 +#define IT87_SIO_GPIO9_REG 0xd3
180 #define IT87_SIO_PINX1_REG 0x2a /* Pin selection */
181 #define IT87_SIO_PINX2_REG 0x2c /* Pin selection */
182 +#define IT87_SIO_PINX4_REG 0x2d /* Pin selection */
183 +
184 +/* Logical device 7 (GPIO) registers (IT8712F and later) */
185 #define IT87_SIO_SPI_REG 0xef /* SPI function pin select */
186 #define IT87_SIO_VID_REG 0xfc /* VID value */
187 #define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */
188 @@ -204,24 +249,30 @@
189
190 /*----- The IT87 registers -----*/
191
192 -#define IT87_REG_CONFIG 0x00
193 +#define IT87_REG_CONFIG 0x00
194 +
195 +#define IT87_REG_ALARM1 0x01
196 +#define IT87_REG_ALARM2 0x02
197 +#define IT87_REG_ALARM3 0x03
198
199 -#define IT87_REG_ALARM1 0x01
200 -#define IT87_REG_ALARM2 0x02
201 -#define IT87_REG_ALARM3 0x03
202 +#define IT87_REG_BANK 0x06
203
204 /*
205 * The IT8718F and IT8720F have the VID value in a different register, in
206 * Super-I/O configuration space.
207 */
208 -#define IT87_REG_VID 0x0a
209 +#define IT87_REG_VID 0x0a
210 +
211 +/* Interface Selection register on other chips */
212 +#define IT87_REG_IFSEL 0x0a
213 +
214 /*
215 * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
216 * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
217 * mode.
218 */
219 -#define IT87_REG_FAN_DIV 0x0b
220 -#define IT87_REG_FAN_16BIT 0x0c
221 +#define IT87_REG_FAN_DIV 0x0b
222 +#define IT87_REG_FAN_16BIT 0x0c
223
224 /*
225 * Monitors:
226 @@ -230,33 +281,53 @@
227 * - up to 6 fan (1 to 6)
228 */
229
230 -static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
231 -static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
232 -static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
233 -static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
234 -static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59 };
235 -
236 -#define IT87_REG_FAN_MAIN_CTRL 0x13
237 -#define IT87_REG_FAN_CTL 0x14
238 -static const u8 IT87_REG_PWM[] = { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
239 -static const u8 IT87_REG_PWM_DUTY[] = { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
240 +static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
241 +static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
242 +static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
243 +static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
244 +
245 +static const u8 IT87_REG_FAN_8665[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x93 };
246 +static const u8 IT87_REG_FAN_MIN_8665[] = {
247 + 0x10, 0x11, 0x12, 0x84, 0x86, 0xb2 };
248 +static const u8 IT87_REG_FANX_8665[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x94 };
249 +static const u8 IT87_REG_FANX_MIN_8665[] = {
250 + 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0xb3 };
251 +
252 +static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 };
253 +
254 +static const u8 IT87_REG_TEMP_OFFSET_8686[] = {
255 + 0x56, 0x57, 0x59, 0x90, 0x91, 0x92 };
256 +
257 +#define IT87_REG_FAN_MAIN_CTRL 0x13
258 +#define IT87_REG_FAN_CTL 0x14
259 +
260 +static const u8 IT87_REG_PWM[] = { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
261 +static const u8 IT87_REG_PWM_8665[] = { 0x15, 0x16, 0x17, 0x1e, 0x1f, 0x92 };
262 +
263 +static const u8 IT87_REG_PWM_DUTY[] = { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
264
265 static const u8 IT87_REG_VIN[] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
266 0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
267
268 -#define IT87_REG_TEMP(nr) (0x29 + (nr))
269 +#define IT87_REG_TEMP(nr) (0x29 + (nr))
270 +
271 +#define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2)
272 +#define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2)
273 +
274 +static const u8 IT87_REG_TEMP_HIGH[] = { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 };
275 +static const u8 IT87_REG_TEMP_LOW[] = { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 };
276 +
277 +static const u8 IT87_REG_TEMP_HIGH_8686[] = {
278 + 0x40, 0x42, 0x44, 0xb4, 0xb6, 0xb8 };
279 +static const u8 IT87_REG_TEMP_LOW_8686[] = {
280 + 0x41, 0x43, 0x45, 0xb5, 0xb7, 0xb9 };
281
282 -#define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2)
283 -#define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2)
284 -#define IT87_REG_TEMP_HIGH(nr) (0x40 + (nr) * 2)
285 -#define IT87_REG_TEMP_LOW(nr) (0x41 + (nr) * 2)
286 -
287 -#define IT87_REG_VIN_ENABLE 0x50
288 -#define IT87_REG_TEMP_ENABLE 0x51
289 -#define IT87_REG_TEMP_EXTRA 0x55
290 -#define IT87_REG_BEEP_ENABLE 0x5c
291 +#define IT87_REG_VIN_ENABLE 0x50
292 +#define IT87_REG_TEMP_ENABLE 0x51
293 +#define IT87_REG_TEMP_EXTRA 0x55
294 +#define IT87_REG_BEEP_ENABLE 0x5c
295
296 -#define IT87_REG_CHIPID 0x58
297 +#define IT87_REG_CHIPID 0x58
298
299 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
300
301 @@ -265,11 +336,12 @@
302
303 #define IT87_REG_TEMP456_ENABLE 0x77
304
305 +static const u16 IT87_REG_TEMP_SRC1[] = { 0x21d, 0x21e, 0x21f };
306 +#define IT87_REG_TEMP_SRC2 0x23d
307 +
308 #define NUM_VIN ARRAY_SIZE(IT87_REG_VIN)
309 #define NUM_VIN_LIMIT 8
310 #define NUM_TEMP 6
311 -#define NUM_TEMP_OFFSET ARRAY_SIZE(IT87_REG_TEMP_OFFSET)
312 -#define NUM_TEMP_LIMIT 3
313 #define NUM_FAN ARRAY_SIZE(IT87_REG_FAN)
314 #define NUM_FAN_DIV 3
315 #define NUM_PWM ARRAY_SIZE(IT87_REG_PWM)
316 @@ -277,17 +349,21 @@
317
318 struct it87_devices {
319 const char *name;
320 - const char * const suffix;
321 + const char * const model;
322 u32 features;
323 + u8 num_temp_limit;
324 + u8 num_temp_offset;
325 + u8 num_temp_map; /* Number of temperature sources for pwm */
326 u8 peci_mask;
327 u8 old_peci_mask;
328 + u8 smbus_bitmap; /* SMBus enable bits in extra config register */
329 + u8 ec_special_config;
330 };
331
332 #define FEAT_12MV_ADC BIT(0)
333 #define FEAT_NEWER_AUTOPWM BIT(1)
334 #define FEAT_OLD_AUTOPWM BIT(2)
335 #define FEAT_16BIT_FANS BIT(3)
336 -#define FEAT_TEMP_OFFSET BIT(4)
337 #define FEAT_TEMP_PECI BIT(5)
338 #define FEAT_TEMP_OLD_PECI BIT(6)
339 #define FEAT_FAN16_CONFIG BIT(7) /* Need to enable 16-bit fans */
340 @@ -302,173 +378,361 @@
341 #define FEAT_PWM_FREQ2 BIT(16) /* Separate pwm freq 2 */
342 #define FEAT_SIX_TEMP BIT(17) /* Up to 6 temp sensors */
343 #define FEAT_VIN3_5V BIT(18) /* VIN3 connected to +5V */
344 +#define FEAT_FOUR_FANS BIT(19) /* Supports four fans */
345 +#define FEAT_FOUR_PWM BIT(20) /* Supports four fan controls */
346 +#define FEAT_BANK_SEL BIT(21) /* Chip has multi-bank support */
347 +#define FEAT_SCALING BIT(22) /* Internal voltage scaling */
348 +#define FEAT_FANCTL_ONOFF BIT(23) /* chip has FAN_CTL ON/OFF */
349 +#define FEAT_11MV_ADC BIT(24)
350 +#define FEAT_NEW_TEMPMAP BIT(25) /* new temp input selection */
351 +#define FEAT_MMIO BIT(26) /* Chip supports MMIO */
352 +#define FEAT_FOUR_TEMP BIT(27)
353
354 static const struct it87_devices it87_devices[] = {
355 [it87] = {
356 .name = "it87",
357 - .suffix = "F",
358 - .features = FEAT_OLD_AUTOPWM, /* may need to overwrite */
359 + .model = "IT87F",
360 + .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
361 + /* may need to overwrite */
362 + .num_temp_limit = 3,
363 + .num_temp_offset = 0,
364 + .num_temp_map = 3,
365 },
366 [it8712] = {
367 .name = "it8712",
368 - .suffix = "F",
369 - .features = FEAT_OLD_AUTOPWM | FEAT_VID,
370 + .model = "IT8712F",
371 + .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
372 /* may need to overwrite */
373 + .num_temp_limit = 3,
374 + .num_temp_offset = 0,
375 + .num_temp_map = 3,
376 },
377 [it8716] = {
378 .name = "it8716",
379 - .suffix = "F",
380 - .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
381 - | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2,
382 + .model = "IT8716F",
383 + .features = FEAT_16BIT_FANS | FEAT_VID
384 + | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
385 + | FEAT_FANCTL_ONOFF,
386 + .num_temp_limit = 3,
387 + .num_temp_offset = 3,
388 + .num_temp_map = 3,
389 },
390 [it8718] = {
391 .name = "it8718",
392 - .suffix = "F",
393 - .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
394 + .model = "IT8718F",
395 + .features = FEAT_16BIT_FANS | FEAT_VID
396 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
397 - | FEAT_PWM_FREQ2,
398 + | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
399 + .num_temp_limit = 3,
400 + .num_temp_offset = 3,
401 + .num_temp_map = 3,
402 .old_peci_mask = 0x4,
403 },
404 [it8720] = {
405 .name = "it8720",
406 - .suffix = "F",
407 - .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
408 + .model = "IT8720F",
409 + .features = FEAT_16BIT_FANS | FEAT_VID
410 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
411 - | FEAT_PWM_FREQ2,
412 + | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
413 + .num_temp_limit = 3,
414 + .num_temp_offset = 3,
415 + .num_temp_map = 3,
416 .old_peci_mask = 0x4,
417 },
418 [it8721] = {
419 .name = "it8721",
420 - .suffix = "F",
421 + .model = "IT8721F",
422 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
423 - | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
424 + | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
425 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
426 - | FEAT_PWM_FREQ2,
427 + | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
428 + .num_temp_limit = 3,
429 + .num_temp_offset = 3,
430 + .num_temp_map = 3,
431 .peci_mask = 0x05,
432 .old_peci_mask = 0x02, /* Actually reports PCH */
433 },
434 [it8728] = {
435 .name = "it8728",
436 - .suffix = "F",
437 + .model = "IT8728F",
438 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
439 - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
440 - | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2,
441 + | FEAT_TEMP_PECI | FEAT_FIVE_FANS
442 + | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING
443 + | FEAT_FANCTL_ONOFF,
444 + .num_temp_limit = 6,
445 + .num_temp_offset = 3,
446 + .num_temp_map = 3,
447 .peci_mask = 0x07,
448 },
449 [it8732] = {
450 .name = "it8732",
451 - .suffix = "F",
452 + .model = "IT8732F",
453 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
454 - | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
455 - | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL,
456 + | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
457 + | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
458 + | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF | FEAT_SCALING,
459 + .num_temp_limit = 3,
460 + .num_temp_offset = 3,
461 + .num_temp_map = 3,
462 + .peci_mask = 0x07,
463 + .old_peci_mask = 0x02, /* Actually reports PCH */
464 + },
465 + [it8736] = {
466 + .name = "it8736",
467 + .model = "IT8736F",
468 + .features = FEAT_16BIT_FANS
469 + | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
470 + | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
471 + | FEAT_FANCTL_ONOFF | FEAT_SCALING,
472 + .num_temp_limit = 3,
473 + .num_temp_offset = 3,
474 + .num_temp_map = 3,
475 .peci_mask = 0x07,
476 .old_peci_mask = 0x02, /* Actually reports PCH */
477 },
478 + [it8738] = {
479 + .name = "it8738",
480 + .model = "IT8738E",
481 + .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
482 + | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
483 + | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL
484 + | FEAT_FANCTL_ONOFF | FEAT_SCALING
485 + | FEAT_AVCC3,
486 + .num_temp_limit = 3,
487 + .num_temp_offset = 3,
488 + .num_temp_map = 3,
489 + .peci_mask = 0x07,
490 + .old_peci_mask = 0x02,
491 + },
492 [it8771] = {
493 .name = "it8771",
494 - .suffix = "E",
495 + .model = "IT8771E",
496 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
497 - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
498 - | FEAT_PWM_FREQ2,
499 + | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
500 + | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
501 /* PECI: guesswork */
502 /* 12mV ADC (OHM) */
503 /* 16 bit fans (OHM) */
504 /* three fans, always 16 bit (guesswork) */
505 + .num_temp_limit = 3,
506 + .num_temp_offset = 3,
507 + .num_temp_map = 3,
508 .peci_mask = 0x07,
509 },
510 [it8772] = {
511 .name = "it8772",
512 - .suffix = "E",
513 + .model = "IT8772E",
514 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
515 - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
516 - | FEAT_PWM_FREQ2,
517 + | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
518 + | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
519 /* PECI (coreboot) */
520 /* 12mV ADC (HWSensors4, OHM) */
521 /* 16 bit fans (HWSensors4, OHM) */
522 /* three fans, always 16 bit (datasheet) */
523 + .num_temp_limit = 3,
524 + .num_temp_offset = 3,
525 + .num_temp_map = 3,
526 .peci_mask = 0x07,
527 },
528 [it8781] = {
529 .name = "it8781",
530 - .suffix = "F",
531 - .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
532 - | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
533 + .model = "IT8781F",
534 + .features = FEAT_16BIT_FANS
535 + | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
536 + | FEAT_FANCTL_ONOFF,
537 + .num_temp_limit = 3,
538 + .num_temp_offset = 3,
539 + .num_temp_map = 3,
540 .old_peci_mask = 0x4,
541 },
542 [it8782] = {
543 .name = "it8782",
544 - .suffix = "F",
545 - .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
546 - | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
547 + .model = "IT8782F",
548 + .features = FEAT_16BIT_FANS
549 + | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
550 + | FEAT_FANCTL_ONOFF,
551 + .num_temp_limit = 3,
552 + .num_temp_offset = 3,
553 + .num_temp_map = 3,
554 .old_peci_mask = 0x4,
555 },
556 [it8783] = {
557 .name = "it8783",
558 - .suffix = "E/F",
559 - .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
560 - | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
561 + .model = "IT8783E/F",
562 + .features = FEAT_16BIT_FANS
563 + | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
564 + | FEAT_FANCTL_ONOFF,
565 + .num_temp_limit = 3,
566 + .num_temp_offset = 3,
567 + .num_temp_map = 3,
568 .old_peci_mask = 0x4,
569 },
570 [it8786] = {
571 .name = "it8786",
572 - .suffix = "E",
573 + .model = "IT8786E",
574 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
575 - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
576 - | FEAT_PWM_FREQ2,
577 + | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
578 + | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
579 + .num_temp_limit = 3,
580 + .num_temp_offset = 3,
581 + .num_temp_map = 3,
582 .peci_mask = 0x07,
583 },
584 [it8790] = {
585 .name = "it8790",
586 - .suffix = "E",
587 - .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
588 - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
589 - | FEAT_PWM_FREQ2,
590 + .model = "IT8790E",
591 + .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
592 + | FEAT_16BIT_FANS | FEAT_TEMP_PECI
593 + | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
594 + .num_temp_limit = 3,
595 + .num_temp_offset = 3,
596 + .num_temp_map = 3,
597 .peci_mask = 0x07,
598 },
599 [it8792] = {
600 .name = "it8792",
601 - .suffix = "E",
602 - .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
603 - | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
604 - | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL,
605 + .model = "IT8792E/IT8795E",
606 + .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
607 + | FEAT_16BIT_FANS | FEAT_TEMP_PECI
608 + | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
609 + .num_temp_limit = 3,
610 + .num_temp_offset = 3,
611 + .num_temp_map = 3,
612 .peci_mask = 0x07,
613 - .old_peci_mask = 0x02, /* Actually reports PCH */
614 },
615 [it8603] = {
616 .name = "it8603",
617 - .suffix = "E",
618 + .model = "IT8603E",
619 + .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
620 + | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
621 + | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
622 + .num_temp_limit = 3,
623 + .num_temp_offset = 3,
624 + .num_temp_map = 4,
625 + .peci_mask = 0x07,
626 + },
627 + [it8606] = {
628 + .name = "it8606",
629 + .model = "IT8606E",
630 + .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
631 + | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
632 + | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
633 + .num_temp_limit = 3,
634 + .num_temp_offset = 3,
635 + .num_temp_map = 3,
636 + .peci_mask = 0x07,
637 + },
638 + [it8607] = {
639 + .name = "it8607",
640 + .model = "IT8607E",
641 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
642 - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
643 - | FEAT_AVCC3 | FEAT_PWM_FREQ2,
644 + | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_NEW_TEMPMAP
645 + | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING
646 + | FEAT_FANCTL_ONOFF,
647 + .num_temp_limit = 3,
648 + .num_temp_offset = 3,
649 + .num_temp_map = 6,
650 + .peci_mask = 0x07,
651 + },
652 + [it8613] = {
653 + .name = "it8613",
654 + .model = "IT8613E",
655 + .features = FEAT_NEWER_AUTOPWM | FEAT_11MV_ADC | FEAT_16BIT_FANS
656 + | FEAT_TEMP_PECI | FEAT_FIVE_FANS
657 + | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
658 + | FEAT_AVCC3 | FEAT_SCALING | FEAT_NEW_TEMPMAP,
659 + .num_temp_limit = 6,
660 + .num_temp_offset = 6,
661 + .num_temp_map = 6,
662 .peci_mask = 0x07,
663 },
664 [it8620] = {
665 .name = "it8620",
666 - .suffix = "E",
667 + .model = "IT8620E",
668 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
669 - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
670 + | FEAT_TEMP_PECI | FEAT_SIX_FANS
671 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
672 - | FEAT_SIX_TEMP | FEAT_VIN3_5V,
673 + | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_SCALING
674 + | FEAT_FANCTL_ONOFF,
675 + .num_temp_limit = 3,
676 + .num_temp_offset = 3,
677 + .num_temp_map = 3,
678 .peci_mask = 0x07,
679 },
680 [it8622] = {
681 .name = "it8622",
682 - .suffix = "E",
683 + .model = "IT8622E",
684 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
685 - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
686 + | FEAT_TEMP_PECI | FEAT_FIVE_FANS | FEAT_FOUR_TEMP
687 | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
688 - | FEAT_AVCC3 | FEAT_VIN3_5V,
689 - .peci_mask = 0x07,
690 + | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_SCALING,
691 + .num_temp_limit = 3,
692 + .num_temp_offset = 3,
693 + .num_temp_map = 4,
694 + .peci_mask = 0x0f,
695 + .smbus_bitmap = BIT(1) | BIT(2),
696 + },
697 + [it8625] = {
698 + .name = "it8625",
699 + .model = "IT8625E",
700 + .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
701 + | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
702 + | FEAT_11MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
703 + | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_SCALING,
704 + .num_temp_limit = 6,
705 + .num_temp_offset = 6,
706 + .num_temp_map = 6,
707 + .smbus_bitmap = BIT(1) | BIT(2),
708 },
709 [it8628] = {
710 .name = "it8628",
711 - .suffix = "E",
712 + .model = "IT8628E",
713 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
714 - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
715 + | FEAT_TEMP_PECI | FEAT_SIX_FANS
716 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
717 - | FEAT_SIX_TEMP | FEAT_VIN3_5V,
718 + | FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3
719 + | FEAT_FANCTL_ONOFF,
720 + .num_temp_limit = 6,
721 + .num_temp_offset = 3,
722 + .num_temp_map = 3,
723 .peci_mask = 0x07,
724 },
725 + [it8655] = {
726 + .name = "it8655",
727 + .model = "IT8655E",
728 + .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
729 + | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
730 + | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL
731 + | FEAT_SIX_TEMP | FEAT_MMIO,
732 + .num_temp_limit = 6,
733 + .num_temp_offset = 6,
734 + .num_temp_map = 6,
735 + .smbus_bitmap = BIT(2),
736 + },
737 + [it8665] = {
738 + .name = "it8665",
739 + .model = "IT8665E",
740 + .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
741 + | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
742 + | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
743 + | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_MMIO | FEAT_SIX_TEMP,
744 + .num_temp_limit = 6,
745 + .num_temp_offset = 6,
746 + .num_temp_map = 6,
747 + .smbus_bitmap = BIT(2),
748 + },
749 + [it8686] = {
750 + .name = "it8686",
751 + .model = "IT8686E",
752 + .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
753 + | FEAT_SIX_FANS | FEAT_NEW_TEMPMAP
754 + | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
755 + | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
756 + .num_temp_limit = 6,
757 + .num_temp_offset = 6,
758 + .num_temp_map = 7,
759 + .smbus_bitmap = BIT(1) | BIT(2),
760 + },
761 };
762
763 #define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS)
764 @@ -476,7 +740,6 @@
765 #define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC)
766 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
767 #define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM)
768 -#define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET)
769 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
770 ((data)->peci_mask & BIT(nr)))
771 #define has_temp_old_peci(data, nr) \
772 @@ -495,22 +758,37 @@
773 #define has_pwm_freq2(data) ((data)->features & FEAT_PWM_FREQ2)
774 #define has_six_temp(data) ((data)->features & FEAT_SIX_TEMP)
775 #define has_vin3_5v(data) ((data)->features & FEAT_VIN3_5V)
776 +#define has_four_fans(data) ((data)->features & (FEAT_FOUR_FANS | \
777 + FEAT_FIVE_FANS | \
778 + FEAT_SIX_FANS))
779 +#define has_four_pwm(data) ((data)->features & (FEAT_FOUR_PWM | \
780 + FEAT_FIVE_PWM \
781 + | FEAT_SIX_PWM))
782 +#define has_bank_sel(data) ((data)->features & FEAT_BANK_SEL)
783 +#define has_scaling(data) ((data)->features & FEAT_SCALING)
784 +#define has_fanctl_onoff(data) ((data)->features & FEAT_FANCTL_ONOFF)
785 +#define has_11mv_adc(data) ((data)->features & FEAT_11MV_ADC)
786 +#define has_new_tempmap(data) ((data)->features & FEAT_NEW_TEMPMAP)
787 +#define has_mmio(data) ((data)->features & FEAT_MMIO)
788 +#define has_four_temp(data) ((data)->features & FEAT_FOUR_TEMP)
789
790 struct it87_sio_data {
791 - int sioaddr;
792 enum chips type;
793 + u8 sioaddr;
794 + u8 doexit;
795 /* Values read from Super-I/O config space */
796 u8 revision;
797 u8 vid_value;
798 u8 beep_pin;
799 u8 internal; /* Internal sensors can be labeled */
800 - bool need_in7_reroute;
801 /* Features skipped based on config or DMI */
802 u16 skip_in;
803 u8 skip_vid;
804 u8 skip_fan;
805 u8 skip_pwm;
806 u8 skip_temp;
807 + u8 smbus_bitmap;
808 + u8 ec_special_config;
809 };
810
811 /*
812 @@ -519,14 +797,33 @@
813 */
814 struct it87_data {
815 const struct attribute_group *groups[7];
816 - int sioaddr;
817 enum chips type;
818 u32 features;
819 u8 peci_mask;
820 u8 old_peci_mask;
821
822 + u8 smbus_bitmap; /* !=0 if SMBus needs to be disabled */
823 + u8 saved_bank; /* saved bank register value */
824 + u8 ec_special_config; /* EC special config register restore value */
825 + u8 sioaddr; /* SIO port address */
826 + bool doexit; /* true if exit from sio config is ok */
827 +
828 + void __iomem *mmio; /* Remapped MMIO address if available */
829 + int (*read)(struct it87_data *, u16);
830 + void (*write)(struct it87_data *, u16, u8);
831 +
832 + const u8 *REG_FAN;
833 + const u8 *REG_FANX;
834 + const u8 *REG_FAN_MIN;
835 + const u8 *REG_FANX_MIN;
836 +
837 + const u8 *REG_PWM;
838 +
839 + const u8 *REG_TEMP_OFFSET;
840 + const u8 *REG_TEMP_LOW;
841 + const u8 *REG_TEMP_HIGH;
842 +
843 unsigned short addr;
844 - const char *name;
845 struct mutex update_lock;
846 bool valid; /* true if following fields are valid */
847 unsigned long last_updated; /* In jiffies */
848 @@ -535,11 +832,13 @@
849 u16 in_internal; /* Bitfield, internal sensors (for labels) */
850 u16 has_in; /* Bitfield, voltage sensors enabled */
851 u8 in[NUM_VIN][3]; /* [nr][0]=in, [1]=min, [2]=max */
852 - bool need_in7_reroute;
853 u8 has_fan; /* Bitfield, fans enabled */
854 u16 fan[NUM_FAN][2]; /* Register values, [nr][0]=fan, [1]=min */
855 u8 has_temp; /* Bitfield, temp sensors enabled */
856 s8 temp[NUM_TEMP][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
857 + u8 num_temp_limit; /* Number of temperature limit registers */
858 + u8 num_temp_offset; /* Number of temperature offset registers */
859 + u8 temp_src[4]; /* Up to 4 temperature source registers */
860 u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */
861 u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */
862 u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
863 @@ -566,6 +865,9 @@
864 u8 pwm_ctrl[NUM_PWM]; /* Register value */
865 u8 pwm_duty[NUM_PWM]; /* Manual PWM value set by user */
866 u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
867 + u8 pwm_temp_map_mask; /* 0x03 for old, 0x07 for new temp map */
868 + u8 pwm_temp_map_shift; /* 0 for old, 3 for new temp map */
869 + u8 pwm_num_temp_map; /* from config data, 3..7 depending on chip */
870
871 /* Automatic fan speed control registers */
872 u8 auto_pwm[NUM_AUTO_PWM][4]; /* [nr][3] is hard-coded */
873 @@ -580,6 +882,8 @@
874 lsb = 120;
875 else if (has_10_9mv_adc(data))
876 lsb = 109;
877 + else if (has_11mv_adc(data))
878 + lsb = 110;
879 else
880 lsb = 160;
881 if (data->in_scaled & BIT(nr))
882 @@ -650,6 +954,25 @@
883
884 #define DIV_FROM_REG(val) BIT(val)
885
886 +static u8 temp_map_from_reg(const struct it87_data *data, u8 reg)
887 +{
888 + u8 map;
889 +
890 + map = (reg >> data->pwm_temp_map_shift) & data->pwm_temp_map_mask;
891 + if (map >= data->pwm_num_temp_map) /* map is 0-based */
892 + map = 0;
893 +
894 + return map;
895 +}
896 +
897 +static u8 temp_map_to_reg(const struct it87_data *data, int nr, u8 map)
898 +{
899 + u8 ctrl = data->pwm_ctrl[nr];
900 +
901 + return (ctrl & ~(data->pwm_temp_map_mask << data->pwm_temp_map_shift)) |
902 + (map << data->pwm_temp_map_shift);
903 +}
904 +
905 /*
906 * PWM base frequencies. The frequency has to be divided by either 128 or 256,
907 * depending on the chip type, to calculate the actual PWM frequency.
908 @@ -671,50 +994,139 @@
909 750000,
910 };
911
912 +static int _it87_io_read(struct it87_data *data, u16 reg)
913 +{
914 + outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
915 + return inb_p(data->addr + IT87_DATA_REG_OFFSET);
916 +}
917 +
918 +static void _it87_io_write(struct it87_data *data, u16 reg, u8 value)
919 +{
920 + outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
921 + outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
922 +}
923 +
924 +static int smbus_disable(struct it87_data *data)
925 +{
926 + int err;
927 +
928 + if (data->smbus_bitmap) {
929 + err = superio_enter(data->sioaddr);
930 + if (err)
931 + return err;
932 + superio_select(data->sioaddr, PME);
933 + superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
934 + data->ec_special_config & ~data->smbus_bitmap);
935 + superio_exit(data->sioaddr, data->doexit);
936 + if (has_bank_sel(data) && !data->mmio)
937 + data->saved_bank = _it87_io_read(data, IT87_REG_BANK);
938 + }
939 + return 0;
940 +}
941 +
942 +static int smbus_enable(struct it87_data *data)
943 +{
944 + int err;
945 +
946 + if (data->smbus_bitmap) {
947 + if (has_bank_sel(data) && !data->mmio)
948 + _it87_io_write(data, IT87_REG_BANK, data->saved_bank);
949 + err = superio_enter(data->sioaddr);
950 + if (err)
951 + return err;
952 +
953 + superio_select(data->sioaddr, PME);
954 + superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
955 + data->ec_special_config);
956 + superio_exit(data->sioaddr, data->doexit);
957 + }
958 + return 0;
959 +}
960 +
961 +static u8 it87_io_set_bank(struct it87_data *data, u8 bank)
962 +{
963 + u8 _bank = bank;
964 +
965 + if (has_bank_sel(data)) {
966 + u8 breg = _it87_io_read(data, IT87_REG_BANK);
967 +
968 + _bank = breg >> 5;
969 + if (bank != _bank) {
970 + breg &= 0x1f;
971 + breg |= (bank << 5);
972 + _it87_io_write(data, IT87_REG_BANK, breg);
973 + }
974 + }
975 + return _bank;
976 +}
977 +
978 /*
979 * Must be called with data->update_lock held, except during initialization.
980 + * Must be called with SMBus accesses disabled.
981 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
982 * would slow down the IT87 access and should not be necessary.
983 */
984 -static int it87_read_value(struct it87_data *data, u8 reg)
985 +static int it87_io_read(struct it87_data *data, u16 reg)
986 {
987 - outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
988 - return inb_p(data->addr + IT87_DATA_REG_OFFSET);
989 + u8 bank;
990 + int val;
991 +
992 + bank = it87_io_set_bank(data, reg >> 8);
993 + val = _it87_io_read(data, reg & 0xff);
994 + it87_io_set_bank(data, bank);
995 +
996 + return val;
997 }
998
999 /*
1000 * Must be called with data->update_lock held, except during initialization.
1001 + * Must be called with SMBus accesses disabled
1002 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
1003 * would slow down the IT87 access and should not be necessary.
1004 */
1005 -static void it87_write_value(struct it87_data *data, u8 reg, u8 value)
1006 +static void it87_io_write(struct it87_data *data, u16 reg, u8 value)
1007 {
1008 - outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
1009 - outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
1010 + u8 bank;
1011 +
1012 + bank = it87_io_set_bank(data, reg >> 8);
1013 + _it87_io_write(data, reg & 0xff, value);
1014 + it87_io_set_bank(data, bank);
1015 +}
1016 +
1017 +static int it87_mmio_read(struct it87_data *data, u16 reg)
1018 +{
1019 + return readb(data->mmio + reg);
1020 +}
1021 +
1022 +static void it87_mmio_write(struct it87_data *data, u16 reg, u8 value)
1023 +{
1024 + writeb(value, data->mmio + reg);
1025 }
1026
1027 static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
1028 {
1029 - data->pwm_ctrl[nr] = it87_read_value(data, IT87_REG_PWM[nr]);
1030 + u8 ctrl;
1031 +
1032 + ctrl = data->read(data, data->REG_PWM[nr]);
1033 + data->pwm_ctrl[nr] = ctrl;
1034 if (has_newer_autopwm(data)) {
1035 - data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
1036 - data->pwm_duty[nr] = it87_read_value(data,
1037 - IT87_REG_PWM_DUTY[nr]);
1038 + data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
1039 + data->pwm_duty[nr] = data->read(data, IT87_REG_PWM_DUTY[nr]);
1040 } else {
1041 - if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */
1042 - data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
1043 + if (ctrl & 0x80) /* Automatic mode */
1044 + data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
1045 else /* Manual mode */
1046 - data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f;
1047 + data->pwm_duty[nr] = ctrl & 0x7f;
1048 }
1049
1050 if (has_old_autopwm(data)) {
1051 int i;
1052
1053 for (i = 0; i < 5 ; i++)
1054 - data->auto_temp[nr][i] = it87_read_value(data,
1055 + data->auto_temp[nr][i] = data->read(data,
1056 IT87_REG_AUTO_TEMP(nr, i));
1057 for (i = 0; i < 3 ; i++)
1058 - data->auto_pwm[nr][i] = it87_read_value(data,
1059 + data->auto_pwm[nr][i] = data->read(data,
1060 IT87_REG_AUTO_PWM(nr, i));
1061 } else if (has_newer_autopwm(data)) {
1062 int i;
1063 @@ -726,55 +1138,75 @@
1064 * 3: fan max temperature (base + 2)
1065 */
1066 data->auto_temp[nr][0] =
1067 - it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5));
1068 + data->read(data, IT87_REG_AUTO_TEMP(nr, 5));
1069
1070 for (i = 0; i < 3 ; i++)
1071 data->auto_temp[nr][i + 1] =
1072 - it87_read_value(data,
1073 - IT87_REG_AUTO_TEMP(nr, i));
1074 + data->read(data, IT87_REG_AUTO_TEMP(nr, i));
1075 /*
1076 * 0: start pwm value (base + 3)
1077 * 1: pwm slope (base + 4, 1/8th pwm)
1078 */
1079 data->auto_pwm[nr][0] =
1080 - it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3));
1081 + data->read(data, IT87_REG_AUTO_TEMP(nr, 3));
1082 data->auto_pwm[nr][1] =
1083 - it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4));
1084 + data->read(data, IT87_REG_AUTO_TEMP(nr, 4));
1085 }
1086 }
1087
1088 +static int it87_lock(struct it87_data *data)
1089 +{
1090 + int err;
1091 +
1092 + mutex_lock(&data->update_lock);
1093 + err = smbus_disable(data);
1094 + if (err)
1095 + mutex_unlock(&data->update_lock);
1096 + return err;
1097 +}
1098 +
1099 +static void it87_unlock(struct it87_data *data)
1100 +{
1101 + smbus_enable(data);
1102 + mutex_unlock(&data->update_lock);
1103 +}
1104 +
1105 static struct it87_data *it87_update_device(struct device *dev)
1106 {
1107 struct it87_data *data = dev_get_drvdata(dev);
1108 + struct it87_data *ret = data;
1109 + int err;
1110 int i;
1111
1112 mutex_lock(&data->update_lock);
1113
1114 if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
1115 !data->valid) {
1116 + err = smbus_disable(data);
1117 + if (err) {
1118 + ret = ERR_PTR(err);
1119 + goto unlock;
1120 + }
1121 if (update_vbat) {
1122 /*
1123 * Cleared after each update, so reenable. Value
1124 * returned by this read will be previous value
1125 */
1126 - it87_write_value(data, IT87_REG_CONFIG,
1127 - it87_read_value(data, IT87_REG_CONFIG) | 0x40);
1128 + data->write(data, IT87_REG_CONFIG,
1129 + data->read(data, IT87_REG_CONFIG) | 0x40);
1130 }
1131 for (i = 0; i < NUM_VIN; i++) {
1132 if (!(data->has_in & BIT(i)))
1133 continue;
1134
1135 - data->in[i][0] =
1136 - it87_read_value(data, IT87_REG_VIN[i]);
1137 + data->in[i][0] = data->read(data, IT87_REG_VIN[i]);
1138
1139 /* VBAT and AVCC don't have limit registers */
1140 if (i >= NUM_VIN_LIMIT)
1141 continue;
1142
1143 - data->in[i][1] =
1144 - it87_read_value(data, IT87_REG_VIN_MIN(i));
1145 - data->in[i][2] =
1146 - it87_read_value(data, IT87_REG_VIN_MAX(i));
1147 + data->in[i][1] = data->read(data, IT87_REG_VIN_MIN(i));
1148 + data->in[i][2] = data->read(data, IT87_REG_VIN_MAX(i));
1149 }
1150
1151 for (i = 0; i < NUM_FAN; i++) {
1152 @@ -782,70 +1214,67 @@
1153 if (!(data->has_fan & BIT(i)))
1154 continue;
1155
1156 - data->fan[i][1] =
1157 - it87_read_value(data, IT87_REG_FAN_MIN[i]);
1158 - data->fan[i][0] = it87_read_value(data,
1159 - IT87_REG_FAN[i]);
1160 + data->fan[i][1] = data->read(data,
1161 + data->REG_FAN_MIN[i]);
1162 + data->fan[i][0] = data->read(data, data->REG_FAN[i]);
1163 /* Add high byte if in 16-bit mode */
1164 if (has_16bit_fans(data)) {
1165 - data->fan[i][0] |= it87_read_value(data,
1166 - IT87_REG_FANX[i]) << 8;
1167 - data->fan[i][1] |= it87_read_value(data,
1168 - IT87_REG_FANX_MIN[i]) << 8;
1169 + data->fan[i][0] |= data->read(data,
1170 + data->REG_FANX[i]) << 8;
1171 + data->fan[i][1] |= data->read(data,
1172 + data->REG_FANX_MIN[i]) << 8;
1173 }
1174 }
1175 for (i = 0; i < NUM_TEMP; i++) {
1176 if (!(data->has_temp & BIT(i)))
1177 continue;
1178 data->temp[i][0] =
1179 - it87_read_value(data, IT87_REG_TEMP(i));
1180 + data->read(data, IT87_REG_TEMP(i));
1181
1182 - if (has_temp_offset(data) && i < NUM_TEMP_OFFSET)
1183 - data->temp[i][3] =
1184 - it87_read_value(data,
1185 - IT87_REG_TEMP_OFFSET[i]);
1186 -
1187 - if (i >= NUM_TEMP_LIMIT)
1188 + if (i >= data->num_temp_limit)
1189 continue;
1190
1191 + if (i < data->num_temp_offset)
1192 + data->temp[i][3] =
1193 + data->read(data, data->REG_TEMP_OFFSET[i]);
1194 +
1195 data->temp[i][1] =
1196 - it87_read_value(data, IT87_REG_TEMP_LOW(i));
1197 + data->read(data, data->REG_TEMP_LOW[i]);
1198 data->temp[i][2] =
1199 - it87_read_value(data, IT87_REG_TEMP_HIGH(i));
1200 + data->read(data, data->REG_TEMP_HIGH[i]);
1201 }
1202
1203 /* Newer chips don't have clock dividers */
1204 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
1205 - i = it87_read_value(data, IT87_REG_FAN_DIV);
1206 + i = data->read(data, IT87_REG_FAN_DIV);
1207 data->fan_div[0] = i & 0x07;
1208 data->fan_div[1] = (i >> 3) & 0x07;
1209 data->fan_div[2] = (i & 0x40) ? 3 : 1;
1210 }
1211
1212 data->alarms =
1213 - it87_read_value(data, IT87_REG_ALARM1) |
1214 - (it87_read_value(data, IT87_REG_ALARM2) << 8) |
1215 - (it87_read_value(data, IT87_REG_ALARM3) << 16);
1216 - data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1217 -
1218 - data->fan_main_ctrl = it87_read_value(data,
1219 - IT87_REG_FAN_MAIN_CTRL);
1220 - data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
1221 + data->read(data, IT87_REG_ALARM1) |
1222 + (data->read(data, IT87_REG_ALARM2) << 8) |
1223 + (data->read(data, IT87_REG_ALARM3) << 16);
1224 + data->beeps = data->read(data, IT87_REG_BEEP_ENABLE);
1225 +
1226 + data->fan_main_ctrl = data->read(data, IT87_REG_FAN_MAIN_CTRL);
1227 + data->fan_ctl = data->read(data, IT87_REG_FAN_CTL);
1228 for (i = 0; i < NUM_PWM; i++) {
1229 if (!(data->has_pwm & BIT(i)))
1230 continue;
1231 it87_update_pwm_ctrl(data, i);
1232 }
1233
1234 - data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1235 - data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1236 + data->sensor = data->read(data, IT87_REG_TEMP_ENABLE);
1237 + data->extra = data->read(data, IT87_REG_TEMP_EXTRA);
1238 /*
1239 * The IT8705F does not have VID capability.
1240 * The IT8718F and later don't use IT87_REG_VID for the
1241 * same purpose.
1242 */
1243 if (data->type == it8712 || data->type == it8716) {
1244 - data->vid = it87_read_value(data, IT87_REG_VID);
1245 + data->vid = data->read(data, IT87_REG_VID);
1246 /*
1247 * The older IT8712F revisions had only 5 VID pins,
1248 * but we assume it is always safe to read 6 bits.
1249 @@ -854,11 +1283,11 @@
1250 }
1251 data->last_updated = jiffies;
1252 data->valid = true;
1253 + smbus_enable(data);
1254 }
1255 -
1256 +unlock:
1257 mutex_unlock(&data->update_lock);
1258 -
1259 - return data;
1260 + return ret;
1261 }
1262
1263 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
1264 @@ -869,6 +1298,9 @@
1265 int index = sattr->index;
1266 int nr = sattr->nr;
1267
1268 + if (IS_ERR(data))
1269 + return PTR_ERR(data);
1270 +
1271 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1272 }
1273
1274 @@ -880,73 +1312,60 @@
1275 int index = sattr->index;
1276 int nr = sattr->nr;
1277 unsigned long val;
1278 + int err;
1279
1280 if (kstrtoul(buf, 10, &val) < 0)
1281 return -EINVAL;
1282
1283 - mutex_lock(&data->update_lock);
1284 + err = it87_lock(data);
1285 + if (err)
1286 + return err;
1287 +
1288 data->in[nr][index] = in_to_reg(data, nr, val);
1289 - it87_write_value(data,
1290 - index == 1 ? IT87_REG_VIN_MIN(nr)
1291 - : IT87_REG_VIN_MAX(nr),
1292 - data->in[nr][index]);
1293 - mutex_unlock(&data->update_lock);
1294 + data->write(data, index == 1 ? IT87_REG_VIN_MIN(nr)
1295 + : IT87_REG_VIN_MAX(nr),
1296 + data->in[nr][index]);
1297 + it87_unlock(data);
1298 return count;
1299 }
1300
1301 -static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
1302 -static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
1303 - 0, 1);
1304 -static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
1305 - 0, 2);
1306 -
1307 -static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
1308 -static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
1309 - 1, 1);
1310 -static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
1311 - 1, 2);
1312 -
1313 -static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
1314 -static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
1315 - 2, 1);
1316 -static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
1317 - 2, 2);
1318 -
1319 -static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
1320 -static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
1321 - 3, 1);
1322 -static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
1323 - 3, 2);
1324 -
1325 -static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
1326 -static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
1327 - 4, 1);
1328 -static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
1329 - 4, 2);
1330 -
1331 -static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
1332 -static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
1333 - 5, 1);
1334 -static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
1335 - 5, 2);
1336 -
1337 -static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
1338 -static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
1339 - 6, 1);
1340 -static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
1341 - 6, 2);
1342 -
1343 -static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
1344 -static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
1345 - 7, 1);
1346 -static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
1347 - 7, 2);
1348 -
1349 -static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
1350 -static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
1351 -static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0);
1352 -static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0);
1353 -static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0);
1354 +static SENSOR_DEVICE_ATTR_2(in0_input, 0444, show_in, NULL, 0, 0);
1355 +static SENSOR_DEVICE_ATTR_2(in0_min, 0644, show_in, set_in, 0, 1);
1356 +static SENSOR_DEVICE_ATTR_2(in0_max, 0644, show_in, set_in, 0, 2);
1357 +
1358 +static SENSOR_DEVICE_ATTR_2(in1_input, 0444, show_in, NULL, 1, 0);
1359 +static SENSOR_DEVICE_ATTR_2(in1_min, 0644, show_in, set_in, 1, 1);
1360 +static SENSOR_DEVICE_ATTR_2(in1_max, 0644, show_in, set_in, 1, 2);
1361 +
1362 +static SENSOR_DEVICE_ATTR_2(in2_input, 0444, show_in, NULL, 2, 0);
1363 +static SENSOR_DEVICE_ATTR_2(in2_min, 0644, show_in, set_in, 2, 1);
1364 +static SENSOR_DEVICE_ATTR_2(in2_max, 0644, show_in, set_in, 2, 2);
1365 +
1366 +static SENSOR_DEVICE_ATTR_2(in3_input, 0444, show_in, NULL, 3, 0);
1367 +static SENSOR_DEVICE_ATTR_2(in3_min, 0644, show_in, set_in, 3, 1);
1368 +static SENSOR_DEVICE_ATTR_2(in3_max, 0644, show_in, set_in, 3, 2);
1369 +
1370 +static SENSOR_DEVICE_ATTR_2(in4_input, 0444, show_in, NULL, 4, 0);
1371 +static SENSOR_DEVICE_ATTR_2(in4_min, 0644, show_in, set_in, 4, 1);
1372 +static SENSOR_DEVICE_ATTR_2(in4_max, 0644, show_in, set_in, 4, 2);
1373 +
1374 +static SENSOR_DEVICE_ATTR_2(in5_input, 0444, show_in, NULL, 5, 0);
1375 +static SENSOR_DEVICE_ATTR_2(in5_min, 0644, show_in, set_in, 5, 1);
1376 +static SENSOR_DEVICE_ATTR_2(in5_max, 0644, show_in, set_in, 5, 2);
1377 +
1378 +static SENSOR_DEVICE_ATTR_2(in6_input, 0444, show_in, NULL, 6, 0);
1379 +static SENSOR_DEVICE_ATTR_2(in6_min, 0644, show_in, set_in, 6, 1);
1380 +static SENSOR_DEVICE_ATTR_2(in6_max, 0644, show_in, set_in, 6, 2);
1381 +
1382 +static SENSOR_DEVICE_ATTR_2(in7_input, 0444, show_in, NULL, 7, 0);
1383 +static SENSOR_DEVICE_ATTR_2(in7_min, 0644, show_in, set_in, 7, 1);
1384 +static SENSOR_DEVICE_ATTR_2(in7_max, 0644, show_in, set_in, 7, 2);
1385 +
1386 +static SENSOR_DEVICE_ATTR_2(in8_input, 0444, show_in, NULL, 8, 0);
1387 +static SENSOR_DEVICE_ATTR_2(in9_input, 0444, show_in, NULL, 9, 0);
1388 +static SENSOR_DEVICE_ATTR_2(in10_input, 0444, show_in, NULL, 10, 0);
1389 +static SENSOR_DEVICE_ATTR_2(in11_input, 0444, show_in, NULL, 11, 0);
1390 +static SENSOR_DEVICE_ATTR_2(in12_input, 0444, show_in, NULL, 12, 0);
1391
1392 /* Up to 6 temperatures */
1393 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
1394 @@ -957,6 +1376,9 @@
1395 int index = sattr->index;
1396 struct it87_data *data = it87_update_device(dev);
1397
1398 + if (IS_ERR(data))
1399 + return PTR_ERR(data);
1400 +
1401 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1402 }
1403
1404 @@ -969,79 +1391,169 @@
1405 struct it87_data *data = dev_get_drvdata(dev);
1406 long val;
1407 u8 reg, regval;
1408 + int err;
1409
1410 if (kstrtol(buf, 10, &val) < 0)
1411 return -EINVAL;
1412
1413 - mutex_lock(&data->update_lock);
1414 + err = it87_lock(data);
1415 + if (err)
1416 + return err;
1417
1418 switch (index) {
1419 default:
1420 case 1:
1421 - reg = IT87_REG_TEMP_LOW(nr);
1422 + reg = data->REG_TEMP_LOW[nr];
1423 break;
1424 case 2:
1425 - reg = IT87_REG_TEMP_HIGH(nr);
1426 + reg = data->REG_TEMP_HIGH[nr];
1427 break;
1428 case 3:
1429 - regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1430 + regval = data->read(data, IT87_REG_BEEP_ENABLE);
1431 if (!(regval & 0x80)) {
1432 regval |= 0x80;
1433 - it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
1434 + data->write(data, IT87_REG_BEEP_ENABLE, regval);
1435 }
1436 data->valid = false;
1437 - reg = IT87_REG_TEMP_OFFSET[nr];
1438 + reg = data->REG_TEMP_OFFSET[nr];
1439 break;
1440 }
1441
1442 data->temp[nr][index] = TEMP_TO_REG(val);
1443 - it87_write_value(data, reg, data->temp[nr][index]);
1444 - mutex_unlock(&data->update_lock);
1445 + data->write(data, reg, data->temp[nr][index]);
1446 + it87_unlock(data);
1447 return count;
1448 }
1449
1450 -static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
1451 -static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1452 - 0, 1);
1453 -static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1454 - 0, 2);
1455 -static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
1456 - set_temp, 0, 3);
1457 -static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
1458 -static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1459 - 1, 1);
1460 -static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1461 - 1, 2);
1462 -static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
1463 - set_temp, 1, 3);
1464 -static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
1465 -static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1466 - 2, 1);
1467 -static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1468 - 2, 2);
1469 -static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
1470 - set_temp, 2, 3);
1471 -static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0);
1472 -static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0);
1473 -static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0);
1474 +static SENSOR_DEVICE_ATTR_2(temp1_input, 0444, show_temp, NULL, 0, 0);
1475 +static SENSOR_DEVICE_ATTR_2(temp1_min, 0644, show_temp, set_temp, 0, 1);
1476 +static SENSOR_DEVICE_ATTR_2(temp1_max, 0644, show_temp, set_temp, 0, 2);
1477 +static SENSOR_DEVICE_ATTR_2(temp1_offset, 0644, show_temp, set_temp, 0, 3);
1478 +static SENSOR_DEVICE_ATTR_2(temp2_input, 0444, show_temp, NULL, 1, 0);
1479 +static SENSOR_DEVICE_ATTR_2(temp2_min, 0644, show_temp, set_temp, 1, 1);
1480 +static SENSOR_DEVICE_ATTR_2(temp2_max, 0644, show_temp, set_temp, 1, 2);
1481 +static SENSOR_DEVICE_ATTR_2(temp2_offset, 0644, show_temp, set_temp, 1, 3);
1482 +static SENSOR_DEVICE_ATTR_2(temp3_input, 0444, show_temp, NULL, 2, 0);
1483 +static SENSOR_DEVICE_ATTR_2(temp3_min, 0644, show_temp, set_temp, 2, 1);
1484 +static SENSOR_DEVICE_ATTR_2(temp3_max, 0644, show_temp, set_temp, 2, 2);
1485 +static SENSOR_DEVICE_ATTR_2(temp3_offset, 0644, show_temp, set_temp, 2, 3);
1486 +static SENSOR_DEVICE_ATTR_2(temp4_input, 0444, show_temp, NULL, 3, 0);
1487 +static SENSOR_DEVICE_ATTR_2(temp4_min, 0644, show_temp, set_temp, 3, 1);
1488 +static SENSOR_DEVICE_ATTR_2(temp4_max, 0644, show_temp, set_temp, 3, 2);
1489 +static SENSOR_DEVICE_ATTR_2(temp4_offset, 0644, show_temp, set_temp, 3, 3);
1490 +static SENSOR_DEVICE_ATTR_2(temp5_input, 0444, show_temp, NULL, 4, 0);
1491 +static SENSOR_DEVICE_ATTR_2(temp5_min, 0644, show_temp, set_temp, 4, 1);
1492 +static SENSOR_DEVICE_ATTR_2(temp5_max, 0644, show_temp, set_temp, 4, 2);
1493 +static SENSOR_DEVICE_ATTR_2(temp5_offset, 0644, show_temp, set_temp, 4, 3);
1494 +static SENSOR_DEVICE_ATTR_2(temp6_input, 0444, show_temp, NULL, 5, 0);
1495 +static SENSOR_DEVICE_ATTR_2(temp6_min, 0644, show_temp, set_temp, 5, 1);
1496 +static SENSOR_DEVICE_ATTR_2(temp6_max, 0644, show_temp, set_temp, 5, 2);
1497 +static SENSOR_DEVICE_ATTR_2(temp6_offset, 0644, show_temp, set_temp, 5, 3);
1498 +
1499 +static const u8 temp_types_8686[NUM_TEMP][9] = {
1500 + { 0, 8, 8, 8, 8, 8, 8, 8, 7 },
1501 + { 0, 6, 8, 8, 6, 0, 0, 0, 7 },
1502 + { 0, 6, 5, 8, 6, 0, 0, 0, 7 },
1503 + { 4, 8, 8, 8, 8, 8, 8, 8, 7 },
1504 + { 4, 6, 8, 8, 6, 0, 0, 0, 7 },
1505 + { 4, 6, 5, 8, 6, 0, 0, 0, 7 },
1506 +};
1507 +
1508 +static int get_temp_type(struct it87_data *data, int index)
1509 +{
1510 + u8 reg, extra;
1511 + int ttype, type = 0;
1512 +
1513 + if (has_bank_sel(data)) {
1514 + u8 src1, src2;
1515 +
1516 + src1 = (data->temp_src[index / 2] >> ((index % 2) * 4)) & 0x0f;
1517 +
1518 + switch (data->type) {
1519 + case it8686:
1520 + if (src1 < 9)
1521 + type = temp_types_8686[index][src1];
1522 + break;
1523 + case it8625:
1524 + if (index < 3)
1525 + break;
1526 + case it8655:
1527 + case it8665:
1528 + if (src1 < 3) {
1529 + index = src1;
1530 + break;
1531 + }
1532 + src2 = data->temp_src[3];
1533 + switch (src1) {
1534 + case 3:
1535 + type = (src2 & BIT(index)) ? 6 : 5;
1536 + break;
1537 + case 4 ... 8:
1538 + type = (src2 & BIT(index)) ? 4 : 6;
1539 + break;
1540 + case 9:
1541 + type = (src2 & BIT(index)) ? 5 : 0;
1542 + break;
1543 + default:
1544 + break;
1545 + }
1546 + return type;
1547 + default:
1548 + return 0;
1549 + }
1550 + }
1551 + if (type)
1552 + return type;
1553 +
1554 + /* Dectect PECI vs. AMDTSI */
1555 + ttype = 6;
1556 + if ((has_temp_peci(data, index)) || data->type == it8721 ||
1557 + data->type == it8720) {
1558 + extra = data->read(data, IT87_REG_IFSEL);
1559 + if ((extra & 0x70) == 0x40)
1560 + ttype = 5;
1561 + }
1562 +
1563 + reg = data->read(data, IT87_REG_TEMP_ENABLE);
1564 +
1565 + /* Per chip special detection */
1566 + switch (data->type) {
1567 + case it8622:
1568 + if (!(reg & 0xc0) && index == 3)
1569 + type = ttype;
1570 + break;
1571 + default:
1572 + break;
1573 + }
1574 +
1575 + if (type || index >= 3)
1576 + return type;
1577 +
1578 + extra = data->read(data, IT87_REG_TEMP_EXTRA);
1579 +
1580 + if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) ||
1581 + (has_temp_old_peci(data, index) && (extra & 0x80)))
1582 + type = ttype; /* Intel PECI or AMDTSI */
1583 + else if (reg & BIT(index))
1584 + type = 3; /* thermal diode */
1585 + else if (reg & BIT(index + 3))
1586 + type = 4; /* thermistor */
1587 +
1588 + return type;
1589 +}
1590
1591 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
1592 char *buf)
1593 {
1594 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1595 - int nr = sensor_attr->index;
1596 struct it87_data *data = it87_update_device(dev);
1597 - u8 reg = data->sensor; /* In case value is updated while used */
1598 - u8 extra = data->extra;
1599 + int type;
1600 +
1601 + if (IS_ERR(data))
1602 + return PTR_ERR(data);
1603
1604 - if ((has_temp_peci(data, nr) && (reg >> 6 == nr + 1)) ||
1605 - (has_temp_old_peci(data, nr) && (extra & 0x80)))
1606 - return sprintf(buf, "6\n"); /* Intel PECI */
1607 - if (reg & (1 << nr))
1608 - return sprintf(buf, "3\n"); /* thermal diode */
1609 - if (reg & (8 << nr))
1610 - return sprintf(buf, "4\n"); /* thermistor */
1611 - return sprintf(buf, "0\n"); /* disabled */
1612 + type = get_temp_type(data, sensor_attr->index);
1613 + return sprintf(buf, "%d\n", type);
1614 }
1615
1616 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1617 @@ -1053,16 +1565,21 @@
1618 struct it87_data *data = dev_get_drvdata(dev);
1619 long val;
1620 u8 reg, extra;
1621 + int err;
1622
1623 if (kstrtol(buf, 10, &val) < 0)
1624 return -EINVAL;
1625
1626 - reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1627 + err = it87_lock(data);
1628 + if (err)
1629 + return err;
1630 +
1631 + reg = data->read(data, IT87_REG_TEMP_ENABLE);
1632 reg &= ~(1 << nr);
1633 reg &= ~(8 << nr);
1634 if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1635 reg &= 0x3f;
1636 - extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1637 + extra = data->read(data, IT87_REG_TEMP_EXTRA);
1638 if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1639 extra &= 0x7f;
1640 if (val == 2) { /* backwards compatibility */
1641 @@ -1079,36 +1596,39 @@
1642 reg |= (nr + 1) << 6;
1643 else if (has_temp_old_peci(data, nr) && val == 6)
1644 extra |= 0x80;
1645 - else if (val != 0)
1646 - return -EINVAL;
1647 + else if (val != 0) {
1648 + count = -EINVAL;
1649 + goto unlock;
1650 + }
1651
1652 - mutex_lock(&data->update_lock);
1653 data->sensor = reg;
1654 data->extra = extra;
1655 - it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
1656 + data->write(data, IT87_REG_TEMP_ENABLE, data->sensor);
1657 if (has_temp_old_peci(data, nr))
1658 - it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1659 + data->write(data, IT87_REG_TEMP_EXTRA, data->extra);
1660 data->valid = false; /* Force cache refresh */
1661 - mutex_unlock(&data->update_lock);
1662 +unlock:
1663 + it87_unlock(data);
1664 return count;
1665 }
1666
1667 -static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
1668 - set_temp_type, 0);
1669 -static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
1670 - set_temp_type, 1);
1671 -static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
1672 - set_temp_type, 2);
1673 +static SENSOR_DEVICE_ATTR(temp1_type, 0644, show_temp_type, set_temp_type, 0);
1674 +static SENSOR_DEVICE_ATTR(temp2_type, 0644, show_temp_type, set_temp_type, 1);
1675 +static SENSOR_DEVICE_ATTR(temp3_type, 0644, show_temp_type, set_temp_type, 2);
1676 +static SENSOR_DEVICE_ATTR(temp4_type, 0644, show_temp_type, set_temp_type, 3);
1677 +static SENSOR_DEVICE_ATTR(temp5_type, 0644, show_temp_type, set_temp_type, 4);
1678 +static SENSOR_DEVICE_ATTR(temp6_type, 0644, show_temp_type, set_temp_type, 5);
1679
1680 /* 6 Fans */
1681
1682 static int pwm_mode(const struct it87_data *data, int nr)
1683 {
1684 - if (data->type != it8603 && nr < 3 && !(data->fan_main_ctrl & BIT(nr)))
1685 + if (has_fanctl_onoff(data) && nr < 3 &&
1686 + !(data->fan_main_ctrl & BIT(nr)))
1687 return 0; /* Full speed */
1688 if (data->pwm_ctrl[nr] & 0x80)
1689 return 2; /* Automatic mode */
1690 - if ((data->type == it8603 || nr >= 3) &&
1691 + if ((!has_fanctl_onoff(data) || nr >= 3) &&
1692 data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1693 return 0; /* Full speed */
1694
1695 @@ -1124,6 +1644,9 @@
1696 int speed;
1697 struct it87_data *data = it87_update_device(dev);
1698
1699 + if (IS_ERR(data))
1700 + return PTR_ERR(data);
1701 +
1702 speed = has_16bit_fans(data) ?
1703 FAN16_FROM_REG(data->fan[nr][index]) :
1704 FAN_FROM_REG(data->fan[nr][index],
1705 @@ -1138,6 +1661,9 @@
1706 struct it87_data *data = it87_update_device(dev);
1707 int nr = sensor_attr->index;
1708
1709 + if (IS_ERR(data))
1710 + return PTR_ERR(data);
1711 +
1712 return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1713 }
1714
1715 @@ -1148,6 +1674,9 @@
1716 struct it87_data *data = it87_update_device(dev);
1717 int nr = sensor_attr->index;
1718
1719 + if (IS_ERR(data))
1720 + return PTR_ERR(data);
1721 +
1722 return sprintf(buf, "%d\n", pwm_mode(data, nr));
1723 }
1724
1725 @@ -1158,6 +1687,9 @@
1726 struct it87_data *data = it87_update_device(dev);
1727 int nr = sensor_attr->index;
1728
1729 + if (IS_ERR(data))
1730 + return PTR_ERR(data);
1731 +
1732 return sprintf(buf, "%d\n",
1733 pwm_from_reg(data, data->pwm_duty[nr]));
1734 }
1735 @@ -1171,6 +1703,9 @@
1736 unsigned int freq;
1737 int index;
1738
1739 + if (IS_ERR(data))
1740 + return PTR_ERR(data);
1741 +
1742 if (has_pwm_freq2(data) && nr == 1)
1743 index = (data->extra >> 4) & 0x07;
1744 else
1745 @@ -1190,21 +1725,24 @@
1746
1747 struct it87_data *data = dev_get_drvdata(dev);
1748 long val;
1749 + int err;
1750 u8 reg;
1751
1752 if (kstrtol(buf, 10, &val) < 0)
1753 return -EINVAL;
1754
1755 - mutex_lock(&data->update_lock);
1756 + err = it87_lock(data);
1757 + if (err)
1758 + return err;
1759
1760 if (has_16bit_fans(data)) {
1761 data->fan[nr][index] = FAN16_TO_REG(val);
1762 - it87_write_value(data, IT87_REG_FAN_MIN[nr],
1763 - data->fan[nr][index] & 0xff);
1764 - it87_write_value(data, IT87_REG_FANX_MIN[nr],
1765 - data->fan[nr][index] >> 8);
1766 + data->write(data, data->REG_FAN_MIN[nr],
1767 + data->fan[nr][index] & 0xff);
1768 + data->write(data, data->REG_FANX_MIN[nr],
1769 + data->fan[nr][index] >> 8);
1770 } else {
1771 - reg = it87_read_value(data, IT87_REG_FAN_DIV);
1772 + reg = data->read(data, IT87_REG_FAN_DIV);
1773 switch (nr) {
1774 case 0:
1775 data->fan_div[nr] = reg & 0x07;
1776 @@ -1218,11 +1756,9 @@
1777 }
1778 data->fan[nr][index] =
1779 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1780 - it87_write_value(data, IT87_REG_FAN_MIN[nr],
1781 - data->fan[nr][index]);
1782 + data->write(data, data->REG_FAN_MIN[nr], data->fan[nr][index]);
1783 }
1784 -
1785 - mutex_unlock(&data->update_lock);
1786 + it87_unlock(data);
1787 return count;
1788 }
1789
1790 @@ -1233,14 +1769,17 @@
1791 struct it87_data *data = dev_get_drvdata(dev);
1792 int nr = sensor_attr->index;
1793 unsigned long val;
1794 - int min;
1795 + int min, err;
1796 u8 old;
1797
1798 if (kstrtoul(buf, 10, &val) < 0)
1799 return -EINVAL;
1800
1801 - mutex_lock(&data->update_lock);
1802 - old = it87_read_value(data, IT87_REG_FAN_DIV);
1803 + err = it87_lock(data);
1804 + if (err)
1805 + return err;
1806 +
1807 + old = data->read(data, IT87_REG_FAN_DIV);
1808
1809 /* Save fan min limit */
1810 min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1811 @@ -1261,13 +1800,12 @@
1812 val |= (data->fan_div[1] & 0x07) << 3;
1813 if (data->fan_div[2] == 3)
1814 val |= 0x1 << 6;
1815 - it87_write_value(data, IT87_REG_FAN_DIV, val);
1816 + data->write(data, IT87_REG_FAN_DIV, val);
1817
1818 /* Restore fan min limit */
1819 data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1820 - it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan[nr][1]);
1821 -
1822 - mutex_unlock(&data->update_lock);
1823 + data->write(data, data->REG_FAN_MIN[nr], data->fan[nr][1]);
1824 + it87_unlock(data);
1825 return count;
1826 }
1827
1828 @@ -1308,6 +1846,7 @@
1829 struct it87_data *data = dev_get_drvdata(dev);
1830 int nr = sensor_attr->index;
1831 long val;
1832 + int err;
1833
1834 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1835 return -EINVAL;
1836 @@ -1318,58 +1857,64 @@
1837 return -EINVAL;
1838 }
1839
1840 - mutex_lock(&data->update_lock);
1841 + err = it87_lock(data);
1842 + if (err)
1843 + return err;
1844 +
1845 + it87_update_pwm_ctrl(data, nr);
1846
1847 if (val == 0) {
1848 - if (nr < 3 && data->type != it8603) {
1849 + if (nr < 3 && has_fanctl_onoff(data)) {
1850 int tmp;
1851 /* make sure the fan is on when in on/off mode */
1852 - tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1853 - it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1854 + tmp = data->read(data, IT87_REG_FAN_CTL);
1855 + data->write(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1856 /* set on/off mode */
1857 data->fan_main_ctrl &= ~BIT(nr);
1858 - it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1859 - data->fan_main_ctrl);
1860 + data->write(data, IT87_REG_FAN_MAIN_CTRL,
1861 + data->fan_main_ctrl);
1862 } else {
1863 u8 ctrl;
1864
1865 /* No on/off mode, set maximum pwm value */
1866 data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1867 - it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1868 - data->pwm_duty[nr]);
1869 + data->write(data, IT87_REG_PWM_DUTY[nr],
1870 + data->pwm_duty[nr]);
1871 /* and set manual mode */
1872 if (has_newer_autopwm(data)) {
1873 - ctrl = (data->pwm_ctrl[nr] & 0x7c) |
1874 - data->pwm_temp_map[nr];
1875 + ctrl = temp_map_to_reg(data, nr,
1876 + data->pwm_temp_map[nr]);
1877 + ctrl &= 0x7f;
1878 } else {
1879 ctrl = data->pwm_duty[nr];
1880 }
1881 data->pwm_ctrl[nr] = ctrl;
1882 - it87_write_value(data, IT87_REG_PWM[nr], ctrl);
1883 + data->write(data, data->REG_PWM[nr], ctrl);
1884 }
1885 } else {
1886 u8 ctrl;
1887
1888 if (has_newer_autopwm(data)) {
1889 - ctrl = (data->pwm_ctrl[nr] & 0x7c) |
1890 - data->pwm_temp_map[nr];
1891 - if (val != 1)
1892 + ctrl = temp_map_to_reg(data, nr,
1893 + data->pwm_temp_map[nr]);
1894 + if (val == 1)
1895 + ctrl &= 0x7f;
1896 + else
1897 ctrl |= 0x80;
1898 } else {
1899 ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1900 }
1901 data->pwm_ctrl[nr] = ctrl;
1902 - it87_write_value(data, IT87_REG_PWM[nr], ctrl);
1903 + data->write(data, data->REG_PWM[nr], ctrl);
1904
1905 - if (data->type != it8603 && nr < 3) {
1906 + if (has_fanctl_onoff(data) && nr < 3) {
1907 /* set SmartGuardian mode */
1908 data->fan_main_ctrl |= BIT(nr);
1909 - it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1910 - data->fan_main_ctrl);
1911 + data->write(data, IT87_REG_FAN_MAIN_CTRL,
1912 + data->fan_main_ctrl);
1913 }
1914 }
1915 -
1916 - mutex_unlock(&data->update_lock);
1917 + it87_unlock(data);
1918 return count;
1919 }
1920
1921 @@ -1380,11 +1925,15 @@
1922 struct it87_data *data = dev_get_drvdata(dev);
1923 int nr = sensor_attr->index;
1924 long val;
1925 + int err;
1926
1927 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1928 return -EINVAL;
1929
1930 - mutex_lock(&data->update_lock);
1931 + err = it87_lock(data);
1932 + if (err)
1933 + return err;
1934 +
1935 it87_update_pwm_ctrl(data, nr);
1936 if (has_newer_autopwm(data)) {
1937 /*
1938 @@ -1392,12 +1941,12 @@
1939 * is read-only so we can't write the value.
1940 */
1941 if (data->pwm_ctrl[nr] & 0x80) {
1942 - mutex_unlock(&data->update_lock);
1943 - return -EBUSY;
1944 + count = -EBUSY;
1945 + goto unlock;
1946 }
1947 data->pwm_duty[nr] = pwm_to_reg(data, val);
1948 - it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1949 - data->pwm_duty[nr]);
1950 + data->write(data, IT87_REG_PWM_DUTY[nr],
1951 + data->pwm_duty[nr]);
1952 } else {
1953 data->pwm_duty[nr] = pwm_to_reg(data, val);
1954 /*
1955 @@ -1406,11 +1955,12 @@
1956 */
1957 if (!(data->pwm_ctrl[nr] & 0x80)) {
1958 data->pwm_ctrl[nr] = data->pwm_duty[nr];
1959 - it87_write_value(data, IT87_REG_PWM[nr],
1960 - data->pwm_ctrl[nr]);
1961 + data->write(data, data->REG_PWM[nr],
1962 + data->pwm_ctrl[nr]);
1963 }
1964 }
1965 - mutex_unlock(&data->update_lock);
1966 +unlock:
1967 + it87_unlock(data);
1968 return count;
1969 }
1970
1971 @@ -1421,6 +1971,7 @@
1972 struct it87_data *data = dev_get_drvdata(dev);
1973 int nr = sensor_attr->index;
1974 unsigned long val;
1975 + int err;
1976 int i;
1977
1978 if (kstrtoul(buf, 10, &val) < 0)
1979 @@ -1430,23 +1981,25 @@
1980 val *= has_newer_autopwm(data) ? 256 : 128;
1981
1982 /* Search for the nearest available frequency */
1983 - for (i = 0; i < 7; i++) {
1984 + for (i = 0; i < ARRAY_SIZE(pwm_freq) - 1; i++) {
1985 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1986 break;
1987 }
1988
1989 - mutex_lock(&data->update_lock);
1990 + err = it87_lock(data);
1991 + if (err)
1992 + return err;
1993 +
1994 if (nr == 0) {
1995 - data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
1996 + data->fan_ctl = data->read(data, IT87_REG_FAN_CTL) & 0x8f;
1997 data->fan_ctl |= i << 4;
1998 - it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
1999 + data->write(data, IT87_REG_FAN_CTL, data->fan_ctl);
2000 } else {
2001 - data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f;
2002 + data->extra = data->read(data, IT87_REG_TEMP_EXTRA) & 0x8f;
2003 data->extra |= i << 4;
2004 - it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
2005 + data->write(data, IT87_REG_TEMP_EXTRA, data->extra);
2006 }
2007 - mutex_unlock(&data->update_lock);
2008 -
2009 + it87_unlock(data);
2010 return count;
2011 }
2012
2013 @@ -1456,15 +2009,11 @@
2014 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2015 struct it87_data *data = it87_update_device(dev);
2016 int nr = sensor_attr->index;
2017 - int map;
2018
2019 - map = data->pwm_temp_map[nr];
2020 - if (map >= 3)
2021 - map = 0; /* Should never happen */
2022 - if (nr >= 3) /* pwm channels 3..6 map to temp4..6 */
2023 - map += 3;
2024 + if (IS_ERR(data))
2025 + return PTR_ERR(data);
2026
2027 - return sprintf(buf, "%d\n", (int)BIT(map));
2028 + return sprintf(buf, "%d\n", data->pwm_temp_map[nr] + 1);
2029 }
2030
2031 static ssize_t set_pwm_temp_map(struct device *dev,
2032 @@ -1474,42 +2023,33 @@
2033 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2034 struct it87_data *data = dev_get_drvdata(dev);
2035 int nr = sensor_attr->index;
2036 - long val;
2037 - u8 reg;
2038 + unsigned long val;
2039 + int err;
2040 + u8 map;
2041
2042 - if (kstrtol(buf, 10, &val) < 0)
2043 + if (kstrtoul(buf, 10, &val) < 0)
2044 return -EINVAL;
2045
2046 - if (nr >= 3)
2047 - val -= 3;
2048 -
2049 - switch (val) {
2050 - case BIT(0):
2051 - reg = 0x00;
2052 - break;
2053 - case BIT(1):
2054 - reg = 0x01;
2055 - break;
2056 - case BIT(2):
2057 - reg = 0x02;
2058 - break;
2059 - default:
2060 + if (!val || val > data->pwm_num_temp_map)
2061 return -EINVAL;
2062 - }
2063
2064 - mutex_lock(&data->update_lock);
2065 + map = val - 1;
2066 +
2067 + err = it87_lock(data);
2068 + if (err)
2069 + return err;
2070 +
2071 it87_update_pwm_ctrl(data, nr);
2072 - data->pwm_temp_map[nr] = reg;
2073 + data->pwm_temp_map[nr] = map;
2074 /*
2075 * If we are in automatic mode, write the temp mapping immediately;
2076 * otherwise, just store it for later use.
2077 */
2078 if (data->pwm_ctrl[nr] & 0x80) {
2079 - data->pwm_ctrl[nr] = (data->pwm_ctrl[nr] & 0xfc) |
2080 - data->pwm_temp_map[nr];
2081 - it87_write_value(data, IT87_REG_PWM[nr], data->pwm_ctrl[nr]);
2082 + data->pwm_ctrl[nr] = temp_map_to_reg(data, nr, map);
2083 + data->write(data, data->REG_PWM[nr], data->pwm_ctrl[nr]);
2084 }
2085 - mutex_unlock(&data->update_lock);
2086 + it87_unlock(data);
2087 return count;
2088 }
2089
2090 @@ -1522,6 +2062,9 @@
2091 int nr = sensor_attr->nr;
2092 int point = sensor_attr->index;
2093
2094 + if (IS_ERR(data))
2095 + return PTR_ERR(data);
2096 +
2097 return sprintf(buf, "%d\n",
2098 pwm_from_reg(data, data->auto_pwm[nr][point]));
2099 }
2100 @@ -1536,18 +2079,22 @@
2101 int point = sensor_attr->index;
2102 int regaddr;
2103 long val;
2104 + int err;
2105
2106 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
2107 return -EINVAL;
2108
2109 - mutex_lock(&data->update_lock);
2110 + err = it87_lock(data);
2111 + if (err)
2112 + return err;
2113 +
2114 data->auto_pwm[nr][point] = pwm_to_reg(data, val);
2115 if (has_newer_autopwm(data))
2116 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
2117 else
2118 regaddr = IT87_REG_AUTO_PWM(nr, point);
2119 - it87_write_value(data, regaddr, data->auto_pwm[nr][point]);
2120 - mutex_unlock(&data->update_lock);
2121 + data->write(data, regaddr, data->auto_pwm[nr][point]);
2122 + it87_unlock(data);
2123 return count;
2124 }
2125
2126 @@ -1558,6 +2105,9 @@
2127 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2128 int nr = sensor_attr->index;
2129
2130 + if (IS_ERR(data))
2131 + return PTR_ERR(data);
2132 +
2133 return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
2134 }
2135
2136 @@ -1569,15 +2119,18 @@
2137 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2138 int nr = sensor_attr->index;
2139 unsigned long val;
2140 + int err;
2141
2142 if (kstrtoul(buf, 10, &val) < 0 || val > 127)
2143 return -EINVAL;
2144
2145 - mutex_lock(&data->update_lock);
2146 + err = it87_lock(data);
2147 + if (err)
2148 + return err;
2149 +
2150 data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
2151 - it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4),
2152 - data->auto_pwm[nr][1]);
2153 - mutex_unlock(&data->update_lock);
2154 + data->write(data, IT87_REG_AUTO_TEMP(nr, 4), data->auto_pwm[nr][1]);
2155 + it87_unlock(data);
2156 return count;
2157 }
2158
2159 @@ -1591,6 +2144,9 @@
2160 int point = sensor_attr->index;
2161 int reg;
2162
2163 + if (IS_ERR(data))
2164 + return PTR_ERR(data);
2165 +
2166 if (has_old_autopwm(data) || point)
2167 reg = data->auto_temp[nr][point];
2168 else
2169 @@ -1609,211 +2165,208 @@
2170 int point = sensor_attr->index;
2171 long val;
2172 int reg;
2173 + int err;
2174
2175 if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
2176 return -EINVAL;
2177
2178 - mutex_lock(&data->update_lock);
2179 + err = it87_lock(data);
2180 + if (err)
2181 + return err;
2182 +
2183 if (has_newer_autopwm(data) && !point) {
2184 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
2185 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
2186 data->auto_temp[nr][0] = reg;
2187 - it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
2188 + data->write(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
2189 } else {
2190 reg = TEMP_TO_REG(val);
2191 data->auto_temp[nr][point] = reg;
2192 if (has_newer_autopwm(data))
2193 point--;
2194 - it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg);
2195 + data->write(data, IT87_REG_AUTO_TEMP(nr, point), reg);
2196 }
2197 - mutex_unlock(&data->update_lock);
2198 + it87_unlock(data);
2199 return count;
2200 }
2201
2202 -static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
2203 -static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2204 - 0, 1);
2205 -static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
2206 - set_fan_div, 0);
2207 -
2208 -static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
2209 -static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2210 - 1, 1);
2211 -static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
2212 - set_fan_div, 1);
2213 -
2214 -static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
2215 -static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2216 - 2, 1);
2217 -static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
2218 - set_fan_div, 2);
2219 -
2220 -static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
2221 -static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2222 - 3, 1);
2223 -
2224 -static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
2225 -static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2226 - 4, 1);
2227 -
2228 -static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0);
2229 -static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2230 - 5, 1);
2231 +static SENSOR_DEVICE_ATTR_2(fan1_input, 0444, show_fan, NULL, 0, 0);
2232 +static SENSOR_DEVICE_ATTR_2(fan1_min, 0644, show_fan, set_fan, 0, 1);
2233 +static SENSOR_DEVICE_ATTR(fan1_div, 0644, show_fan_div, set_fan_div, 0);
2234 +
2235 +static SENSOR_DEVICE_ATTR_2(fan2_input, 0444, show_fan, NULL, 1, 0);
2236 +static SENSOR_DEVICE_ATTR_2(fan2_min, 0644, show_fan, set_fan, 1, 1);
2237 +static SENSOR_DEVICE_ATTR(fan2_div, 0644, show_fan_div, set_fan_div, 1);
2238 +
2239 +static SENSOR_DEVICE_ATTR_2(fan3_input, 0444, show_fan, NULL, 2, 0);
2240 +static SENSOR_DEVICE_ATTR_2(fan3_min, 0644, show_fan, set_fan, 2, 1);
2241 +static SENSOR_DEVICE_ATTR(fan3_div, 0644, show_fan_div, set_fan_div, 2);
2242 +
2243 +static SENSOR_DEVICE_ATTR_2(fan4_input, 0444, show_fan, NULL, 3, 0);
2244 +static SENSOR_DEVICE_ATTR_2(fan4_min, 0644, show_fan, set_fan, 3, 1);
2245
2246 -static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
2247 +static SENSOR_DEVICE_ATTR_2(fan5_input, 0444, show_fan, NULL, 4, 0);
2248 +static SENSOR_DEVICE_ATTR_2(fan5_min, 0644, show_fan, set_fan, 4, 1);
2249 +
2250 +static SENSOR_DEVICE_ATTR_2(fan6_input, 0444, show_fan, NULL, 5, 0);
2251 +static SENSOR_DEVICE_ATTR_2(fan6_min, 0644, show_fan, set_fan, 5, 1);
2252 +
2253 +static SENSOR_DEVICE_ATTR(pwm1_enable, 0644,
2254 show_pwm_enable, set_pwm_enable, 0);
2255 -static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
2256 -static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq,
2257 - set_pwm_freq, 0);
2258 -static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO,
2259 +static SENSOR_DEVICE_ATTR(pwm1, 0644, show_pwm, set_pwm, 0);
2260 +static SENSOR_DEVICE_ATTR(pwm1_freq, 0644, show_pwm_freq, set_pwm_freq, 0);
2261 +static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, 0444,
2262 show_pwm_temp_map, set_pwm_temp_map, 0);
2263 -static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
2264 +static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, 0644,
2265 show_auto_pwm, set_auto_pwm, 0, 0);
2266 -static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
2267 +static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, 0644,
2268 show_auto_pwm, set_auto_pwm, 0, 1);
2269 -static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
2270 +static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, 0644,
2271 show_auto_pwm, set_auto_pwm, 0, 2);
2272 -static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
2273 +static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, 0444,
2274 show_auto_pwm, NULL, 0, 3);
2275 -static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
2276 +static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, 0644,
2277 show_auto_temp, set_auto_temp, 0, 1);
2278 -static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2279 +static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, 0644,
2280 show_auto_temp, set_auto_temp, 0, 0);
2281 -static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
2282 +static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, 0644,
2283 show_auto_temp, set_auto_temp, 0, 2);
2284 -static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
2285 +static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, 0644,
2286 show_auto_temp, set_auto_temp, 0, 3);
2287 -static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
2288 +static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, 0644,
2289 show_auto_temp, set_auto_temp, 0, 4);
2290 -static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR,
2291 +static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, 0644,
2292 show_auto_pwm, set_auto_pwm, 0, 0);
2293 -static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR,
2294 +static SENSOR_DEVICE_ATTR(pwm1_auto_slope, 0644,
2295 show_auto_pwm_slope, set_auto_pwm_slope, 0);
2296
2297 -static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
2298 +static SENSOR_DEVICE_ATTR(pwm2_enable, 0644,
2299 show_pwm_enable, set_pwm_enable, 1);
2300 -static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
2301 -static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1);
2302 -static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO,
2303 +static SENSOR_DEVICE_ATTR(pwm2, 0644, show_pwm, set_pwm, 1);
2304 +static SENSOR_DEVICE_ATTR(pwm2_freq, 0444, show_pwm_freq, set_pwm_freq, 1);
2305 +static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, 0444,
2306 show_pwm_temp_map, set_pwm_temp_map, 1);
2307 -static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
2308 +static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, 0644,
2309 show_auto_pwm, set_auto_pwm, 1, 0);
2310 -static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
2311 +static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, 0644,
2312 show_auto_pwm, set_auto_pwm, 1, 1);
2313 -static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
2314 +static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, 0644,
2315 show_auto_pwm, set_auto_pwm, 1, 2);
2316 -static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
2317 +static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, 0444,
2318 show_auto_pwm, NULL, 1, 3);
2319 -static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
2320 +static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, 0644,
2321 show_auto_temp, set_auto_temp, 1, 1);
2322 -static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2323 +static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, 0644,
2324 show_auto_temp, set_auto_temp, 1, 0);
2325 -static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
2326 +static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, 0644,
2327 show_auto_temp, set_auto_temp, 1, 2);
2328 -static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
2329 +static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, 0644,
2330 show_auto_temp, set_auto_temp, 1, 3);
2331 -static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
2332 +static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, 0644,
2333 show_auto_temp, set_auto_temp, 1, 4);
2334 -static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR,
2335 +static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, 0644,
2336 show_auto_pwm, set_auto_pwm, 1, 0);
2337 -static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR,
2338 +static SENSOR_DEVICE_ATTR(pwm2_auto_slope, 0644,
2339 show_auto_pwm_slope, set_auto_pwm_slope, 1);
2340
2341 -static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
2342 +static SENSOR_DEVICE_ATTR(pwm3_enable, 0644,
2343 show_pwm_enable, set_pwm_enable, 2);
2344 -static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
2345 -static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2);
2346 -static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO,
2347 +static SENSOR_DEVICE_ATTR(pwm3, 0644, show_pwm, set_pwm, 2);
2348 +static SENSOR_DEVICE_ATTR(pwm3_freq, 0444, show_pwm_freq, NULL, 2);
2349 +static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, 0444,
2350 show_pwm_temp_map, set_pwm_temp_map, 2);
2351 -static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
2352 +static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, 0644,
2353 show_auto_pwm, set_auto_pwm, 2, 0);
2354 -static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
2355 +static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, 0644,
2356 show_auto_pwm, set_auto_pwm, 2, 1);
2357 -static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
2358 +static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, 0644,
2359 show_auto_pwm, set_auto_pwm, 2, 2);
2360 -static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
2361 +static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, 0444,
2362 show_auto_pwm, NULL, 2, 3);
2363 -static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
2364 +static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, 0644,
2365 show_auto_temp, set_auto_temp, 2, 1);
2366 -static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2367 +static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, 0644,
2368 show_auto_temp, set_auto_temp, 2, 0);
2369 -static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
2370 +static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, 0644,
2371 show_auto_temp, set_auto_temp, 2, 2);
2372 -static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
2373 +static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, 0644,
2374 show_auto_temp, set_auto_temp, 2, 3);
2375 -static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
2376 +static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, 0644,
2377 show_auto_temp, set_auto_temp, 2, 4);
2378 -static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR,
2379 +static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, 0644,
2380 show_auto_pwm, set_auto_pwm, 2, 0);
2381 -static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR,
2382 +static SENSOR_DEVICE_ATTR(pwm3_auto_slope, 0644,
2383 show_auto_pwm_slope, set_auto_pwm_slope, 2);
2384
2385 -static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR,
2386 +static SENSOR_DEVICE_ATTR(pwm4_enable, 0644,
2387 show_pwm_enable, set_pwm_enable, 3);
2388 -static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3);
2389 -static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3);
2390 -static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO,
2391 +static SENSOR_DEVICE_ATTR(pwm4, 0644, show_pwm, set_pwm, 3);
2392 +static SENSOR_DEVICE_ATTR(pwm4_freq, 0444, show_pwm_freq, NULL, 3);
2393 +static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, 0444,
2394 show_pwm_temp_map, set_pwm_temp_map, 3);
2395 -static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR,
2396 +static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, 0644,
2397 show_auto_temp, set_auto_temp, 2, 1);
2398 -static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2399 +static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, 0644,
2400 show_auto_temp, set_auto_temp, 2, 0);
2401 -static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR,
2402 +static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, 0644,
2403 show_auto_temp, set_auto_temp, 2, 2);
2404 -static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR,
2405 +static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, 0644,
2406 show_auto_temp, set_auto_temp, 2, 3);
2407 -static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR,
2408 +static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, 0644,
2409 show_auto_pwm, set_auto_pwm, 3, 0);
2410 -static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR,
2411 +static SENSOR_DEVICE_ATTR(pwm4_auto_slope, 0644,
2412 show_auto_pwm_slope, set_auto_pwm_slope, 3);
2413
2414 -static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR,
2415 +static SENSOR_DEVICE_ATTR(pwm5_enable, 0644,
2416 show_pwm_enable, set_pwm_enable, 4);
2417 -static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4);
2418 -static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4);
2419 -static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO,
2420 +static SENSOR_DEVICE_ATTR(pwm5, 0644, show_pwm, set_pwm, 4);
2421 +static SENSOR_DEVICE_ATTR(pwm5_freq, 0444, show_pwm_freq, NULL, 4);
2422 +static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, 0444,
2423 show_pwm_temp_map, set_pwm_temp_map, 4);
2424 -static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR,
2425 +static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, 0644,
2426 show_auto_temp, set_auto_temp, 2, 1);
2427 -static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2428 +static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, 0644,
2429 show_auto_temp, set_auto_temp, 2, 0);
2430 -static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR,
2431 +static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, 0644,
2432 show_auto_temp, set_auto_temp, 2, 2);
2433 -static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR,
2434 +static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, 0644,
2435 show_auto_temp, set_auto_temp, 2, 3);
2436 -static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR,
2437 +static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, 0644,
2438 show_auto_pwm, set_auto_pwm, 4, 0);
2439 -static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR,
2440 +static SENSOR_DEVICE_ATTR(pwm5_auto_slope, 0644,
2441 show_auto_pwm_slope, set_auto_pwm_slope, 4);
2442
2443 -static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR,
2444 +static SENSOR_DEVICE_ATTR(pwm6_enable, 0644,
2445 show_pwm_enable, set_pwm_enable, 5);
2446 -static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5);
2447 -static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5);
2448 -static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO,
2449 +static SENSOR_DEVICE_ATTR(pwm6, 0644, show_pwm, set_pwm, 5);
2450 +static SENSOR_DEVICE_ATTR(pwm6_freq, 0444, show_pwm_freq, NULL, 5);
2451 +static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, 0444,
2452 show_pwm_temp_map, set_pwm_temp_map, 5);
2453 -static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR,
2454 +static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, 0644,
2455 show_auto_temp, set_auto_temp, 2, 1);
2456 -static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2457 +static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, 0644,
2458 show_auto_temp, set_auto_temp, 2, 0);
2459 -static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR,
2460 +static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, 0644,
2461 show_auto_temp, set_auto_temp, 2, 2);
2462 -static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR,
2463 +static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, 0644,
2464 show_auto_temp, set_auto_temp, 2, 3);
2465 -static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR,
2466 +static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, 0644,
2467 show_auto_pwm, set_auto_pwm, 5, 0);
2468 -static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR,
2469 +static SENSOR_DEVICE_ATTR(pwm6_auto_slope, 0644,
2470 show_auto_pwm_slope, set_auto_pwm_slope, 5);
2471
2472 /* Alarms */
2473 -static ssize_t alarms_show(struct device *dev, struct device_attribute *attr,
2474 +static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
2475 char *buf)
2476 {
2477 struct it87_data *data = it87_update_device(dev);
2478
2479 + if (IS_ERR(data))
2480 + return PTR_ERR(data);
2481 +
2482 return sprintf(buf, "%u\n", data->alarms);
2483 }
2484 -static DEVICE_ATTR_RO(alarms);
2485 +static DEVICE_ATTR(alarms, 0444, show_alarms, NULL);
2486
2487 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
2488 char *buf)
2489 @@ -1821,6 +2374,9 @@
2490 struct it87_data *data = it87_update_device(dev);
2491 int bitnr = to_sensor_dev_attr(attr)->index;
2492
2493 + if (IS_ERR(data))
2494 + return PTR_ERR(data);
2495 +
2496 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
2497 }
2498
2499 @@ -1829,45 +2385,46 @@
2500 size_t count)
2501 {
2502 struct it87_data *data = dev_get_drvdata(dev);
2503 - int config;
2504 + int err, config;
2505 long val;
2506
2507 if (kstrtol(buf, 10, &val) < 0 || val != 0)
2508 return -EINVAL;
2509
2510 - mutex_lock(&data->update_lock);
2511 - config = it87_read_value(data, IT87_REG_CONFIG);
2512 - if (config < 0) {
2513 - count = config;
2514 - } else {
2515 - config |= BIT(5);
2516 - it87_write_value(data, IT87_REG_CONFIG, config);
2517 - /* Invalidate cache to force re-read */
2518 - data->valid = false;
2519 - }
2520 - mutex_unlock(&data->update_lock);
2521 + err = it87_lock(data);
2522 + if (err)
2523 + return err;
2524
2525 + config = data->read(data, IT87_REG_CONFIG);
2526 + config |= BIT(5);
2527 + data->write(data, IT87_REG_CONFIG, config);
2528 + /* Invalidate cache to force re-read */
2529 + data->valid = false;
2530 + it87_unlock(data);
2531 return count;
2532 }
2533
2534 -static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
2535 -static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
2536 -static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
2537 -static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
2538 -static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
2539 -static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
2540 -static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
2541 -static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
2542 -static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
2543 -static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
2544 -static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
2545 -static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
2546 -static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
2547 -static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7);
2548 -static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
2549 -static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
2550 -static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
2551 -static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
2552 +static SENSOR_DEVICE_ATTR(in0_alarm, 0444, show_alarm, NULL, 8);
2553 +static SENSOR_DEVICE_ATTR(in1_alarm, 0444, show_alarm, NULL, 9);
2554 +static SENSOR_DEVICE_ATTR(in2_alarm, 0444, show_alarm, NULL, 10);
2555 +static SENSOR_DEVICE_ATTR(in3_alarm, 0444, show_alarm, NULL, 11);
2556 +static SENSOR_DEVICE_ATTR(in4_alarm, 0444, show_alarm, NULL, 12);
2557 +static SENSOR_DEVICE_ATTR(in5_alarm, 0444, show_alarm, NULL, 13);
2558 +static SENSOR_DEVICE_ATTR(in6_alarm, 0444, show_alarm, NULL, 14);
2559 +static SENSOR_DEVICE_ATTR(in7_alarm, 0444, show_alarm, NULL, 15);
2560 +static SENSOR_DEVICE_ATTR(fan1_alarm, 0444, show_alarm, NULL, 0);
2561 +static SENSOR_DEVICE_ATTR(fan2_alarm, 0444, show_alarm, NULL, 1);
2562 +static SENSOR_DEVICE_ATTR(fan3_alarm, 0444, show_alarm, NULL, 2);
2563 +static SENSOR_DEVICE_ATTR(fan4_alarm, 0444, show_alarm, NULL, 3);
2564 +static SENSOR_DEVICE_ATTR(fan5_alarm, 0444, show_alarm, NULL, 6);
2565 +static SENSOR_DEVICE_ATTR(fan6_alarm, 0444, show_alarm, NULL, 7);
2566 +static SENSOR_DEVICE_ATTR(temp1_alarm, 0444, show_alarm, NULL, 16);
2567 +static SENSOR_DEVICE_ATTR(temp2_alarm, 0444, show_alarm, NULL, 17);
2568 +static SENSOR_DEVICE_ATTR(temp3_alarm, 0444, show_alarm, NULL, 18);
2569 +static SENSOR_DEVICE_ATTR(temp4_alarm, 0444, show_alarm, NULL, 19);
2570 +static SENSOR_DEVICE_ATTR(temp5_alarm, 0444, show_alarm, NULL, 20);
2571 +static SENSOR_DEVICE_ATTR(temp6_alarm, 0444, show_alarm, NULL, 21);
2572 +static SENSOR_DEVICE_ATTR(intrusion0_alarm, 0644,
2573 show_alarm, clear_intrusion, 4);
2574
2575 static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
2576 @@ -1876,6 +2433,9 @@
2577 struct it87_data *data = it87_update_device(dev);
2578 int bitnr = to_sensor_dev_attr(attr)->index;
2579
2580 + if (IS_ERR(data))
2581 + return PTR_ERR(data);
2582 +
2583 return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
2584 }
2585
2586 @@ -1885,52 +2445,59 @@
2587 int bitnr = to_sensor_dev_attr(attr)->index;
2588 struct it87_data *data = dev_get_drvdata(dev);
2589 long val;
2590 + int err;
2591
2592 if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
2593 return -EINVAL;
2594
2595 - mutex_lock(&data->update_lock);
2596 - data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
2597 + err = it87_lock(data);
2598 + if (err)
2599 + return err;
2600 +
2601 + data->beeps = data->read(data, IT87_REG_BEEP_ENABLE);
2602 if (val)
2603 data->beeps |= BIT(bitnr);
2604 else
2605 data->beeps &= ~BIT(bitnr);
2606 - it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
2607 - mutex_unlock(&data->update_lock);
2608 + data->write(data, IT87_REG_BEEP_ENABLE, data->beeps);
2609 + it87_unlock(data);
2610 return count;
2611 }
2612
2613 -static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
2614 +static SENSOR_DEVICE_ATTR(in0_beep, 0644,
2615 show_beep, set_beep, 1);
2616 -static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
2617 -static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
2618 -static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
2619 -static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
2620 -static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
2621 -static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
2622 -static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
2623 +static SENSOR_DEVICE_ATTR(in1_beep, 0444, show_beep, NULL, 1);
2624 +static SENSOR_DEVICE_ATTR(in2_beep, 0444, show_beep, NULL, 1);
2625 +static SENSOR_DEVICE_ATTR(in3_beep, 0444, show_beep, NULL, 1);
2626 +static SENSOR_DEVICE_ATTR(in4_beep, 0444, show_beep, NULL, 1);
2627 +static SENSOR_DEVICE_ATTR(in5_beep, 0444, show_beep, NULL, 1);
2628 +static SENSOR_DEVICE_ATTR(in6_beep, 0444, show_beep, NULL, 1);
2629 +static SENSOR_DEVICE_ATTR(in7_beep, 0444, show_beep, NULL, 1);
2630 /* fanX_beep writability is set later */
2631 -static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
2632 -static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
2633 -static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
2634 -static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
2635 -static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
2636 -static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0);
2637 -static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
2638 +static SENSOR_DEVICE_ATTR(fan1_beep, 0444, show_beep, set_beep, 0);
2639 +static SENSOR_DEVICE_ATTR(fan2_beep, 0444, show_beep, set_beep, 0);
2640 +static SENSOR_DEVICE_ATTR(fan3_beep, 0444, show_beep, set_beep, 0);
2641 +static SENSOR_DEVICE_ATTR(fan4_beep, 0444, show_beep, set_beep, 0);
2642 +static SENSOR_DEVICE_ATTR(fan5_beep, 0444, show_beep, set_beep, 0);
2643 +static SENSOR_DEVICE_ATTR(fan6_beep, 0444, show_beep, set_beep, 0);
2644 +static SENSOR_DEVICE_ATTR(temp1_beep, 0644,
2645 show_beep, set_beep, 2);
2646 -static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
2647 -static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
2648 +static SENSOR_DEVICE_ATTR(temp2_beep, 0444, show_beep, NULL, 2);
2649 +static SENSOR_DEVICE_ATTR(temp3_beep, 0444, show_beep, NULL, 2);
2650 +static SENSOR_DEVICE_ATTR(temp4_beep, 0444, show_beep, NULL, 2);
2651 +static SENSOR_DEVICE_ATTR(temp5_beep, 0444, show_beep, NULL, 2);
2652 +static SENSOR_DEVICE_ATTR(temp6_beep, 0444, show_beep, NULL, 2);
2653
2654 -static ssize_t vrm_show(struct device *dev, struct device_attribute *attr,
2655 - char *buf)
2656 +static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
2657 + char *buf)
2658 {
2659 struct it87_data *data = dev_get_drvdata(dev);
2660
2661 return sprintf(buf, "%u\n", data->vrm);
2662 }
2663
2664 -static ssize_t vrm_store(struct device *dev, struct device_attribute *attr,
2665 - const char *buf, size_t count)
2666 +static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
2667 + const char *buf, size_t count)
2668 {
2669 struct it87_data *data = dev_get_drvdata(dev);
2670 unsigned long val;
2671 @@ -1942,16 +2509,19 @@
2672
2673 return count;
2674 }
2675 -static DEVICE_ATTR_RW(vrm);
2676 +static DEVICE_ATTR(vrm, 0644, show_vrm_reg, store_vrm_reg);
2677
2678 -static ssize_t cpu0_vid_show(struct device *dev,
2679 - struct device_attribute *attr, char *buf)
2680 +static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
2681 + char *buf)
2682 {
2683 struct it87_data *data = it87_update_device(dev);
2684
2685 + if (IS_ERR(data))
2686 + return PTR_ERR(data);
2687 +
2688 return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
2689 }
2690 -static DEVICE_ATTR_RO(cpu0_vid);
2691 +static DEVICE_ATTR(cpu0_vid, 0444, show_vid_reg, NULL);
2692
2693 static ssize_t show_label(struct device *dev, struct device_attribute *attr,
2694 char *buf)
2695 @@ -1974,18 +2544,19 @@
2696
2697 if (has_vin3_5v(data) && nr == 0)
2698 label = labels[0];
2699 - else if (has_12mv_adc(data) || has_10_9mv_adc(data))
2700 + else if (has_12mv_adc(data) || has_10_9mv_adc(data) ||
2701 + has_11mv_adc(data))
2702 label = labels_it8721[nr];
2703 else
2704 label = labels[nr];
2705
2706 return sprintf(buf, "%s\n", label);
2707 }
2708 -static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
2709 -static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
2710 -static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
2711 +static SENSOR_DEVICE_ATTR(in3_label, 0444, show_label, NULL, 0);
2712 +static SENSOR_DEVICE_ATTR(in7_label, 0444, show_label, NULL, 1);
2713 +static SENSOR_DEVICE_ATTR(in8_label, 0444, show_label, NULL, 2);
2714 /* AVCC3 */
2715 -static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3);
2716 +static SENSOR_DEVICE_ATTR(in9_label, 0444, show_label, NULL, 3);
2717
2718 static umode_t it87_in_is_visible(struct kobject *kobj,
2719 struct attribute *attr, int index)
2720 @@ -2059,10 +2630,10 @@
2721 &sensor_dev_attr_in7_beep.dev_attr.attr, /* 39 */
2722
2723 &sensor_dev_attr_in8_input.dev_attr.attr, /* 40 */
2724 - &sensor_dev_attr_in9_input.dev_attr.attr,
2725 - &sensor_dev_attr_in10_input.dev_attr.attr,
2726 - &sensor_dev_attr_in11_input.dev_attr.attr,
2727 - &sensor_dev_attr_in12_input.dev_attr.attr,
2728 + &sensor_dev_attr_in9_input.dev_attr.attr, /* 41 */
2729 + &sensor_dev_attr_in10_input.dev_attr.attr, /* 42 */
2730 + &sensor_dev_attr_in11_input.dev_attr.attr, /* 43 */
2731 + &sensor_dev_attr_in12_input.dev_attr.attr, /* 44 */
2732 NULL
2733 };
2734
2735 @@ -2079,15 +2650,23 @@
2736 int i = index / 7; /* temperature index */
2737 int a = index % 7; /* attribute index */
2738
2739 - if (index >= 21) {
2740 - i = index - 21 + 3;
2741 - a = 0;
2742 - }
2743 -
2744 if (!(data->has_temp & BIT(i)))
2745 return 0;
2746
2747 - if (a == 5 && !has_temp_offset(data))
2748 + if (a && i >= data->num_temp_limit)
2749 + return 0;
2750 +
2751 + if (a == 3) {
2752 + int type = get_temp_type(data, i);
2753 +
2754 + if (type == 0)
2755 + return 0;
2756 + if (has_bank_sel(data))
2757 + return 0444;
2758 + return attr->mode;
2759 + }
2760 +
2761 + if (a == 5 && i >= data->num_temp_offset)
2762 return 0;
2763
2764 if (a == 6 && !data->has_beep)
2765 @@ -2100,7 +2679,7 @@
2766 &sensor_dev_attr_temp1_input.dev_attr.attr,
2767 &sensor_dev_attr_temp1_max.dev_attr.attr,
2768 &sensor_dev_attr_temp1_min.dev_attr.attr,
2769 - &sensor_dev_attr_temp1_type.dev_attr.attr,
2770 + &sensor_dev_attr_temp1_type.dev_attr.attr, /* 3 */
2771 &sensor_dev_attr_temp1_alarm.dev_attr.attr,
2772 &sensor_dev_attr_temp1_offset.dev_attr.attr, /* 5 */
2773 &sensor_dev_attr_temp1_beep.dev_attr.attr, /* 6 */
2774 @@ -2122,8 +2701,28 @@
2775 &sensor_dev_attr_temp3_beep.dev_attr.attr,
2776
2777 &sensor_dev_attr_temp4_input.dev_attr.attr, /* 21 */
2778 + &sensor_dev_attr_temp4_max.dev_attr.attr,
2779 + &sensor_dev_attr_temp4_min.dev_attr.attr,
2780 + &sensor_dev_attr_temp4_type.dev_attr.attr,
2781 + &sensor_dev_attr_temp4_alarm.dev_attr.attr,
2782 + &sensor_dev_attr_temp4_offset.dev_attr.attr,
2783 + &sensor_dev_attr_temp4_beep.dev_attr.attr,
2784 +
2785 &sensor_dev_attr_temp5_input.dev_attr.attr,
2786 + &sensor_dev_attr_temp5_max.dev_attr.attr,
2787 + &sensor_dev_attr_temp5_min.dev_attr.attr,
2788 + &sensor_dev_attr_temp5_type.dev_attr.attr,
2789 + &sensor_dev_attr_temp5_alarm.dev_attr.attr,
2790 + &sensor_dev_attr_temp5_offset.dev_attr.attr,
2791 + &sensor_dev_attr_temp5_beep.dev_attr.attr,
2792 +
2793 &sensor_dev_attr_temp6_input.dev_attr.attr,
2794 + &sensor_dev_attr_temp6_max.dev_attr.attr,
2795 + &sensor_dev_attr_temp6_min.dev_attr.attr,
2796 + &sensor_dev_attr_temp6_type.dev_attr.attr,
2797 + &sensor_dev_attr_temp6_alarm.dev_attr.attr,
2798 + &sensor_dev_attr_temp6_offset.dev_attr.attr,
2799 + &sensor_dev_attr_temp6_beep.dev_attr.attr,
2800 NULL
2801 };
2802
2803 @@ -2185,7 +2784,7 @@
2804 return 0;
2805 /* first fan beep attribute is writable */
2806 if (i == __ffs(data->has_fan))
2807 - return attr->mode | S_IWUSR;
2808 + return attr->mode | 0200;
2809 }
2810
2811 if (a == 4 && has_16bit_fans(data)) /* divisor */
2812 @@ -2248,11 +2847,11 @@
2813
2814 /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2815 if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2816 - return attr->mode | S_IWUSR;
2817 + return attr->mode | 0200;
2818
2819 /* pwm2_freq is writable if there are two pwm frequency selects */
2820 if (has_pwm_freq2(data) && i == 1 && a == 2)
2821 - return attr->mode | S_IWUSR;
2822 + return attr->mode | 0200;
2823
2824 return attr->mode;
2825 }
2826 @@ -2394,19 +2993,29 @@
2827
2828 /* SuperIO detection - will change isa_address if a chip is found */
2829 static int __init it87_find(int sioaddr, unsigned short *address,
2830 + phys_addr_t *mmio_address,
2831 struct it87_sio_data *sio_data)
2832 {
2833 - int err;
2834 - u16 chip_type;
2835 - const char *board_vendor, *board_name;
2836 const struct it87_devices *config;
2837 + phys_addr_t base = 0;
2838 + bool doexit = true;
2839 + char mmio_str[32];
2840 + u16 chip_type;
2841 + int err;
2842
2843 err = superio_enter(sioaddr);
2844 if (err)
2845 return err;
2846
2847 + sio_data->sioaddr = sioaddr;
2848 +
2849 err = -ENODEV;
2850 - chip_type = force_id ? force_id : superio_inw(sioaddr, DEVID);
2851 + chip_type = superio_inw(sioaddr, DEVID);
2852 + if (chip_type == 0xffff)
2853 + goto exit;
2854 +
2855 + if (force_id)
2856 + chip_type = force_id;
2857
2858 switch (chip_type) {
2859 case IT8705F_DEVID:
2860 @@ -2434,8 +3043,21 @@
2861 case IT8732F_DEVID:
2862 sio_data->type = it8732;
2863 break;
2864 + case IT8736F_DEVID:
2865 + sio_data->type = it8736;
2866 + break;
2867 + case IT8738E_DEVID:
2868 + sio_data->type = it8738;
2869 + break;
2870 case IT8792E_DEVID:
2871 sio_data->type = it8792;
2872 + /*
2873 + * Disabling configuration mode on IT8792E can result in system
2874 + * hang-ups and access failures to the Super-IO chip at the
2875 + * second SIO address. Never exit configuration mode on this
2876 + * chip to avoid the problem.
2877 + */
2878 + doexit = false;
2879 break;
2880 case IT8771E_DEVID:
2881 sio_data->type = it8771;
2882 @@ -2457,20 +3079,42 @@
2883 break;
2884 case IT8790E_DEVID:
2885 sio_data->type = it8790;
2886 + doexit = false; /* See IT8792E comment above */
2887 break;
2888 case IT8603E_DEVID:
2889 case IT8623E_DEVID:
2890 sio_data->type = it8603;
2891 break;
2892 + case IT8606E_DEVID:
2893 + sio_data->type = it8606;
2894 + break;
2895 + case IT8607E_DEVID:
2896 + sio_data->type = it8607;
2897 + break;
2898 + case IT8613E_DEVID:
2899 + sio_data->type = it8613;
2900 + break;
2901 case IT8620E_DEVID:
2902 sio_data->type = it8620;
2903 break;
2904 case IT8622E_DEVID:
2905 sio_data->type = it8622;
2906 break;
2907 + case IT8625E_DEVID:
2908 + sio_data->type = it8625;
2909 + break;
2910 case IT8628E_DEVID:
2911 sio_data->type = it8628;
2912 break;
2913 + case IT8655E_DEVID:
2914 + sio_data->type = it8655;
2915 + break;
2916 + case IT8665E_DEVID:
2917 + sio_data->type = it8665;
2918 + break;
2919 + case IT8686E_DEVID:
2920 + sio_data->type = it8686;
2921 + break;
2922 case 0xffff: /* No device at all */
2923 goto exit;
2924 default:
2925 @@ -2490,15 +3134,32 @@
2926 goto exit;
2927 }
2928
2929 + sio_data->doexit = doexit;
2930 +
2931 err = 0;
2932 - sio_data->sioaddr = sioaddr;
2933 sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
2934 - pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type,
2935 - it87_devices[sio_data->type].suffix,
2936 - *address, sio_data->revision);
2937
2938 config = &it87_devices[sio_data->type];
2939
2940 + if (has_mmio(config) && mmio) {
2941 + u8 reg;
2942 +
2943 + reg = superio_inb(sioaddr, IT87_EC_HWM_MIO_REG);
2944 + if (reg & BIT(5)) {
2945 + base = 0xf0000000 + ((reg & 0x0f) << 24);
2946 + base += (reg & 0xc0) << 14;
2947 + }
2948 + }
2949 + *mmio_address = base;
2950 +
2951 + mmio_str[0] = '\0';
2952 + if (base)
2953 + snprintf(mmio_str, sizeof(mmio_str), " [MMIO at %pa]", &base);
2954 +
2955 + pr_info("Found %s chip at 0x%x%s, revision %d\n",
2956 + it87_devices[sio_data->type].model,
2957 + *address, mmio_str, sio_data->revision);
2958 +
2959 /* in7 (VSB or VCCH5V) is always internal on some chips */
2960 if (has_in7_internal(config))
2961 sio_data->internal |= BIT(1);
2962 @@ -2512,8 +3173,10 @@
2963 else
2964 sio_data->skip_in |= BIT(9);
2965
2966 - if (!has_five_pwm(config))
2967 + if (!has_four_pwm(config))
2968 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
2969 + else if (!has_five_pwm(config))
2970 + sio_data->skip_pwm |= BIT(4) | BIT(5);
2971 else if (!has_six_pwm(config))
2972 sio_data->skip_pwm |= BIT(5);
2973
2974 @@ -2580,7 +3243,6 @@
2975 reg2c |= BIT(1);
2976 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
2977 reg2c);
2978 - sio_data->need_in7_reroute = true;
2979 pr_notice("Routing internal VCCH5V to in7.\n");
2980 }
2981 pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
2982 @@ -2594,7 +3256,8 @@
2983
2984 sio_data->beep_pin = superio_inb(sioaddr,
2985 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2986 - } else if (sio_data->type == it8603) {
2987 + } else if (sio_data->type == it8603 || sio_data->type == it8606 ||
2988 + sio_data->type == it8607) {
2989 int reg27, reg29;
2990
2991 superio_select(sioaddr, GPIO);
2992 @@ -2614,12 +3277,59 @@
2993 if (reg29 & BIT(2))
2994 sio_data->skip_fan |= BIT(1);
2995
2996 - sio_data->skip_in |= BIT(5); /* No VIN5 */
2997 - sio_data->skip_in |= BIT(6); /* No VIN6 */
2998 + switch (sio_data->type) {
2999 + case it8603:
3000 + sio_data->skip_in |= BIT(5); /* No VIN5 */
3001 + sio_data->skip_in |= BIT(6); /* No VIN6 */
3002 + break;
3003 + case it8607:
3004 + sio_data->skip_pwm |= BIT(0);/* No fan1 */
3005 + sio_data->skip_fan |= BIT(0);
3006 + default:
3007 + break;
3008 + }
3009 +
3010 + sio_data->beep_pin = superio_inb(sioaddr,
3011 + IT87_SIO_BEEP_PIN_REG) & 0x3f;
3012 + } else if (sio_data->type == it8613) {
3013 + int reg27, reg29, reg2a;
3014 +
3015 + superio_select(sioaddr, GPIO);
3016 +
3017 + /* Check for pwm3, fan3, pwm5, fan5 */
3018 + reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3019 + if (reg27 & BIT(1))
3020 + sio_data->skip_fan |= BIT(4);
3021 + if (reg27 & BIT(3))
3022 + sio_data->skip_pwm |= BIT(4);
3023 + if (reg27 & BIT(6))
3024 + sio_data->skip_pwm |= BIT(2);
3025 + if (reg27 & BIT(7))
3026 + sio_data->skip_fan |= BIT(2);
3027 +
3028 + /* Check for pwm2, fan2 */
3029 + reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3030 + if (reg29 & BIT(1))
3031 + sio_data->skip_pwm |= BIT(1);
3032 + if (reg29 & BIT(2))
3033 + sio_data->skip_fan |= BIT(1);
3034 +
3035 + /* Check for pwm4, fan4 */
3036 + reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3037 + if (!(reg2a & BIT(0)) || (reg29 & BIT(7))) {
3038 + sio_data->skip_fan |= BIT(3);
3039 + sio_data->skip_pwm |= BIT(3);
3040 + }
3041 +
3042 + sio_data->skip_pwm |= BIT(0); /* No pwm1 */
3043 + sio_data->skip_fan |= BIT(0); /* No fan1 */
3044 + sio_data->skip_in |= BIT(3); /* No VIN3 */
3045 + sio_data->skip_in |= BIT(6); /* No VIN6 */
3046
3047 sio_data->beep_pin = superio_inb(sioaddr,
3048 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3049 - } else if (sio_data->type == it8620 || sio_data->type == it8628) {
3050 + } else if (sio_data->type == it8620 || sio_data->type == it8628 ||
3051 + sio_data->type == it8686) {
3052 int reg;
3053
3054 superio_select(sioaddr, GPIO);
3055 @@ -2662,10 +3372,14 @@
3056
3057 /* Check if AVCC is on VIN3 */
3058 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3059 - if (reg & BIT(0))
3060 - sio_data->internal |= BIT(0);
3061 - else
3062 + if (reg & BIT(0)) {
3063 + /* For it8686, the bit just enables AVCC3 */
3064 + if (sio_data->type != it8686)
3065 + sio_data->internal |= BIT(0);
3066 + } else {
3067 + sio_data->internal &= ~BIT(3);
3068 sio_data->skip_in |= BIT(9);
3069 + }
3070
3071 sio_data->beep_pin = superio_inb(sioaddr,
3072 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3073 @@ -2706,6 +3420,124 @@
3074
3075 sio_data->beep_pin = superio_inb(sioaddr,
3076 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3077 + } else if (sio_data->type == it8732 || sio_data->type == it8736 ||
3078 + sio_data->type == it8738) {
3079 + int reg;
3080 +
3081 + superio_select(sioaddr, GPIO);
3082 +
3083 + /* Check for pwm2, fan2 */
3084 + reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3085 + if (reg & BIT(1))
3086 + sio_data->skip_pwm |= BIT(1);
3087 + if (reg & BIT(2))
3088 + sio_data->skip_fan |= BIT(1);
3089 +
3090 + /* Check for pwm3, fan3, fan4 */
3091 + reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3092 + if (reg & BIT(6))
3093 + sio_data->skip_pwm |= BIT(2);
3094 + if (reg & BIT(7))
3095 + sio_data->skip_fan |= BIT(2);
3096 + if (reg & BIT(5))
3097 + sio_data->skip_fan |= BIT(3);
3098 +
3099 + /* Check if AVCC is on VIN3 */
3100 + if (sio_data->type != it8738) {
3101 + reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3102 + if (reg & BIT(0))
3103 + sio_data->internal |= BIT(0);
3104 + }
3105 +
3106 + sio_data->beep_pin = superio_inb(sioaddr,
3107 + IT87_SIO_BEEP_PIN_REG) & 0x3f;
3108 + } else if (sio_data->type == it8655) {
3109 + int reg;
3110 +
3111 + superio_select(sioaddr, GPIO);
3112 +
3113 + /* Check for pwm2 */
3114 + reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3115 + if (reg & BIT(1))
3116 + sio_data->skip_pwm |= BIT(1);
3117 +
3118 + /* Check for fan2 */
3119 + reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3120 + if (reg & BIT(4))
3121 + sio_data->skip_fan |= BIT(1);
3122 +
3123 + /* Check for pwm3, fan3 */
3124 + reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3125 + if (reg & BIT(6))
3126 + sio_data->skip_pwm |= BIT(2);
3127 + if (reg & BIT(7))
3128 + sio_data->skip_fan |= BIT(2);
3129 +
3130 + sio_data->beep_pin = superio_inb(sioaddr,
3131 + IT87_SIO_BEEP_PIN_REG) & 0x3f;
3132 + } else if (sio_data->type == it8665 || sio_data->type == it8625) {
3133 + int reg27, reg29, reg2d, regd3;
3134 +
3135 + superio_select(sioaddr, GPIO);
3136 +
3137 + reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3138 + reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3139 + reg2d = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3140 + regd3 = superio_inb(sioaddr, IT87_SIO_GPIO9_REG);
3141 +
3142 + /* Check for pwm2 */
3143 + if (reg29 & BIT(1))
3144 + sio_data->skip_pwm |= BIT(1);
3145 +
3146 + /* Check for pwm3, fan3 */
3147 + if (reg27 & BIT(6))
3148 + sio_data->skip_pwm |= BIT(2);
3149 + if (reg27 & BIT(7))
3150 + sio_data->skip_fan |= BIT(2);
3151 +
3152 + /* Check for fan2, pwm4, fan4, pwm5, fan5 */
3153 + if (sio_data->type == it8625) {
3154 + int reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3155 +
3156 + if (reg29 & BIT(2))
3157 + sio_data->skip_fan |= BIT(1);
3158 + if (reg25 & BIT(6))
3159 + sio_data->skip_fan |= BIT(3);
3160 + if (reg25 & BIT(5))
3161 + sio_data->skip_pwm |= BIT(3);
3162 + if (reg27 & BIT(3))
3163 + sio_data->skip_pwm |= BIT(4);
3164 + if (!(reg27 & BIT(1)))
3165 + sio_data->skip_fan |= BIT(4);
3166 + } else {
3167 + int reg26 = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3168 +
3169 + if (reg2d & BIT(4))
3170 + sio_data->skip_fan |= BIT(1);
3171 + if (regd3 & BIT(2))
3172 + sio_data->skip_pwm |= BIT(3);
3173 + if (regd3 & BIT(3))
3174 + sio_data->skip_fan |= BIT(3);
3175 + if (reg26 & BIT(5))
3176 + sio_data->skip_pwm |= BIT(4);
3177 + /*
3178 + * Table 6-1 in datasheet claims that FAN_TAC5 would
3179 + * be enabled with 26h[4]=0. This contradicts with the
3180 + * information in section 8.3.9 and with feedback from
3181 + * users.
3182 + */
3183 + if (!(reg26 & BIT(4)))
3184 + sio_data->skip_fan |= BIT(4);
3185 + }
3186 +
3187 + /* Check for pwm6, fan6 */
3188 + if (regd3 & BIT(0))
3189 + sio_data->skip_pwm |= BIT(5);
3190 + if (regd3 & BIT(1))
3191 + sio_data->skip_fan |= BIT(5);
3192 +
3193 + sio_data->beep_pin = superio_inb(sioaddr,
3194 + IT87_SIO_BEEP_PIN_REG) & 0x3f;
3195 } else {
3196 int reg;
3197 bool uart6;
3198 @@ -2767,13 +3599,13 @@
3199 uart6 = sio_data->type == it8782 && (reg & BIT(2));
3200
3201 /*
3202 - * The IT8720F has no VIN7 pin, so VCCH5V should always be
3203 + * The IT8720F has no VIN7 pin, so VCCH should always be
3204 * routed internally to VIN7 with an internal divider.
3205 * Curiously, there still is a configuration bit to control
3206 * this, which means it can be set incorrectly. And even
3207 * more curiously, many boards out there are improperly
3208 * configured, even though the IT8720F datasheet claims
3209 - * that the internal routing of VCCH5V to VIN7 is the default
3210 + * that the internal routing of VCCH to VIN7 is the default
3211 * setting. So we force the internal routing in this case.
3212 *
3213 * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
3214 @@ -2783,8 +3615,7 @@
3215 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
3216 reg |= BIT(1);
3217 superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
3218 - sio_data->need_in7_reroute = true;
3219 - pr_notice("Routing internal VCCH5V to in7\n");
3220 + pr_notice("Routing internal VCCH to in7\n");
3221 }
3222 if (reg & BIT(0))
3223 sio_data->internal |= BIT(0);
3224 @@ -2811,113 +3642,108 @@
3225 if (sio_data->beep_pin)
3226 pr_info("Beeping is supported\n");
3227
3228 - /* Disable specific features based on DMI strings */
3229 - board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
3230 - board_name = dmi_get_system_info(DMI_BOARD_NAME);
3231 - if (board_vendor && board_name) {
3232 - if (strcmp(board_vendor, "nVIDIA") == 0 &&
3233 - strcmp(board_name, "FN68PT") == 0) {
3234 - /*
3235 - * On the Shuttle SN68PT, FAN_CTL2 is apparently not
3236 - * connected to a fan, but to something else. One user
3237 - * has reported instant system power-off when changing
3238 - * the PWM2 duty cycle, so we disable it.
3239 - * I use the board name string as the trigger in case
3240 - * the same board is ever used in other systems.
3241 - */
3242 - pr_info("Disabling pwm2 due to hardware constraints\n");
3243 - sio_data->skip_pwm = BIT(1);
3244 - }
3245 + if (config->smbus_bitmap && !base) {
3246 + u8 reg;
3247 +
3248 + superio_select(sioaddr, PME);
3249 + reg = superio_inb(sioaddr, IT87_SPECIAL_CFG_REG);
3250 + sio_data->ec_special_config = reg;
3251 + sio_data->smbus_bitmap = reg & config->smbus_bitmap;
3252 }
3253
3254 exit:
3255 - superio_exit(sioaddr);
3256 + superio_exit(sioaddr, doexit);
3257 return err;
3258 }
3259
3260 -/*
3261 - * Some chips seem to have default value 0xff for all limit
3262 - * registers. For low voltage limits it makes no sense and triggers
3263 - * alarms, so change to 0 instead. For high temperature limits, it
3264 - * means -1 degree C, which surprisingly doesn't trigger an alarm,
3265 - * but is still confusing, so change to 127 degrees C.
3266 - */
3267 -static void it87_check_limit_regs(struct it87_data *data)
3268 -{
3269 - int i, reg;
3270 -
3271 - for (i = 0; i < NUM_VIN_LIMIT; i++) {
3272 - reg = it87_read_value(data, IT87_REG_VIN_MIN(i));
3273 - if (reg == 0xff)
3274 - it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
3275 - }
3276 - for (i = 0; i < NUM_TEMP_LIMIT; i++) {
3277 - reg = it87_read_value(data, IT87_REG_TEMP_HIGH(i));
3278 - if (reg == 0xff)
3279 - it87_write_value(data, IT87_REG_TEMP_HIGH(i), 127);
3280 - }
3281 -}
3282 -
3283 -/* Check if voltage monitors are reset manually or by some reason */
3284 -static void it87_check_voltage_monitors_reset(struct it87_data *data)
3285 +static void it87_init_regs(struct platform_device *pdev)
3286 {
3287 - int reg;
3288 -
3289 - reg = it87_read_value(data, IT87_REG_VIN_ENABLE);
3290 - if ((reg & 0xff) == 0) {
3291 - /* Enable all voltage monitors */
3292 - it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
3293 - }
3294 -}
3295 -
3296 -/* Check if tachometers are reset manually or by some reason */
3297 -static void it87_check_tachometers_reset(struct platform_device *pdev)
3298 -{
3299 - struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
3300 struct it87_data *data = platform_get_drvdata(pdev);
3301 - u8 mask, fan_main_ctrl;
3302
3303 - mask = 0x70 & ~(sio_data->skip_fan << 4);
3304 - fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
3305 - if ((fan_main_ctrl & mask) == 0) {
3306 - /* Enable all fan tachometers */
3307 - fan_main_ctrl |= mask;
3308 - it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
3309 - fan_main_ctrl);
3310 + /* Initialize chip specific register pointers */
3311 + switch (data->type) {
3312 + case it8628:
3313 + case it8686:
3314 + data->REG_FAN = IT87_REG_FAN;
3315 + data->REG_FANX = IT87_REG_FANX;
3316 + data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3317 + data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3318 + data->REG_PWM = IT87_REG_PWM;
3319 + data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET_8686;
3320 + data->REG_TEMP_LOW = IT87_REG_TEMP_LOW_8686;
3321 + data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH_8686;
3322 + break;
3323 + case it8625:
3324 + case it8655:
3325 + case it8665:
3326 + data->REG_FAN = IT87_REG_FAN_8665;
3327 + data->REG_FANX = IT87_REG_FANX_8665;
3328 + data->REG_FAN_MIN = IT87_REG_FAN_MIN_8665;
3329 + data->REG_FANX_MIN = IT87_REG_FANX_MIN_8665;
3330 + data->REG_PWM = IT87_REG_PWM_8665;
3331 + data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3332 + data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3333 + data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3334 + break;
3335 + case it8622:
3336 + data->REG_FAN = IT87_REG_FAN;
3337 + data->REG_FANX = IT87_REG_FANX;
3338 + data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3339 + data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3340 + data->REG_PWM = IT87_REG_PWM_8665;
3341 + data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3342 + data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3343 + data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3344 + break;
3345 + case it8613:
3346 + data->REG_FAN = IT87_REG_FAN;
3347 + data->REG_FANX = IT87_REG_FANX;
3348 + data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3349 + data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3350 + data->REG_PWM = IT87_REG_PWM_8665;
3351 + data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3352 + data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3353 + data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3354 + break;
3355 + default:
3356 + data->REG_FAN = IT87_REG_FAN;
3357 + data->REG_FANX = IT87_REG_FANX;
3358 + data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3359 + data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3360 + data->REG_PWM = IT87_REG_PWM;
3361 + data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3362 + data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3363 + data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3364 + break;
3365 }
3366 -}
3367 -
3368 -/* Set tachometers to 16-bit mode if needed */
3369 -static void it87_check_tachometers_16bit_mode(struct platform_device *pdev)
3370 -{
3371 - struct it87_data *data = platform_get_drvdata(pdev);
3372 - int reg;
3373 -
3374 - if (!has_fan16_config(data))
3375 - return;
3376
3377 - reg = it87_read_value(data, IT87_REG_FAN_16BIT);
3378 - if (~reg & 0x07 & data->has_fan) {
3379 - dev_dbg(&pdev->dev,
3380 - "Setting fan1-3 to 16-bit mode\n");
3381 - it87_write_value(data, IT87_REG_FAN_16BIT,
3382 - reg | 0x07);
3383 + if (data->mmio) {
3384 + data->read = it87_mmio_read;
3385 + data->write = it87_mmio_write;
3386 + } else if (has_bank_sel(data)) {
3387 + data->read = it87_io_read;
3388 + data->write = it87_io_write;
3389 + } else {
3390 + data->read = _it87_io_read;
3391 + data->write = _it87_io_write;
3392 }
3393 }
3394
3395 -static void it87_start_monitoring(struct it87_data *data)
3396 -{
3397 - it87_write_value(data, IT87_REG_CONFIG,
3398 - (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
3399 - | (update_vbat ? 0x41 : 0x01));
3400 -}
3401 -
3402 /* Called when we have found a new IT87. */
3403 static void it87_init_device(struct platform_device *pdev)
3404 {
3405 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
3406 struct it87_data *data = platform_get_drvdata(pdev);
3407 int tmp, i;
3408 + u8 mask;
3409 +
3410 + if (has_new_tempmap(data)) {
3411 + data->pwm_temp_map_shift = 3;
3412 + data->pwm_temp_map_mask = 0x07;
3413 + } else {
3414 + data->pwm_temp_map_shift = 0;
3415 + data->pwm_temp_map_mask = 0x03;
3416 + }
3417
3418 /*
3419 * For each PWM channel:
3420 @@ -2925,7 +3751,7 @@
3421 * the fan to full speed by default.
3422 * - If it is in manual mode, we need a mapping to temperature
3423 * channels to use when later setting to automatic mode later.
3424 - * Use a 1:1 mapping by default (we are clueless.)
3425 + * Map to the first sensor by default (we are clueless.)
3426 * In both cases, the value can (and should) be changed by the user
3427 * prior to switching to a different mode.
3428 * Note that this is no longer needed for the IT8721F and later, as
3429 @@ -2933,12 +3759,28 @@
3430 * manual duty cycle.
3431 */
3432 for (i = 0; i < NUM_AUTO_PWM; i++) {
3433 - data->pwm_temp_map[i] = i;
3434 + data->pwm_temp_map[i] = 0;
3435 data->pwm_duty[i] = 0x7f; /* Full speed */
3436 data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */
3437 }
3438
3439 - it87_check_limit_regs(data);
3440 + /*
3441 + * Some chips seem to have default value 0xff for all limit
3442 + * registers. For low voltage limits it makes no sense and triggers
3443 + * alarms, so change to 0 instead. For high temperature limits, it
3444 + * means -1 degree C, which surprisingly doesn't trigger an alarm,
3445 + * but is still confusing, so change to 127 degrees C.
3446 + */
3447 + for (i = 0; i < NUM_VIN_LIMIT; i++) {
3448 + tmp = data->read(data, IT87_REG_VIN_MIN(i));
3449 + if (tmp == 0xff)
3450 + data->write(data, IT87_REG_VIN_MIN(i), 0);
3451 + }
3452 + for (i = 0; i < data->num_temp_limit; i++) {
3453 + tmp = data->read(data, data->REG_TEMP_HIGH[i]);
3454 + if (tmp == 0xff)
3455 + data->write(data, data->REG_TEMP_HIGH[i], 127);
3456 + }
3457
3458 /*
3459 * Temperature channels are not forcibly enabled, as they can be
3460 @@ -2947,41 +3789,86 @@
3461 * run-time through the temp{1-3}_type sysfs accessors if needed.
3462 */
3463
3464 - it87_check_voltage_monitors_reset(data);
3465 -
3466 - it87_check_tachometers_reset(pdev);
3467 + /* Check if voltage monitors are reset manually or by some reason */
3468 + tmp = data->read(data, IT87_REG_VIN_ENABLE);
3469 + if ((tmp & 0xff) == 0) {
3470 + /* Enable all voltage monitors */
3471 + data->write(data, IT87_REG_VIN_ENABLE, 0xff);
3472 + }
3473
3474 - data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
3475 + /* Check if tachometers are reset manually or by some reason */
3476 + mask = 0x70 & ~(sio_data->skip_fan << 4);
3477 + data->fan_main_ctrl = data->read(data, IT87_REG_FAN_MAIN_CTRL);
3478 + if ((data->fan_main_ctrl & mask) == 0) {
3479 + /* Enable all fan tachometers */
3480 + data->fan_main_ctrl |= mask;
3481 + data->write(data, IT87_REG_FAN_MAIN_CTRL, data->fan_main_ctrl);
3482 + }
3483 data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
3484
3485 - it87_check_tachometers_16bit_mode(pdev);
3486 + tmp = data->read(data, IT87_REG_FAN_16BIT);
3487
3488 - /* Check for additional fans */
3489 - if (has_five_fans(data)) {
3490 - tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
3491 + /* Set tachometers to 16-bit mode if needed */
3492 + if (has_fan16_config(data)) {
3493 + if (~tmp & 0x07 & data->has_fan) {
3494 + dev_dbg(&pdev->dev,
3495 + "Setting fan1-3 to 16-bit mode\n");
3496 + data->write(data, IT87_REG_FAN_16BIT, tmp | 0x07);
3497 + }
3498 + }
3499
3500 - if (tmp & BIT(4))
3501 - data->has_fan |= BIT(3); /* fan4 enabled */
3502 - if (tmp & BIT(5))
3503 - data->has_fan |= BIT(4); /* fan5 enabled */
3504 - if (has_six_fans(data) && (tmp & BIT(2)))
3505 - data->has_fan |= BIT(5); /* fan6 enabled */
3506 + /* Check for additional fans */
3507 + if (has_four_fans(data) && (tmp & BIT(4)))
3508 + data->has_fan |= BIT(3); /* fan4 enabled */
3509 + if (has_five_fans(data) && (tmp & BIT(5)))
3510 + data->has_fan |= BIT(4); /* fan5 enabled */
3511 + if (has_six_fans(data)) {
3512 + switch (data->type) {
3513 + case it8620:
3514 + case it8628:
3515 + case it8686:
3516 + if (tmp & BIT(2))
3517 + data->has_fan |= BIT(5); /* fan6 enabled */
3518 + break;
3519 + case it8625:
3520 + case it8665:
3521 + tmp = data->read(data, IT87_REG_FAN_DIV);
3522 + if (tmp & BIT(3))
3523 + data->has_fan |= BIT(5); /* fan6 enabled */
3524 + break;
3525 + default:
3526 + break;
3527 + }
3528 }
3529
3530 /* Fan input pins may be used for alternative functions */
3531 data->has_fan &= ~sio_data->skip_fan;
3532
3533 - /* Check if pwm5, pwm6 are enabled */
3534 + /* Check if pwm6 is enabled */
3535 if (has_six_pwm(data)) {
3536 - /* The following code may be IT8620E specific */
3537 - tmp = it87_read_value(data, IT87_REG_FAN_DIV);
3538 - if ((tmp & 0xc0) == 0xc0)
3539 - sio_data->skip_pwm |= BIT(4);
3540 - if (!(tmp & BIT(3)))
3541 - sio_data->skip_pwm |= BIT(5);
3542 + switch (data->type) {
3543 + case it8620:
3544 + case it8686:
3545 + tmp = data->read(data, IT87_REG_FAN_DIV);
3546 + if (!(tmp & BIT(3)))
3547 + sio_data->skip_pwm |= BIT(5);
3548 + break;
3549 + default:
3550 + break;
3551 + }
3552 + }
3553 +
3554 + if (has_bank_sel(data)) {
3555 + for (i = 0; i < 3; i++)
3556 + data->temp_src[i] =
3557 + data->read(data, IT87_REG_TEMP_SRC1[i]);
3558 + data->temp_src[3] = data->read(data, IT87_REG_TEMP_SRC2);
3559 }
3560
3561 - it87_start_monitoring(data);
3562 + /* Start monitoring */
3563 + data->write(data, IT87_REG_CONFIG,
3564 + (data->read(data, IT87_REG_CONFIG) & 0x3e) |
3565 + (update_vbat ? 0x41 : 0x01));
3566 }
3567
3568 /* Return 1 if and only if the PWM interface is safe to use */
3569 @@ -2993,7 +3880,7 @@
3570 * and polarity set to active low is sign that this is the case so we
3571 * disable pwm control to protect the user.
3572 */
3573 - int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
3574 + int tmp = data->read(data, IT87_REG_FAN_CTL);
3575
3576 if ((tmp & 0x87) == 0) {
3577 if (fix_pwm_polarity) {
3578 @@ -3006,8 +3893,8 @@
3579 u8 pwm[3];
3580
3581 for (i = 0; i < ARRAY_SIZE(pwm); i++)
3582 - pwm[i] = it87_read_value(data,
3583 - IT87_REG_PWM[i]);
3584 + pwm[i] = data->read(data,
3585 + data->REG_PWM[i]);
3586
3587 /*
3588 * If any fan is in automatic pwm mode, the polarity
3589 @@ -3018,12 +3905,10 @@
3590 if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
3591 dev_info(dev,
3592 "Reconfiguring PWM to active high polarity\n");
3593 - it87_write_value(data, IT87_REG_FAN_CTL,
3594 - tmp | 0x87);
3595 + data->write(data, IT87_REG_FAN_CTL, tmp | 0x87);
3596 for (i = 0; i < 3; i++)
3597 - it87_write_value(data,
3598 - IT87_REG_PWM[i],
3599 - 0x7f & ~pwm[i]);
3600 + data->write(data, data->REG_PWM[i],
3601 + 0x7f & ~pwm[i]);
3602 return 1;
3603 }
3604
3605 @@ -3031,6 +3916,8 @@
3606 "PWM configuration is too broken to be fixed\n");
3607 }
3608
3609 + dev_info(dev,
3610 + "Detected broken BIOS defaults, disabling PWM interface\n");
3611 return 0;
3612 } else if (fix_pwm_polarity) {
3613 dev_info(dev,
3614 @@ -3048,26 +3935,39 @@
3615 struct it87_sio_data *sio_data = dev_get_platdata(dev);
3616 int enable_pwm_interface;
3617 struct device *hwmon_dev;
3618 + int err;
3619
3620 - res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3621 - if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
3622 - DRVNAME)) {
3623 - dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
3624 - (unsigned long)res->start,
3625 - (unsigned long)(res->start + IT87_EC_EXTENT - 1));
3626 - return -EBUSY;
3627 - }
3628 -
3629 - data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
3630 + data = devm_kzalloc(dev, sizeof(struct it87_data), GFP_KERNEL);
3631 if (!data)
3632 return -ENOMEM;
3633
3634 + res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3635 + if (res) {
3636 + if (!devm_request_region(dev, res->start, IT87_EC_EXTENT,
3637 + DRVNAME)) {
3638 + dev_err(dev, "Failed to request region %pR\n", res);
3639 + return -EBUSY;
3640 + }
3641 + } else {
3642 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3643 + data->mmio = devm_ioremap_resource(dev, res);
3644 + if (IS_ERR(data->mmio))
3645 + return PTR_ERR(data->mmio);
3646 + }
3647 +
3648 data->addr = res->start;
3649 - data->sioaddr = sio_data->sioaddr;
3650 data->type = sio_data->type;
3651 + data->sioaddr = sio_data->sioaddr;
3652 + data->smbus_bitmap = sio_data->smbus_bitmap;
3653 + data->ec_special_config = sio_data->ec_special_config;
3654 + data->doexit = sio_data->doexit;
3655 data->features = it87_devices[sio_data->type].features;
3656 + data->num_temp_limit = it87_devices[sio_data->type].num_temp_limit;
3657 + data->num_temp_offset = it87_devices[sio_data->type].num_temp_offset;
3658 + data->pwm_num_temp_map = it87_devices[sio_data->type].num_temp_map;
3659 data->peci_mask = it87_devices[sio_data->type].peci_mask;
3660 data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
3661 +
3662 /*
3663 * IT8705F Datasheet 0.4.1, 3h == Version G.
3664 * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
3665 @@ -3091,23 +3991,40 @@
3666 break;
3667 }
3668
3669 - /* Now, we do the remaining detection. */
3670 - if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) ||
3671 - it87_read_value(data, IT87_REG_CHIPID) != 0x90)
3672 - return -ENODEV;
3673 -
3674 platform_set_drvdata(pdev, data);
3675
3676 mutex_init(&data->update_lock);
3677
3678 + /* Initialize register pointers */
3679 + it87_init_regs(pdev);
3680 +
3681 + /*
3682 + * We need to disable SMBus before we can read any registers in
3683 + * the envmon address space, even if it is for chip identification
3684 + * purposes. If the chip has SMBus client support, it likely also has
3685 + * multi-page envmon registers, so we have to set the page anyway
3686 + * before accessing those registers. Kind of a chicken-and-egg
3687 + * problem.
3688 + * Fortunately, the chip was already identified through the SIO
3689 + * address space, only recent chips are affected, and this is just
3690 + * an additional safeguard.
3691 + */
3692 + err = smbus_disable(data);
3693 + if (err)
3694 + return err;
3695 +
3696 + /* Now, we do the remaining detection. */
3697 + if ((data->read(data, IT87_REG_CONFIG) & 0x80) ||
3698 + data->read(data, IT87_REG_CHIPID) != 0x90) {
3699 + smbus_enable(data);
3700 + return -ENODEV;
3701 + }
3702 +
3703 /* Check PWM configuration */
3704 enable_pwm_interface = it87_check_pwm(dev);
3705 - if (!enable_pwm_interface)
3706 - dev_info(dev,
3707 - "Detected broken BIOS defaults, disabling PWM interface\n");
3708
3709 /* Starting with IT8721F, we handle scaling of internal voltages */
3710 - if (has_12mv_adc(data)) {
3711 + if (has_scaling(data)) {
3712 if (sio_data->internal & BIT(0))
3713 data->in_scaled |= BIT(3); /* in3 is AVCC */
3714 if (sio_data->internal & BIT(1))
3715 @@ -3127,32 +4044,37 @@
3716 data->has_temp = 0x07;
3717 if (sio_data->skip_temp & BIT(2)) {
3718 if (sio_data->type == it8782 &&
3719 - !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
3720 + !(data->read(data, IT87_REG_TEMP_EXTRA) & 0x80))
3721 data->has_temp &= ~BIT(2);
3722 }
3723
3724 data->in_internal = sio_data->internal;
3725 - data->need_in7_reroute = sio_data->need_in7_reroute;
3726 data->has_in = 0x3ff & ~sio_data->skip_in;
3727
3728 - if (has_six_temp(data)) {
3729 - u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE);
3730 + if (has_four_temp(data)) {
3731 + data->has_temp |= BIT(3);
3732 + } else if (has_six_temp(data)) {
3733 + if (sio_data->type == it8655 || sio_data->type == it8665) {
3734 + data->has_temp |= BIT(3) | BIT(4) | BIT(5);
3735 + } else {
3736 + u8 reg = data->read(data, IT87_REG_TEMP456_ENABLE);
3737
3738 - /* Check for additional temperature sensors */
3739 - if ((reg & 0x03) >= 0x02)
3740 - data->has_temp |= BIT(3);
3741 - if (((reg >> 2) & 0x03) >= 0x02)
3742 - data->has_temp |= BIT(4);
3743 - if (((reg >> 4) & 0x03) >= 0x02)
3744 - data->has_temp |= BIT(5);
3745 -
3746 - /* Check for additional voltage sensors */
3747 - if ((reg & 0x03) == 0x01)
3748 - data->has_in |= BIT(10);
3749 - if (((reg >> 2) & 0x03) == 0x01)
3750 - data->has_in |= BIT(11);
3751 - if (((reg >> 4) & 0x03) == 0x01)
3752 - data->has_in |= BIT(12);
3753 + /* Check for additional temperature sensors */
3754 + if ((reg & 0x03) >= 0x02)
3755 + data->has_temp |= BIT(3);
3756 + if (((reg >> 2) & 0x03) >= 0x02)
3757 + data->has_temp |= BIT(4);
3758 + if (((reg >> 4) & 0x03) >= 0x02)
3759 + data->has_temp |= BIT(5);
3760 +
3761 + /* Check for additional voltage sensors */
3762 + if ((reg & 0x03) == 0x01)
3763 + data->has_in |= BIT(10);
3764 + if (((reg >> 2) & 0x03) == 0x01)
3765 + data->has_in |= BIT(11);
3766 + if (((reg >> 4) & 0x03) == 0x01)
3767 + data->has_in |= BIT(12);
3768 + }
3769 }
3770
3771 data->has_beep = !!sio_data->beep_pin;
3772 @@ -3160,6 +4082,8 @@
3773 /* Initialize the IT87 chip */
3774 it87_init_device(pdev);
3775
3776 + smbus_enable(data);
3777 +
3778 if (!sio_data->skip_vid) {
3779 data->has_vid = true;
3780 data->vrm = vid_which_vrm();
3781 @@ -3188,92 +4112,40 @@
3782 return PTR_ERR_OR_ZERO(hwmon_dev);
3783 }
3784
3785 -static void __maybe_unused it87_resume_sio(struct platform_device *pdev)
3786 -{
3787 - struct it87_data *data = dev_get_drvdata(&pdev->dev);
3788 - int err;
3789 - int reg2c;
3790 -
3791 - if (!data->need_in7_reroute)
3792 - return;
3793 -
3794 - err = superio_enter(data->sioaddr);
3795 - if (err) {
3796 - dev_warn(&pdev->dev,
3797 - "Unable to enter Super I/O to reroute in7 (%d)",
3798 - err);
3799 - return;
3800 - }
3801 -
3802 - superio_select(data->sioaddr, GPIO);
3803 -
3804 - reg2c = superio_inb(data->sioaddr, IT87_SIO_PINX2_REG);
3805 - if (!(reg2c & BIT(1))) {
3806 - dev_dbg(&pdev->dev,
3807 - "Routing internal VCCH5V to in7 again");
3808 -
3809 - reg2c |= BIT(1);
3810 - superio_outb(data->sioaddr, IT87_SIO_PINX2_REG,
3811 - reg2c);
3812 - }
3813 -
3814 - superio_exit(data->sioaddr);
3815 -}
3816 -
3817 -static int __maybe_unused it87_resume(struct device *dev)
3818 -{
3819 - struct platform_device *pdev = to_platform_device(dev);
3820 - struct it87_data *data = dev_get_drvdata(dev);
3821 -
3822 - it87_resume_sio(pdev);
3823 -
3824 - mutex_lock(&data->update_lock);
3825 -
3826 - it87_check_pwm(dev);
3827 - it87_check_limit_regs(data);
3828 - it87_check_voltage_monitors_reset(data);
3829 - it87_check_tachometers_reset(pdev);
3830 - it87_check_tachometers_16bit_mode(pdev);
3831 -
3832 - it87_start_monitoring(data);
3833 -
3834 - /* force update */
3835 - data->valid = false;
3836 -
3837 - mutex_unlock(&data->update_lock);
3838 -
3839 - it87_update_device(dev);
3840 -
3841 - return 0;
3842 -}
3843 -
3844 -static SIMPLE_DEV_PM_OPS(it87_dev_pm_ops, NULL, it87_resume);
3845 -
3846 static struct platform_driver it87_driver = {
3847 .driver = {
3848 .name = DRVNAME,
3849 - .pm = &it87_dev_pm_ops,
3850 },
3851 .probe = it87_probe,
3852 };
3853
3854 -static int __init it87_device_add(int index, unsigned short address,
3855 +static int __init it87_device_add(int index, unsigned short sio_address,
3856 + phys_addr_t mmio_address,
3857 const struct it87_sio_data *sio_data)
3858 {
3859 struct platform_device *pdev;
3860 struct resource res = {
3861 - .start = address + IT87_EC_OFFSET,
3862 - .end = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
3863 .name = DRVNAME,
3864 - .flags = IORESOURCE_IO,
3865 };
3866 int err;
3867
3868 + if (mmio_address) {
3869 + res.start = mmio_address;
3870 + res.end = mmio_address + 0x400 - 1;
3871 + res.flags = IORESOURCE_MEM;
3872 + } else {
3873 + res.start = sio_address + IT87_EC_OFFSET;
3874 + res.end = sio_address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1;
3875 + res.flags = IORESOURCE_IO;
3876 + }
3877 +
3878 err = acpi_check_resource_conflict(&res);
3879 - if (err)
3880 - return err;
3881 + if (err) {
3882 + if (!ignore_resource_conflict)
3883 + return err;
3884 + }
3885
3886 - pdev = platform_device_alloc(DRVNAME, address);
3887 + pdev = platform_device_alloc(DRVNAME, sio_address);
3888 if (!pdev)
3889 return -ENOMEM;
3890
3891 @@ -3304,43 +4176,114 @@
3892 return err;
3893 }
3894
3895 +struct it87_dmi_data {
3896 + bool sio2_force_config; /* force sio2 into configuration mode */
3897 + u8 skip_pwm; /* pwm channels to skip for this board */
3898 +};
3899 +
3900 +/*
3901 + * On various Gigabyte AM4 boards (AB350, AX370), the second Super-IO chip
3902 + * (IT8792E) needs to be in configuration mode before accessing the first
3903 + * due to a bug in IT8792E which otherwise results in LPC bus access errors.
3904 + * This needs to be done before accessing the first Super-IO chip since
3905 + * the second chip may have been accessed prior to loading this driver.
3906 + *
3907 + * The problem is also reported to affect IT8795E, which is used on X299 boards
3908 + * and has the same chip ID as IT8792E (0x8733). It also appears to affect
3909 + * systems with IT8790E, which is used on some Z97X-Gaming boards as well as
3910 + * Z87X-OC.
3911 + * DMI entries for those systems will be added as they become available and
3912 + * as the problem is confirmed to affect those boards.
3913 + */
3914 +static struct it87_dmi_data gigabyte_sio2_force = {
3915 + .sio2_force_config = true,
3916 +};
3917 +
3918 +/*
3919 + * On the Shuttle SN68PT, FAN_CTL2 is apparently not
3920 + * connected to a fan, but to something else. One user
3921 + * has reported instant system power-off when changing
3922 + * the PWM2 duty cycle, so we disable it.
3923 + * I use the board name string as the trigger in case
3924 + * the same board is ever used in other systems.
3925 + */
3926 +static struct it87_dmi_data nvidia_fn68pt = {
3927 + .skip_pwm = BIT(1),
3928 +};
3929 +
3930 +static const struct dmi_system_id it87_dmi_table[] __initconst = {
3931 + {
3932 + .matches = {
3933 + DMI_MATCH(DMI_SYS_VENDOR,
3934 + "Gigabyte Technology Co., Ltd."),
3935 + DMI_MATCH(DMI_BOARD_NAME, "AB350"),
3936 + },
3937 + .driver_data = &gigabyte_sio2_force,
3938 + },
3939 + {
3940 + .matches = {
3941 + DMI_MATCH(DMI_SYS_VENDOR,
3942 + "Gigabyte Technology Co., Ltd."),
3943 + DMI_MATCH(DMI_BOARD_NAME, "AX370"),
3944 + },
3945 + .driver_data = &gigabyte_sio2_force,
3946 + },
3947 + {
3948 + .matches = {
3949 + DMI_MATCH(DMI_SYS_VENDOR,
3950 + "Gigabyte Technology Co., Ltd."),
3951 + DMI_MATCH(DMI_BOARD_NAME, "Z97X-Gaming G1"),
3952 + },
3953 + .driver_data = &gigabyte_sio2_force,
3954 + },
3955 + {
3956 + .matches = {
3957 + DMI_MATCH(DMI_BOARD_VENDOR, "nVIDIA"),
3958 + DMI_MATCH(DMI_BOARD_NAME, "FN68PT"),
3959 + },
3960 + .driver_data = &nvidia_fn68pt,
3961 + },
3962 + { }
3963 +};
3964 +
3965 static int __init sm_it87_init(void)
3966 {
3967 + const struct dmi_system_id *dmi = dmi_first_match(it87_dmi_table);
3968 + struct it87_dmi_data *dmi_data = NULL;
3969 int sioaddr[2] = { REG_2E, REG_4E };
3970 struct it87_sio_data sio_data;
3971 - unsigned short isa_address[2];
3972 + unsigned short isa_address;
3973 + phys_addr_t mmio_address;
3974 bool found = false;
3975 int i, err;
3976
3977 + pr_info("it87 driver version %s\n", IT87_DRIVER_VERSION);
3978 +
3979 + if (dmi)
3980 + dmi_data = dmi->driver_data;
3981 +
3982 err = platform_driver_register(&it87_driver);
3983 if (err)
3984 return err;
3985
3986 + if (dmi_data && dmi_data->sio2_force_config)
3987 + __superio_enter(REG_4E);
3988 +
3989 for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
3990 memset(&sio_data, 0, sizeof(struct it87_sio_data));
3991 - isa_address[i] = 0;
3992 - err = it87_find(sioaddr[i], &isa_address[i], &sio_data);
3993 - if (err || isa_address[i] == 0)
3994 + isa_address = 0;
3995 + mmio_address = 0;
3996 + err = it87_find(sioaddr[i], &isa_address, &mmio_address,
3997 + &sio_data);
3998 + if (err || isa_address == 0)
3999 continue;
4000 - /*
4001 - * Don't register second chip if its ISA address matches
4002 - * the first chip's ISA address.
4003 - */
4004 - if (i && isa_address[i] == isa_address[0])
4005 - break;
4006
4007 - err = it87_device_add(i, isa_address[i], &sio_data);
4008 + if (dmi_data)
4009 + sio_data.skip_pwm |= dmi_data->skip_pwm;
4010 + err = it87_device_add(i, isa_address, mmio_address, &sio_data);
4011 if (err)
4012 goto exit_dev_unregister;
4013 -
4014 found = true;
4015 -
4016 - /*
4017 - * IT8705F may respond on both SIO addresses.
4018 - * Stop probing after finding one.
4019 - */
4020 - if (sio_data.type == it87)
4021 - break;
4022 }
4023
4024 if (!found) {
4025 @@ -3367,12 +4310,13 @@
4026
4027 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
4028 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
4029 -module_param(update_vbat, bool, 0);
4030 +module_param(update_vbat, bool, 0000);
4031 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
4032 -module_param(fix_pwm_polarity, bool, 0);
4033 +module_param(fix_pwm_polarity, bool, 0000);
4034 MODULE_PARM_DESC(fix_pwm_polarity,
4035 "Force PWM polarity to active high (DANGEROUS)");
4036 MODULE_LICENSE("GPL");
4037 +MODULE_VERSION(IT87_DRIVER_VERSION);
4038
4039 module_init(sm_it87_init);
4040 module_exit(sm_it87_exit);
t2sde - trunk