| blob | 6e59650cf8e4b01c20a0bcc5be1d2a15f1f7c92d |
1 diff --git a/arch/mips/include/asm/pci/bridge.h b/arch/mips/include/asm/pci/bridge.h
2 index 3206245d1ed6..248a390e89b3 100644
3 --- a/arch/mips/include/asm/pci/bridge.h
4 +++ b/arch/mips/include/asm/pci/bridge.h
5 @@ -388,79 +388,80 @@ typedef struct bridge_err_cmdword_s {
6 * Bridge register bit field definitions
7 */
9 -/* Widget part number of bridge */
10 +/* Widget part numbers. */
11 #define BRIDGE_WIDGET_PART_NUM 0xc002
12 #define XBRIDGE_WIDGET_PART_NUM 0xd002
14 -/* Manufacturer of bridge */
15 +/* Widget manufacturer numbers. */
16 #define BRIDGE_WIDGET_MFGR_NUM 0x036
17 #define XBRIDGE_WIDGET_MFGR_NUM 0x024
19 -/* Revision numbers for known Bridge revisions */
20 +/* Widget revision numbers. */
21 #define BRIDGE_REV_A 0x1
22 #define BRIDGE_REV_B 0x2
23 #define BRIDGE_REV_C 0x3
24 #define BRIDGE_REV_D 0x4
26 /* Bridge widget status register bits definition */
27 -
28 -#define BRIDGE_STAT_LLP_REC_CNT (0xFFu << 24)
29 -#define BRIDGE_STAT_LLP_TX_CNT (0xFF << 16)
30 -#define BRIDGE_STAT_FLASH_SELECT (0x1 << 6)
31 -#define BRIDGE_STAT_PCI_GIO_N (0x1 << 5)
32 -#define BRIDGE_STAT_PENDING (0x1F << 0)
33 +#define BRIDGE_STAT_LLP_REC_CNT GENMASK(31, 24)
34 +#define BRIDGE_STAT_LLP_TX_CNT GENMASK(23, 16)
35 +#define BRIDGE_STAT_FLASH_SELECT BIT(6)
36 +#define BRIDGE_STAT_PCI_GIO_N BIT(5)
37 +#define BRIDGE_STAT_PENDING GENMASK(4, 0)
39 /* Bridge widget control register bits definition */
40 -#define BRIDGE_CTRL_FLASH_WR_EN (0x1ul << 31)
41 -#define BRIDGE_CTRL_EN_CLK50 (0x1 << 30)
42 -#define BRIDGE_CTRL_EN_CLK40 (0x1 << 29)
43 -#define BRIDGE_CTRL_EN_CLK33 (0x1 << 28)
44 +#define BRIDGE_CTRL_FLASH_WR_EN BIT(31)
45 +#define BRIDGE_CTRL_EN_CLK50 BIT(30)
46 +#define BRIDGE_CTRL_EN_CLK40 BIT(29)
47 +#define BRIDGE_CTRL_EN_CLK33 BIT(28)
48 #define BRIDGE_CTRL_RST(n) ((n) << 24)
49 -#define BRIDGE_CTRL_RST_MASK (BRIDGE_CTRL_RST(0xF))
50 -#define BRIDGE_CTRL_RST_PIN(x) (BRIDGE_CTRL_RST(0x1 << (x)))
51 -#define BRIDGE_CTRL_IO_SWAP (0x1 << 23)
52 -#define BRIDGE_CTRL_MEM_SWAP (0x1 << 22)
53 -#define BRIDGE_CTRL_PAGE_SIZE (0x1 << 21)
54 -#define BRIDGE_CTRL_SS_PAR_BAD (0x1 << 20)
55 -#define BRIDGE_CTRL_SS_PAR_EN (0x1 << 19)
56 +#define BRIDGE_CTRL_RST_MASK GENMASK(27, 24)
57 +#define BRIDGE_CTRL_RST_PIN(x) (BRIDGE_CTRL_RST(1UL << (x)))
58 +#define BRIDGE_CTRL_IO_SWAP BIT(23)
59 +#define BRIDGE_CTRL_MEM_SWAP BIT(22)
60 +#define BRIDGE_CTRL_PAGE_SIZE BIT(21)
61 +#define BRIDGE_CTRL_SS_PAR_BAD BIT(20)
62 +#define BRIDGE_CTRL_SS_PAR_EN BIT(19)
63 #define BRIDGE_CTRL_SSRAM_SIZE(n) ((n) << 17)
64 #define BRIDGE_CTRL_SSRAM_SIZE_MASK (BRIDGE_CTRL_SSRAM_SIZE(0x3))
65 #define BRIDGE_CTRL_SSRAM_512K (BRIDGE_CTRL_SSRAM_SIZE(0x3))
66 #define BRIDGE_CTRL_SSRAM_128K (BRIDGE_CTRL_SSRAM_SIZE(0x2))
67 #define BRIDGE_CTRL_SSRAM_64K (BRIDGE_CTRL_SSRAM_SIZE(0x1))
68 #define BRIDGE_CTRL_SSRAM_1K (BRIDGE_CTRL_SSRAM_SIZE(0x0))
69 -#define BRIDGE_CTRL_F_BAD_PKT (0x1 << 16)
70 +#define BRIDGE_CTRL_F_BAD_PKT BIT(16)
71 #define BRIDGE_CTRL_LLP_XBAR_CRD(n) ((n) << 12)
72 #define BRIDGE_CTRL_LLP_XBAR_CRD_MASK (BRIDGE_CTRL_LLP_XBAR_CRD(0xf))
73 -#define BRIDGE_CTRL_CLR_RLLP_CNT (0x1 << 11)
74 -#define BRIDGE_CTRL_CLR_TLLP_CNT (0x1 << 10)
75 -#define BRIDGE_CTRL_SYS_END (0x1 << 9)
76 +#define BRIDGE_CTRL_CLR_RLLP_CNT BIT(11)
77 +#define BRIDGE_CTRL_CLR_TLLP_CNT BIT(10)
78 +#define BRIDGE_CTRL_SYS_END BIT(9)
79 #define BRIDGE_CTRL_MAX_TRANS(n) ((n) << 4)
80 #define BRIDGE_CTRL_MAX_TRANS_MASK (BRIDGE_CTRL_MAX_TRANS(0x1f))
81 #define BRIDGE_CTRL_WIDGET_ID(n) ((n) << 0)
82 #define BRIDGE_CTRL_WIDGET_ID_MASK (BRIDGE_CTRL_WIDGET_ID(0xf))
84 /* Bridge Response buffer Error Upper Register bit fields definition */
85 -#define BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT (20)
86 -#define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
87 -#define BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT (16)
88 -#define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK (0xF << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
89 -#define BRIDGE_RESP_ERRRUPPR_BUFMASK (0xFFFF)
90 -
91 -#define BRIDGE_RESP_ERRUPPR_BUFNUM(x) \
92 - (((x) & BRIDGE_RESP_ERRUPPR_BUFNUM_MASK) >> \
93 - BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
94 -
95 -#define BRIDGE_RESP_ERRUPPR_DEVICE(x) \
96 - (((x) & BRIDGE_RESP_ERRUPPR_DEVNUM_MASK) >> \
97 - BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
98 +#define BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT (20)
99 +#define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK \
100 + (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
101 +#define BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT (16)
102 +#define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK \
103 + (0xf << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
104 +#define BRIDGE_RESP_ERRRUPPR_BUFMASK (0xffff)
105 +
106 +#define BRIDGE_RESP_ERRUPPR_BUFNUM(x) \
107 + (((x) & BRIDGE_RESP_ERRUPPR_BUFNUM_MASK) >> \
108 + BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
109 +
110 +#define BRIDGE_RESP_ERRUPPR_DEVICE(x) \
111 + (((x) & BRIDGE_RESP_ERRUPPR_DEVNUM_MASK) >> \
112 + BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
114 /* Bridge direct mapping register bits definition */
115 #define BRIDGE_DIRMAP_W_ID_SHFT 20
116 -#define BRIDGE_DIRMAP_W_ID (0xf << BRIDGE_DIRMAP_W_ID_SHFT)
117 -#define BRIDGE_DIRMAP_RMF_64 (0x1 << 18)
118 -#define BRIDGE_DIRMAP_ADD512 (0x1 << 17)
119 -#define BRIDGE_DIRMAP_OFF (0x1ffff << 0)
120 +#define BRIDGE_DIRMAP_W_ID GENMASK(23, BRIDGE_DIRMAP_W_ID_SHFT)
121 +#define BRIDGE_DIRMAP_RMF_64 BIT(18)
122 +#define BRIDGE_DIRMAP_ADD512 BIT(17)
123 +#define BRIDGE_DIRMAP_OFF GENMASK(16, 0)
124 #define BRIDGE_DIRMAP_OFF_ADDRSHFT (31) /* lsbit of DIRMAP_OFF is xtalk address bit 31 */
126 /* Bridge Arbitration register bits definition */
127 @@ -468,85 +469,98 @@ typedef struct bridge_err_cmdword_s {
128 #define BRIDGE_ARB_REQ_WAIT_TICK_MASK BRIDGE_ARB_REQ_WAIT_TICK(0x3)
129 #define BRIDGE_ARB_REQ_WAIT_EN(x) ((x) << 8)
130 #define BRIDGE_ARB_REQ_WAIT_EN_MASK BRIDGE_ARB_REQ_WAIT_EN(0xff)
131 -#define BRIDGE_ARB_FREEZE_GNT (1 << 6)
132 -#define BRIDGE_ARB_HPRI_RING_B2 (1 << 5)
133 -#define BRIDGE_ARB_HPRI_RING_B1 (1 << 4)
134 -#define BRIDGE_ARB_HPRI_RING_B0 (1 << 3)
135 -#define BRIDGE_ARB_LPRI_RING_B2 (1 << 2)
136 -#define BRIDGE_ARB_LPRI_RING_B1 (1 << 1)
137 -#define BRIDGE_ARB_LPRI_RING_B0 (1 << 0)
138 +#define BRIDGE_ARB_FREEZE_GNT BIT(6)
139 +#define BRIDGE_ARB_HPRI_RING_B2 BIT(5)
140 +#define BRIDGE_ARB_HPRI_RING_B1 BIT(4)
141 +#define BRIDGE_ARB_HPRI_RING_B0 BIT(3)
142 +#define BRIDGE_ARB_LPRI_RING_B2 BIT(2)
143 +#define BRIDGE_ARB_LPRI_RING_B1 BIT(1)
144 +#define BRIDGE_ARB_LPRI_RING_B0 BIT(0)
146 /* Bridge Bus time-out register bits definition */
147 #define BRIDGE_BUS_PCI_RETRY_HLD(x) ((x) << 16)
148 #define BRIDGE_BUS_PCI_RETRY_HLD_MASK BRIDGE_BUS_PCI_RETRY_HLD(0x1f)
149 -#define BRIDGE_BUS_GIO_TIMEOUT (1 << 12)
150 +#define BRIDGE_BUS_GIO_TIMEOUT BIT(12)
151 #define BRIDGE_BUS_PCI_RETRY_CNT(x) ((x) << 0)
152 #define BRIDGE_BUS_PCI_RETRY_MASK BRIDGE_BUS_PCI_RETRY_CNT(0x3ff)
154 /* Bridge interrupt status register bits definition */
155 -#define BRIDGE_ISR_MULTI_ERR (0x1u << 31)
156 -#define BRIDGE_ISR_PMU_ESIZE_FAULT (0x1 << 30)
157 -#define BRIDGE_ISR_UNEXP_RESP (0x1 << 29)
158 -#define BRIDGE_ISR_BAD_XRESP_PKT (0x1 << 28)
159 -#define BRIDGE_ISR_BAD_XREQ_PKT (0x1 << 27)
160 -#define BRIDGE_ISR_RESP_XTLK_ERR (0x1 << 26)
161 -#define BRIDGE_ISR_REQ_XTLK_ERR (0x1 << 25)
162 -#define BRIDGE_ISR_INVLD_ADDR (0x1 << 24)
163 -#define BRIDGE_ISR_UNSUPPORTED_XOP (0x1 << 23)
164 -#define BRIDGE_ISR_XREQ_FIFO_OFLOW (0x1 << 22)
165 -#define BRIDGE_ISR_LLP_REC_SNERR (0x1 << 21)
166 -#define BRIDGE_ISR_LLP_REC_CBERR (0x1 << 20)
167 -#define BRIDGE_ISR_LLP_RCTY (0x1 << 19)
168 -#define BRIDGE_ISR_LLP_TX_RETRY (0x1 << 18)
169 -#define BRIDGE_ISR_LLP_TCTY (0x1 << 17)
170 -#define BRIDGE_ISR_SSRAM_PERR (0x1 << 16)
171 -#define BRIDGE_ISR_PCI_ABORT (0x1 << 15)
172 -#define BRIDGE_ISR_PCI_PARITY (0x1 << 14)
173 -#define BRIDGE_ISR_PCI_SERR (0x1 << 13)
174 -#define BRIDGE_ISR_PCI_PERR (0x1 << 12)
175 -#define BRIDGE_ISR_PCI_MST_TIMEOUT (0x1 << 11)
176 +#define BRIDGE_ISR_MULTI_ERR BIT(31)
177 +#define BRIDGE_ISR_PMU_ESIZE_FAULT BIT(30)
178 +#define BRIDGE_ISR_UNEXP_RESP BIT(29)
179 +#define BRIDGE_ISR_BAD_XRESP_PKT BIT(28)
180 +#define BRIDGE_ISR_BAD_XREQ_PKT BIT(27)
181 +#define BRIDGE_ISR_RESP_XTLK_ERR BIT(26)
182 +#define BRIDGE_ISR_REQ_XTLK_ERR BIT(25)
183 +#define BRIDGE_ISR_INVLD_ADDR BIT(24)
184 +#define BRIDGE_ISR_UNSUPPORTED_XOP BIT(23)
185 +#define BRIDGE_ISR_XREQ_FIFO_OFLOW BIT(22)
186 +#define BRIDGE_ISR_LLP_REC_SNERR BIT(21)
187 +#define BRIDGE_ISR_LLP_REC_CBERR BIT(20)
188 +#define BRIDGE_ISR_LLP_RCTY BIT(19)
189 +#define BRIDGE_ISR_LLP_TX_RETRY BIT(18)
190 +#define BRIDGE_ISR_LLP_TCTY BIT(17)
191 +#define BRIDGE_ISR_SSRAM_PERR BIT(16)
192 +#define BRIDGE_ISR_PCI_ABORT BIT(15)
193 +#define BRIDGE_ISR_PCI_PARITY BIT(14)
194 +#define BRIDGE_ISR_PCI_SERR BIT(13)
195 +#define BRIDGE_ISR_PCI_PERR BIT(12)
196 +#define BRIDGE_ISR_PCI_MST_TIMEOUT BIT(11)
197 #define BRIDGE_ISR_GIO_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT
198 -#define BRIDGE_ISR_PCI_RETRY_CNT (0x1 << 10)
199 -#define BRIDGE_ISR_XREAD_REQ_TIMEOUT (0x1 << 9)
200 -#define BRIDGE_ISR_GIO_B_ENBL_ERR (0x1 << 8)
201 -#define BRIDGE_ISR_INT_MSK (0xff << 0)
202 -#define BRIDGE_ISR_INT(x) (0x1 << (x))
203 -
204 -#define BRIDGE_ISR_LINK_ERROR \
205 - (BRIDGE_ISR_LLP_REC_SNERR|BRIDGE_ISR_LLP_REC_CBERR| \
206 - BRIDGE_ISR_LLP_RCTY|BRIDGE_ISR_LLP_TX_RETRY| \
207 +#define BRIDGE_ISR_PCI_RETRY_CNT BIT(10)
208 +#define BRIDGE_ISR_XREAD_REQ_TIMEOUT BIT(9)
209 +#define BRIDGE_ISR_GIO_B_ENBL_ERR BIT(8)
210 +#define BRIDGE_ISR_INT_MSK GENMASK(7, 0)
211 +#define BRIDGE_ISR_INT(x) BIT((x))
212 +
213 +#define BRIDGE_ISR_LINK_ERROR \
214 + (BRIDGE_ISR_LLP_REC_SNERR | \
215 + BRIDGE_ISR_LLP_REC_CBERR | \
216 + BRIDGE_ISR_LLP_RCTY | \
217 + BRIDGE_ISR_LLP_TX_RETRY | \
218 BRIDGE_ISR_LLP_TCTY)
220 -#define BRIDGE_ISR_PCIBUS_PIOERR \
221 - (BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT)
222 +#define BRIDGE_ISR_PCIBUS_PIOERR \
223 + (BRIDGE_ISR_PCI_MST_TIMEOUT | \
224 + BRIDGE_ISR_PCI_ABORT)
226 -#define BRIDGE_ISR_PCIBUS_ERROR \
227 - (BRIDGE_ISR_PCIBUS_PIOERR|BRIDGE_ISR_PCI_PERR| \
228 - BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_RETRY_CNT| \
229 +#define BRIDGE_ISR_PCIBUS_ERROR \
230 + (BRIDGE_ISR_PCIBUS_PIOERR | \
231 + BRIDGE_ISR_PCI_PERR | \
232 + BRIDGE_ISR_PCI_SERR | \
233 + BRIDGE_ISR_PCI_RETRY_CNT | \
234 BRIDGE_ISR_PCI_PARITY)
236 -#define BRIDGE_ISR_XTALK_ERROR \
237 - (BRIDGE_ISR_XREAD_REQ_TIMEOUT|BRIDGE_ISR_XREQ_FIFO_OFLOW|\
238 - BRIDGE_ISR_UNSUPPORTED_XOP|BRIDGE_ISR_INVLD_ADDR| \
239 - BRIDGE_ISR_REQ_XTLK_ERR|BRIDGE_ISR_RESP_XTLK_ERR| \
240 - BRIDGE_ISR_BAD_XREQ_PKT|BRIDGE_ISR_BAD_XRESP_PKT| \
241 +#define BRIDGE_ISR_XTALK_ERROR \
242 + (BRIDGE_ISR_XREAD_REQ_TIMEOUT | \
243 + BRIDGE_ISR_XREQ_FIFO_OFLOW | \
244 + BRIDGE_ISR_UNSUPPORTED_XOP | \
245 + BRIDGE_ISR_INVLD_ADDR | \
246 + BRIDGE_ISR_REQ_XTLK_ERR | \
247 + BRIDGE_ISR_RESP_XTLK_ERR | \
248 + BRIDGE_ISR_BAD_XREQ_PKT | \
249 + BRIDGE_ISR_BAD_XRESP_PKT | \
250 BRIDGE_ISR_UNEXP_RESP)
252 -#define BRIDGE_ISR_ERRORS \
253 - (BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR| \
254 - BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR| \
255 +#define BRIDGE_ISR_ERRORS \
256 + (BRIDGE_ISR_LINK_ERROR | \
257 + BRIDGE_ISR_PCIBUS_ERROR | \
258 + BRIDGE_ISR_XTALK_ERROR | \
259 + BRIDGE_ISR_SSRAM_PERR | \
260 BRIDGE_ISR_PMU_ESIZE_FAULT)
262 -/*
263 - * List of Errors which are fatal and kill the system
264 - */
265 -#define BRIDGE_ISR_ERROR_FATAL \
266 - ((BRIDGE_ISR_XTALK_ERROR & ~BRIDGE_ISR_XREAD_REQ_TIMEOUT)|\
267 - BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY )
268 +/* List of Errors which are fatal and kill the system */
269 +#define BRIDGE_ISR_ERROR_FATAL \
270 + ((BRIDGE_ISR_XTALK_ERROR & \
271 + ~BRIDGE_ISR_XREAD_REQ_TIMEOUT) | \
272 + BRIDGE_ISR_PCI_SERR | \
273 + BRIDGE_ISR_PCI_PARITY)
275 -#define BRIDGE_ISR_ERROR_DUMP \
276 - (BRIDGE_ISR_PCIBUS_ERROR|BRIDGE_ISR_PMU_ESIZE_FAULT| \
277 - BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR)
278 +#define BRIDGE_ISR_ERROR_DUMP \
279 + (BRIDGE_ISR_PCIBUS_ERROR | \
280 + BRIDGE_ISR_PMU_ESIZE_FAULT | \
281 + BRIDGE_ISR_XTALK_ERROR | \
282 + BRIDGE_ISR_SSRAM_PERR)
284 /* Bridge interrupt enable register bits definition */
285 #define BRIDGE_IMR_UNEXP_RESP BRIDGE_ISR_UNEXP_RESP
286 @@ -577,60 +591,73 @@ typedef struct bridge_err_cmdword_s {
287 #define BRIDGE_IMR_INT(x) BRIDGE_ISR_INT(x)
289 /* Bridge interrupt reset register bits definition */
290 -#define BRIDGE_IRR_MULTI_CLR (0x1 << 6)
291 -#define BRIDGE_IRR_CRP_GRP_CLR (0x1 << 5)
292 -#define BRIDGE_IRR_RESP_BUF_GRP_CLR (0x1 << 4)
293 -#define BRIDGE_IRR_REQ_DSP_GRP_CLR (0x1 << 3)
294 -#define BRIDGE_IRR_LLP_GRP_CLR (0x1 << 2)
295 -#define BRIDGE_IRR_SSRAM_GRP_CLR (0x1 << 1)
296 -#define BRIDGE_IRR_PCI_GRP_CLR (0x1 << 0)
297 -#define BRIDGE_IRR_GIO_GRP_CLR (0x1 << 0)
298 +#define BRIDGE_IRR_MULTI_CLR BIT(6)
299 +#define BRIDGE_IRR_CRP_GRP_CLR BIT(5)
300 +#define BRIDGE_IRR_RESP_BUF_GRP_CLR BIT(4)
301 +#define BRIDGE_IRR_REQ_DSP_GRP_CLR BIT(3)
302 +#define BRIDGE_IRR_LLP_GRP_CLR BIT(2)
303 +#define BRIDGE_IRR_SSRAM_GRP_CLR BIT(1)
304 +#define BRIDGE_IRR_PCI_GRP_CLR BIT(0)
305 +#define BRIDGE_IRR_GIO_GRP_CLR BRIDGE_IRR_PCI_GRP_CLR
306 #define BRIDGE_IRR_ALL_CLR 0x7f
308 -#define BRIDGE_IRR_CRP_GRP (BRIDGE_ISR_UNEXP_RESP | \
309 - BRIDGE_ISR_XREQ_FIFO_OFLOW)
310 -#define BRIDGE_IRR_RESP_BUF_GRP (BRIDGE_ISR_BAD_XRESP_PKT | \
311 - BRIDGE_ISR_RESP_XTLK_ERR | \
312 - BRIDGE_ISR_XREAD_REQ_TIMEOUT)
313 -#define BRIDGE_IRR_REQ_DSP_GRP (BRIDGE_ISR_UNSUPPORTED_XOP | \
314 - BRIDGE_ISR_BAD_XREQ_PKT | \
315 - BRIDGE_ISR_REQ_XTLK_ERR | \
316 - BRIDGE_ISR_INVLD_ADDR)
317 -#define BRIDGE_IRR_LLP_GRP (BRIDGE_ISR_LLP_REC_SNERR | \
318 - BRIDGE_ISR_LLP_REC_CBERR | \
319 - BRIDGE_ISR_LLP_RCTY | \
320 - BRIDGE_ISR_LLP_TX_RETRY | \
321 - BRIDGE_ISR_LLP_TCTY)
322 -#define BRIDGE_IRR_SSRAM_GRP (BRIDGE_ISR_SSRAM_PERR | \
323 - BRIDGE_ISR_PMU_ESIZE_FAULT)
324 -#define BRIDGE_IRR_PCI_GRP (BRIDGE_ISR_PCI_ABORT | \
325 - BRIDGE_ISR_PCI_PARITY | \
326 - BRIDGE_ISR_PCI_SERR | \
327 - BRIDGE_ISR_PCI_PERR | \
328 - BRIDGE_ISR_PCI_MST_TIMEOUT | \
329 - BRIDGE_ISR_PCI_RETRY_CNT)
330 -
331 -#define BRIDGE_IRR_GIO_GRP (BRIDGE_ISR_GIO_B_ENBL_ERR | \
332 - BRIDGE_ISR_GIO_MST_TIMEOUT)
333 +#define BRIDGE_IRR_CRP_GRP \
334 + (BRIDGE_ISR_UNEXP_RESP | \
335 + BRIDGE_ISR_XREQ_FIFO_OFLOW)
336 +
337 +#define BRIDGE_IRR_RESP_BUF_GRP \
338 + (BRIDGE_ISR_BAD_XRESP_PKT | \
339 + BRIDGE_ISR_RESP_XTLK_ERR | \
340 + BRIDGE_ISR_XREAD_REQ_TIMEOUT)
341 +
342 +#define BRIDGE_IRR_REQ_DSP_GRP \
343 + (BRIDGE_ISR_UNSUPPORTED_XOP | \
344 + BRIDGE_ISR_BAD_XREQ_PKT | \
345 + BRIDGE_ISR_REQ_XTLK_ERR | \
346 + BRIDGE_ISR_INVLD_ADDR)
347 +
348 +#define BRIDGE_IRR_LLP_GRP \
349 + (BRIDGE_ISR_LLP_REC_SNERR | \
350 + BRIDGE_ISR_LLP_REC_CBERR | \
351 + BRIDGE_ISR_LLP_RCTY | \
352 + BRIDGE_ISR_LLP_TX_RETRY | \
353 + BRIDGE_ISR_LLP_TCTY)
354 +
355 +#define BRIDGE_IRR_SSRAM_GRP \
356 + (BRIDGE_ISR_SSRAM_PERR | \
357 + BRIDGE_ISR_PMU_ESIZE_FAULT)
358 +
359 +#define BRIDGE_IRR_PCI_GRP \
360 + (BRIDGE_ISR_PCI_ABORT | \
361 + BRIDGE_ISR_PCI_PARITY | \
362 + BRIDGE_ISR_PCI_SERR | \
363 + BRIDGE_ISR_PCI_PERR | \
364 + BRIDGE_ISR_PCI_MST_TIMEOUT | \
365 + BRIDGE_ISR_PCI_RETRY_CNT)
366 +
367 +#define BRIDGE_IRR_GIO_GRP \
368 + (BRIDGE_ISR_GIO_B_ENBL_ERR | \
369 + BRIDGE_ISR_GIO_MST_TIMEOUT)
371 /* Bridge INT_DEV register bits definition */
372 -#define BRIDGE_INT_DEV_SHFT(n) ((n)*3)
373 +#define BRIDGE_INT_DEV_SHFT(n) ((n) * 3)
374 #define BRIDGE_INT_DEV_MASK(n) (0x7 << BRIDGE_INT_DEV_SHFT(n))
375 #define BRIDGE_INT_DEV_SET(_dev, _line) (_dev << BRIDGE_INT_DEV_SHFT(_line))
377 /* Bridge interrupt(x) register bits definition */
378 -#define BRIDGE_INT_ADDR_HOST 0x0003FF00
379 -#define BRIDGE_INT_ADDR_FLD 0x000000FF
380 +#define BRIDGE_INT_ADDR_HOST GENMASK(17, 8)
381 +#define BRIDGE_INT_ADDR_FLD GENMASK(7, 0)
383 -#define BRIDGE_TMO_PCI_RETRY_HLD_MASK 0x1f0000
384 -#define BRIDGE_TMO_GIO_TIMEOUT_MASK 0x001000
385 -#define BRIDGE_TMO_PCI_RETRY_CNT_MASK 0x0003ff
386 +/* Bridge timeout register bits definition */
387 +#define BRIDGE_TMO_PCI_RETRY_HLD_MASK GENMASK(20, 16)
388 +#define BRIDGE_TMO_GIO_TIMEOUT_MASK BIT(12)
389 +#define BRIDGE_TMO_PCI_RETRY_CNT_MASK GENMASK(9, 0)
391 #define BRIDGE_TMO_PCI_RETRY_CNT_MAX 0x3ff
393 /*
394 * The NASID should be shifted by this amount and stored into the
395 - * interrupt(x) register.
396 + * interrupt(x) register. (IP27/IP35 only)
397 */
398 #define BRIDGE_INT_ADDR_NASID_SHFT 8
400 @@ -638,76 +665,82 @@ typedef struct bridge_err_cmdword_s {
401 * The BRIDGE_INT_ADDR_DEST_IO bit should be set to send an interrupt to
402 * memory.
403 */
404 -#define BRIDGE_INT_ADDR_DEST_IO (1 << 17)
405 +#define BRIDGE_INT_ADDR_DEST_IO BIT(17)
406 #define BRIDGE_INT_ADDR_DEST_MEM 0
407 -#define BRIDGE_INT_ADDR_MASK (1 << 17)
408 +#define BRIDGE_INT_ADDR_MASK BIT(17)
410 /* Bridge device(x) register bits definition */
411 -#define BRIDGE_DEV_ERR_LOCK_EN 0x10000000
412 -#define BRIDGE_DEV_PAGE_CHK_DIS 0x08000000
413 -#define BRIDGE_DEV_FORCE_PCI_PAR 0x04000000
414 -#define BRIDGE_DEV_VIRTUAL_EN 0x02000000
415 -#define BRIDGE_DEV_PMU_WRGA_EN 0x01000000
416 -#define BRIDGE_DEV_DIR_WRGA_EN 0x00800000
417 -#define BRIDGE_DEV_DEV_SIZE 0x00400000
418 -#define BRIDGE_DEV_RT 0x00200000
419 -#define BRIDGE_DEV_SWAP_PMU 0x00100000
420 -#define BRIDGE_DEV_SWAP_DIR 0x00080000
421 -#define BRIDGE_DEV_PREF 0x00040000
422 -#define BRIDGE_DEV_PRECISE 0x00020000
423 -#define BRIDGE_DEV_COH 0x00010000
424 -#define BRIDGE_DEV_BARRIER 0x00008000
425 -#define BRIDGE_DEV_GBR 0x00004000
426 -#define BRIDGE_DEV_DEV_SWAP 0x00002000
427 -#define BRIDGE_DEV_DEV_IO_MEM 0x00001000
428 -#define BRIDGE_DEV_OFF_MASK 0x00000fff
429 +#define BRIDGE_DEV_ERR_LOCK_EN BIT(28)
430 +#define BRIDGE_DEV_PAGE_CHK_DIS BIT(27)
431 +#define BRIDGE_DEV_FORCE_PCI_PAR BIT(26)
432 +#define BRIDGE_DEV_VIRTUAL_EN BIT(25)
433 +#define BRIDGE_DEV_PMU_WRGA_EN BIT(24)
434 +#define BRIDGE_DEV_DIR_WRGA_EN BIT(23)
435 +#define BRIDGE_DEV_DEV_SIZE BIT(22)
436 +#define BRIDGE_DEV_RT BIT(21)
437 +#define BRIDGE_DEV_SWAP_PMU BIT(20)
438 +#define BRIDGE_DEV_SWAP_DIR BIT(19)
439 +#define BRIDGE_DEV_PREF BIT(18)
440 +#define BRIDGE_DEV_PRECISE BIT(17)
441 +#define BRIDGE_DEV_COH BIT(16)
442 +#define BRIDGE_DEV_BARRIER BIT(15)
443 +#define BRIDGE_DEV_GBR BIT(14)
444 +#define BRIDGE_DEV_DEV_SWAP BIT(13)
445 +#define BRIDGE_DEV_DEV_IO_MEM BIT(12)
446 +#define BRIDGE_DEV_OFF_MASK GENMASK(11, 0)
447 #define BRIDGE_DEV_OFF_ADDR_SHFT 20
449 -#define BRIDGE_DEV_PMU_BITS (BRIDGE_DEV_PMU_WRGA_EN | \
450 - BRIDGE_DEV_SWAP_PMU)
451 -#define BRIDGE_DEV_D32_BITS (BRIDGE_DEV_DIR_WRGA_EN | \
452 - BRIDGE_DEV_SWAP_DIR | \
453 - BRIDGE_DEV_PREF | \
454 - BRIDGE_DEV_PRECISE | \
455 - BRIDGE_DEV_COH | \
456 - BRIDGE_DEV_BARRIER)
457 -#define BRIDGE_DEV_D64_BITS (BRIDGE_DEV_DIR_WRGA_EN | \
458 - BRIDGE_DEV_SWAP_DIR | \
459 - BRIDGE_DEV_COH | \
460 - BRIDGE_DEV_BARRIER)
461 +#define BRIDGE_DEV_PMU_BITS \
462 + (BRIDGE_DEV_PMU_WRGA_EN | \
463 + BRIDGE_DEV_SWAP_PMU)
464 +
465 +#define BRIDGE_DEV_D32_BITS \
466 + (BRIDGE_DEV_DIR_WRGA_EN | \
467 + BRIDGE_DEV_SWAP_DIR | \
468 + BRIDGE_DEV_PREF | \
469 + BRIDGE_DEV_PRECISE | \
470 + BRIDGE_DEV_COH | \
471 + BRIDGE_DEV_BARRIER)
472 +
473 +#define BRIDGE_DEV_D64_BITS \
474 + (BRIDGE_DEV_DIR_WRGA_EN | \
475 + BRIDGE_DEV_SWAP_DIR | \
476 + BRIDGE_DEV_COH | \
477 + BRIDGE_DEV_BARRIER)
479 /* Bridge Error Upper register bit field definition */
480 -#define BRIDGE_ERRUPPR_DEVMASTER (0x1 << 20) /* Device was master */
481 -#define BRIDGE_ERRUPPR_PCIVDEV (0x1 << 19) /* Virtual Req value */
482 +#define BRIDGE_ERRUPPR_DEVMASTER BIT(20) /* Device was master */
483 +#define BRIDGE_ERRUPPR_PCIVDEV BIT(19) /* Virtual Req value */
484 #define BRIDGE_ERRUPPR_DEVNUM_SHFT (16)
485 #define BRIDGE_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT)
486 -#define BRIDGE_ERRUPPR_DEVICE(err) (((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7)
487 -#define BRIDGE_ERRUPPR_ADDRMASK (0xFFFF)
488 +#define BRIDGE_ERRUPPR_DEVICE(err) \
489 + (((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7)
490 +#define BRIDGE_ERRUPPR_ADDRMASK GENMASK(15, 0)
492 /* Bridge interrupt mode register bits definition */
493 -#define BRIDGE_INTMODE_CLR_PKT_EN(x) (0x1 << (x))
494 +#define BRIDGE_INTMODE_CLR_PKT_EN(x) BIT((x))
496 -/* this should be written to the xbow's link_control(x) register */
497 -#define BRIDGE_CREDIT 3
498 +/* This should be written to the XBOW's link_control(x) register */
499 +#define BRIDGE_CREDIT 3
501 -/* RRB assignment register */
502 -#define BRIDGE_RRB_EN 0x8 /* after shifting down */
503 -#define BRIDGE_RRB_DEV 0x7 /* after shifting down */
504 -#define BRIDGE_RRB_VDEV 0x4 /* after shifting down */
505 -#define BRIDGE_RRB_PDEV 0x3 /* after shifting down */
506 +/* RRB assignment register -- value applies after shifting down */
507 +#define BRIDGE_RRB_EN 0x8
508 +#define BRIDGE_RRB_DEV 0x7
509 +#define BRIDGE_RRB_VDEV 0x4
510 +#define BRIDGE_RRB_PDEV 0x3
512 /* RRB status register */
513 -#define BRIDGE_RRB_VALID(r) (0x00010000<<(r))
514 -#define BRIDGE_RRB_INUSE(r) (0x00000001<<(r))
515 +#define BRIDGE_RRB_VALID(r) (0x00010000 << (r))
516 +#define BRIDGE_RRB_INUSE(r) (0x00000001 << (r))
518 /* RRB clear register */
519 -#define BRIDGE_RRB_CLEAR(r) (0x00000001<<(r))
520 +#define BRIDGE_RRB_CLEAR(r) (0x00000001 << (r))
522 -/* xbox system controller declarations */
523 -#define XBOX_BRIDGE_WID 8
524 -#define FLASH_PROM1_BASE 0xE00000 /* To read the xbox sysctlr status */
525 -#define XBOX_RPS_EXISTS 1 << 6 /* RPS bit in status register */
526 -#define XBOX_RPS_FAIL 1 << 4 /* RPS status bit in register */
527 +/* Xbox system controller declarations */
528 +#define XBOX_BRIDGE_WID 8
529 +#define FLASH_PROM1_BASE 0xe00000 /* Read Xbox sysctlr stat */
530 +#define XBOX_RPS_EXISTS BIT(6) /* RPS bit in status reg */
531 +#define XBOX_RPS_FAIL BIT(4) /* RPS status bit in reg */
533 /* ========================================================================
534 */
535 @@ -716,12 +749,12 @@ typedef struct bridge_err_cmdword_s {
536 * refer to section 4.2.1 of Bridge Spec for xtalk to PCI/GIO PIO mappings
537 */
538 /* XTALK addresses that map into Bridge Bus addr space */
539 -#define BRIDGE_PIO32_XTALK_ALIAS_BASE 0x000040000000L
540 -#define BRIDGE_PIO32_XTALK_ALIAS_LIMIT 0x00007FFFFFFFL
541 -#define BRIDGE_PIO64_XTALK_ALIAS_BASE 0x000080000000L
542 -#define BRIDGE_PIO64_XTALK_ALIAS_LIMIT 0x0000BFFFFFFFL
543 -#define BRIDGE_PCIIO_XTALK_ALIAS_BASE 0x000100000000L
544 -#define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT 0x0001FFFFFFFFL
545 +#define BRIDGE_PIO32_XTALK_ALIAS_BASE 0x000040000000UL
546 +#define BRIDGE_PIO32_XTALK_ALIAS_LIMIT 0x00007fffffffUL
547 +#define BRIDGE_PIO64_XTALK_ALIAS_BASE 0x000080000000UL
548 +#define BRIDGE_PIO64_XTALK_ALIAS_LIMIT 0x0000bfffffffUL
549 +#define BRIDGE_PCIIO_XTALK_ALIAS_BASE 0x000100000000UL
550 +#define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT 0x0001ffffffffUL
552 /* Ranges of PCI bus space that can be accessed via PIO from xtalk */
553 #define BRIDGE_MIN_PIO_ADDR_MEM 0x00000000 /* 1G PCI memory space */
554 @@ -753,15 +786,17 @@ typedef struct bridge_err_cmdword_s {
555 #define PCI32_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE
556 #define PCI32_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE
558 -#define IS_PCI32_LOCAL(x) ((ulong_t)(x) < PCI32_MAPPED_BASE)
559 -#define IS_PCI32_MAPPED(x) ((ulong_t)(x) < PCI32_DIRECT_BASE && \
560 - (ulong_t)(x) >= PCI32_MAPPED_BASE)
561 -#define IS_PCI32_DIRECT(x) ((ulong_t)(x) >= PCI32_MAPPED_BASE)
562 -#define IS_PCI64(x) ((ulong_t)(x) >= PCI64_BASE)
563 -
564 -/*
565 - * The GIO address space.
566 - */
567 +#define IS_PCI32_LOCAL(x) \
568 + ((ulong_t)(x) < PCI32_MAPPED_BASE)
569 +#define IS_PCI32_MAPPED(x) \
570 + ((ulong_t)(x) < PCI32_DIRECT_BASE && \
571 + (ulong_t)(x) >= PCI32_MAPPED_BASE)
572 +#define IS_PCI32_DIRECT(x) \
573 + ((ulong_t)(x) >= PCI32_MAPPED_BASE)
574 +#define IS_PCI64(x) \
575 + ((ulong_t)(x) >= PCI64_BASE)
576 +
577 +/* GIO address space. */
578 /* Xtalk to GIO PIO */
579 #define BRIDGE_GIO_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE
580 #define BRIDGE_GIO_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT
581 @@ -772,29 +807,33 @@ typedef struct bridge_err_cmdword_s {
582 #define GIO_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE
583 #define GIO_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE
585 -#define IS_GIO_LOCAL(x) ((ulong_t)(x) < GIO_MAPPED_BASE)
586 -#define IS_GIO_MAPPED(x) ((ulong_t)(x) < GIO_DIRECT_BASE && \
587 - (ulong_t)(x) >= GIO_MAPPED_BASE)
588 -#define IS_GIO_DIRECT(x) ((ulong_t)(x) >= GIO_MAPPED_BASE)
589 +#define IS_GIO_LOCAL(x) \
590 + ((ulong_t)(x) < GIO_MAPPED_BASE)
591 +#define IS_GIO_MAPPED(x) \
592 + ((ulong_t)(x) < GIO_DIRECT_BASE && \
593 + (ulong_t)(x) >= GIO_MAPPED_BASE)
594 +#define IS_GIO_DIRECT(x) \
595 + ((ulong_t)(x) >= GIO_MAPPED_BASE)
596 +
598 -/* PCI to xtalk mapping */
599 +/* PCI-to-Xtalk mapping */
601 /* given a DIR_OFF value and a pci/gio 32 bits direct address, determine
602 * which xtalk address is accessed
603 */
604 #define BRIDGE_DIRECT_32_SEG_SIZE BRIDGE_DMA_DIRECT_SIZE
605 -#define BRIDGE_DIRECT_32_TO_XTALK(dir_off,adr) \
606 - ((dir_off) * BRIDGE_DIRECT_32_SEG_SIZE + \
607 - ((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE)
608 +#define BRIDGE_DIRECT_32_TO_XTALK(dir_off, adr) \
609 + ((dir_off) * BRIDGE_DIRECT_32_SEG_SIZE + \
610 + ((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE)
612 /* 64-bit address attribute masks */
613 -#define PCI64_ATTR_TARG_MASK 0xf000000000000000
614 +#define PCI64_ATTR_TARG_MASK GENMASK_ULL(63, 60)
615 #define PCI64_ATTR_TARG_SHFT 60
616 -#define PCI64_ATTR_PREF 0x0800000000000000
617 -#define PCI64_ATTR_PREC 0x0400000000000000
618 -#define PCI64_ATTR_VIRTUAL 0x0200000000000000
619 -#define PCI64_ATTR_BAR 0x0100000000000000
620 -#define PCI64_ATTR_RMF_MASK 0x00ff000000000000
621 +#define PCI64_ATTR_PREF BIT_ULL(59)
622 +#define PCI64_ATTR_PREC BIT_ULL(58)
623 +#define PCI64_ATTR_VIRTUAL BIT_ULL(57)
624 +#define PCI64_ATTR_BAR BIT_ULL(56)
625 +#define PCI64_ATTR_RMF_MASK GENMASK_ULL(55, 48)
626 #define PCI64_ATTR_RMF_SHFT 48
628 #ifndef __ASSEMBLY__
629 @@ -815,33 +854,34 @@ typedef union ate_u {
630 } ate_t;
631 #endif /* !__ASSEMBLY__ */
633 -#define ATE_V 0x01
634 -#define ATE_CO 0x02
635 -#define ATE_PREC 0x04
636 -#define ATE_PREF 0x08
637 -#define ATE_BAR 0x10
638 +#define ATE_V 0x01
639 +#define ATE_CO 0x02
640 +#define ATE_PREC 0x04
641 +#define ATE_PREF 0x08
642 +#define ATE_BAR 0x10
644 #define ATE_PFNSHIFT 12
645 #define ATE_TIDSHIFT 8
646 #define ATE_RMFSHIFT 48
648 -#define mkate(xaddr, xid, attr) ((xaddr) & 0x0000fffffffff000ULL) | \
649 - ((xid)<<ATE_TIDSHIFT) | \
650 - (attr)
651 +#define mkate(xaddr, xid, attr) \
652 + (((xaddr) & 0x0000fffffffff000ULL) | \
653 + ((xid) << ATE_TIDSHIFT) | \
654 + (attr))
656 #define BRIDGE_INTERNAL_ATES 128
658 struct bridge_controller {
659 - struct pci_controller pc;
660 - struct resource mem;
661 - struct resource io;
662 - struct resource busn;
663 - bridge_t *base;
664 - nasid_t nasid;
665 - unsigned int widget_id;
666 - unsigned int irq_cpu;
667 - u64 baddr;
668 - unsigned int pci_int[8];
669 + struct pci_controller pc;
670 + struct resource mem;
671 + struct resource io;
672 + struct resource busn;
673 + bridge_t *base;
674 + nasid_t nasid;
675 + u32 widget_id;
676 + u32 irq_cpu;
677 + u64 baddr;
678 + u32 pci_int[8];
679 };
681 #define BRIDGE_CONTROLLER(bus) \