| blob | da80d882d212f11dea8f707790db4158b3bd73d8 |
1 diff --git a/arch/mips/pci/pci-bridge.c b/arch/mips/pci/pci-bridge.c
2 index 0f09eafa5e3a..a64ab146f30c 100644
3 --- a/arch/mips/pci/pci-bridge.c
4 +++ b/arch/mips/pci/pci-bridge.c
5 @@ -3,162 +3,238 @@
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 *
9 - * Copyright (C) 2003 Christoph Hellwig (hch@lst.de)
10 - * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org)
11 - * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
12 + * arch/mips/pci/pci-bridge.c
13 + * platform_driver for SGI BRIDGE/XBRIDGE (and in the future, SGI PIC) ASICs.
14 + *
15 + * Originally called pci-ip27.c, which is:
16 + * Copyright (C) 2003 Christoph Hellwig (hch@lst.de)
17 + * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org)
18 + * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
19 + *
20 + * Modifications sourced from pci-ip30.c in the IP30 patchset are:
21 + * Copyright (C) 2004-2007 Stanislaw Skowronek <skylark@unaligned.org>
22 + * Copyright (C) 2009 Johannes Dickgreber <tanzy@gmx.de>
23 + * Copyright (C) 2016 Joshua Kinard <kumba@gentoo.org>
24 + *
25 + * Functions/info/insight sourced from old IA64 code are:
26 + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc.
27 + * All rights reserved.
28 */
29 +
30 #include <linux/kernel.h>
31 -#include <linux/export.h>
32 #include <linux/pci.h>
33 -#include <linux/smp.h>
34 -#include <asm/sn/arch.h>
35 -#include <asm/pci/bridge.h>
36 +#include <linux/platform_device.h>
37 +
38 #include <asm/paccess.h>
39 -#include <asm/sn/intr.h>
40 -#include <asm/sn/sn0/hub.h>
41 +#include <asm/pci/bridge.h>
42 +#include <asm/xtalk/xtalk.h>
44 -/*
45 - * Max #PCI busses we can handle; ie, max #PCI bridges.
46 - */
47 -#define MAX_PCI_BUSSES 40
48 +#if defined(CONFIG_SGI_IP27)
49 +#include <asm/mach-ip27/pcibr.h>
50 +#else
51 +#error "Unknown CONFIG_SGI_IP??"
52 +#endif
54 -/*
55 - * Max #PCI devices (like scsi controllers) we handle on a bus.
56 - */
57 -#define MAX_DEVICES_PER_PCIBUS 8
58 +/* Increments for each additional bridge. */
59 +static int num_bridges;
61 +
62 +/* XXX: Temporary until the IP27 "mega update". */
63 /*
64 * XXX: No kmalloc available when we do our crosstalk scan,
65 - * we should try to move it later in the boot process.
66 + * we should try to move it later in the boot process.
67 */
68 -static struct bridge_controller bridges[MAX_PCI_BUSSES];
69 +static struct bridge_controller bridges[PCIBR_MAX_NUM_PCIBUS];
71 -/*
72 - * Translate from irq to software PCI bus number and PCI slot.
73 +/**
74 + * bridge_probe - probes a BRIDGE chip and configures it.
75 + * @nasid: NUMA Address Space Identifier.
76 + * @widget_id: s8 value of this BRIDGE's xtalk widget ID.
77 + * @masterwid: widget ID of HUB.
78 + *
79 + * Always returns '0'.
80 */
81 -struct bridge_controller *irq_to_bridge[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS];
82 -int irq_to_slot[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS];
83 -
84 -extern struct pci_ops bridge_pci_ops;
85 -
86 -int bridge_probe(nasid_t nasid, int widget_id, int masterwid)
87 +int
88 +bridge_probe(nasid_t nasid, int widget_id, int masterwid)
89 {
90 + u32 slot, reg;
91 + u32 wid_ctrl; /* BRIDGE WAR */
92 unsigned long offset = NODE_OFFSET(nasid);
93 struct bridge_controller *bc;
94 - static int num_bridges = 0;
95 - bridge_t *bridge;
96 - int slot;
97 -
98 - pci_set_flags(PCI_PROBE_ONLY);
100 - printk("a bridge\n");
101 -
102 - /* XXX: kludge alert.. */
103 + /* XXX: Temporary until the IP27 "mega update". */
104 + bc = &bridges[num_bridges];
105 if (!num_bridges)
106 ioport_resource.end = ~0UL;
108 - bc = &bridges[num_bridges];
109 -
110 - bc->pc.pci_ops = &bridge_pci_ops;
111 - bc->pc.mem_resource = &bc->mem;
112 - bc->pc.io_resource = &bc->io;
113 -
114 - bc->pc.index = num_bridges;
115 + /* Set bridge_controller parameters. */
116 + bc->pc.pci_ops = &bridge_pci_ops;
117 + bc->pc.mem_resource = &bc->mem;
118 + bc->pc.mem_offset = offset;
119 + bc->pc.io_resource = &bc->io;
120 + bc->pc.io_offset = offset;
121 + bc->pc.busn_resource = &bc->busn;
122 + bc->pc.index = num_bridges;
123 + bc->pc.io_map_base = NODE_SWIN_BASE(nasid, widget_id);
124 +
125 + bc->mem.name = "Bridge MEM";
126 + bc->mem.start = (NODE_SWIN_BASE(nasid, widget_id) + PCIBR_OFFSET_MEM);
127 + bc->mem.end = (NODE_SWIN_BASE(nasid, widget_id) + PCIBR_OFFSET_IO - 1);
128 + bc->mem.flags = IORESOURCE_MEM;
129 +
130 + bc->io.name = "Bridge IO";
131 + bc->io.start = (NODE_SWIN_BASE(nasid, widget_id) + PCIBR_OFFSET_IO);
132 + bc->io.end = (NODE_SWIN_BASE(nasid, widget_id) + PCIBR_OFFSET_END - 1);
133 + bc->io.flags = IORESOURCE_IO;
134 +
135 + bc->busn.name = "Bridge BUSN";
136 + bc->busn.start = num_bridges;
137 + bc->busn.end = 255;
138 + bc->busn.flags = IORESOURCE_BUS;
140 - bc->mem.name = "Bridge PCI MEM";
141 - bc->pc.mem_offset = offset;
142 - bc->mem.start = 0;
143 - bc->mem.end = ~0UL;
144 - bc->mem.flags = IORESOURCE_MEM;
145 -
146 - bc->io.name = "Bridge IO MEM";
147 - bc->pc.io_offset = offset;
148 - bc->io.start = 0UL;
149 - bc->io.end = ~0UL;
150 - bc->io.flags = IORESOURCE_IO;
151 -
152 - bc->irq_cpu = smp_processor_id();
153 bc->widget_id = widget_id;
154 bc->nasid = nasid;
155 + bc->baddr = ((u64)masterwid << PCI64_ATTR_TARG_SHFT);
156 +
157 + /* XXX: Kill */
158 + bc->irq_cpu = smp_processor_id();
160 - bc->baddr = (u64)masterwid << 60 | PCI64_ATTR_BAR;
161 + /* Point to this bridge. */
162 + bc->bridge = (struct bridge_widget __iomem *)
163 + RAW_NODE_SWIN_BASE(nasid, widget_id);
165 - /*
166 - * point to this bridge
167 - */
168 - bridge = (bridge_t *) RAW_NODE_SWIN_BASE(nasid, widget_id);
169 + /* Init the BRIDGE lock. */
170 + spin_lock_init(&bc->lock);
172 /*
173 - * Clear all pending interrupts.
174 + * On BRIDGEs prior to Rev D, set the PCI_RETRY_CNT to zero to avoid
175 + * dropping stores (WAR #475347).
176 + * Sourced from Linux-2.5.70/arch/ia64/sn/io/sn1/pcibr.c
177 */
178 - bridge->b_int_rst_stat = BRIDGE_IRR_ALL_CLR;
179 + if (XWIDGET_REV_NUM(bridge_read_reg(bc, b_wid_id)) < BRIDGE_REV_D) {
180 + reg = bridge_read_reg(bc, b_pci_bus_timo);
181 + bridge_write_reg((reg & ~(BRIDGE_BUS_PCI_RETRY_MASK)), bc,
182 + b_pci_bus_timo);
183 + }
184 +
185 + /* Clear all pending interrupts. */
186 + bridge_write_reg(BRIDGE_IRR_ALL_CLR, bc, b_int_reset_stat);
188 /*
189 - * Until otherwise set up, assume all interrupts are from slot 0
190 + * Until otherwise set up, assume all interrupts are from slot 7
191 */
192 - bridge->b_int_device = 0x0;
193 + bridge_write_reg(0xffffffff, bc, b_int_device);
194 +
195 + /* Configure BRIDGE widget control ... */
196 + wid_ctrl = bridge_read_reg(bc, b_wid_ctrl);
198 /*
199 - * swap pio's to pci mem and io space (big windows)
200 + * IP27 & IP35 need I/O and Mem swapping enabled.
201 + * IP30 needs it disabled.
202 */
203 - bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP |
204 - BRIDGE_CTRL_MEM_SWAP;
205 + wid_ctrl |= (BRIDGE_CTRL_IO_SWAP | BRIDGE_CTRL_MEM_SWAP);
206 +
207 + /* Set the BRIDGE PAGE_SIZE */
208 #ifdef CONFIG_PAGE_SIZE_4KB
209 - bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE;
210 + wid_ctrl &= ~BRIDGE_CTRL_PAGE_SIZE;
211 #else /* 16kB or larger */
212 - bridge->b_wid_control |= BRIDGE_CTRL_PAGE_SIZE;
213 + wid_ctrl |= BRIDGE_CTRL_PAGE_SIZE;
214 #endif
216 /*
217 - * Hmm... IRIX sets additional bits in the address which
218 - * are documented as reserved in the bridge docs.
219 + * Another BRIDGE WAR, read the BRIDGE widget control register
220 + * back after writing it to avoid an invalid address bug.
221 */
222 - bridge->b_wid_int_upper = 0x8000 | (masterwid << 16);
223 - bridge->b_wid_int_lower = 0x01800090; /* PI_INT_PEND_MOD off*/
224 - bridge->b_dir_map = (masterwid << 20); /* DMA */
225 - bridge->b_int_enable = 0;
226 + spin_lock(&bc->lock);
227 + bridge_write_reg(wid_ctrl, bc, b_wid_ctrl);
228 + wid_ctrl = bridge_read_reg(bc, b_wid_ctrl);
229 + spin_unlock(&bc->lock);
231 - for (slot = 0; slot < 8; slot ++) {
232 - bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR;
233 + /*
234 + * Set per-device properties.
235 + *
236 + * XXX: Setup per-slot configuration at some point. Different devices
237 + * need different properties.
238 + */
239 + for (slot = 0; slot < BRIDGE_MAX_DEVS; slot++) {
240 + reg = bridge_read_reg(bc, b_device(slot));
241 + reg &= ~BRIDGE_DEV_PAGE_CHK_DIS;
242 + reg |= (BRIDGE_DEV_ERR_LOCK_EN | BRIDGE_DEV_D64_BITS);
243 + reg &= ~(BRIDGE_DEV_WRGA_BITS | BRIDGE_DEV_BARRIER);
244 + reg &= ~BRIDGE_DEV_PREF;
245 +
246 + bridge_write_reg(reg, bc, b_device(slot));
247 bc->pci_int[slot] = -1;
248 }
249 - bridge->b_wid_tflush; /* wait until Bridge PIO complete */
251 - bc->base = bridge;
252 -
253 - register_pci_controller(&bc->pc);
254 + /* Configure direct-mapped DMA */
255 + reg = (masterwid << BRIDGE_DIRMAP_W_ID_SHFT);
256 + bridge_write_reg(reg, bc, b_dir_map);
258 + /*
259 + * Route all PCI bridge interrupts to the appropriate ASIC responsible
260 + * for handling IRQs (HUB in IP27, HEART in IP30, BEDROCK in IP35).
261 + * The actual IRQ support and masking is done elsewhere.
262 + */
263 + /*
264 + * XXX: IRIX sets additional bits (0x8000) in the address which are
265 + * marked as reserved in the BRIDGE docs.
266 + */
267 + bridge_write_reg(((masterwid << WIDGET_TARGET_ID_SHFT) | 0x8000), bc,
268 + b_wid_int_upper);
269 + bridge_write_reg(PCIBR_XIO_SEES_HUB, bc, b_wid_int_lower);
270 + bridge_write_reg(BRIDGE_COSMIC_INT_DEV, bc, b_int_device);
271 + bridge_write_reg(0, bc, b_int_mode);
272 + reg = bridge_read_reg(bc, b_int_enable);
273 + bridge_write_reg((reg | BRIDGE_ISR_ERRORS), bc, b_int_enable);
274 +
275 + /* Wait until Bridge PIO completes. */
276 + BRIDGE_FLUSH(bc);
277 +
278 + /* Increment number of discovered BRIDGE/XBRIDGE widgets. */
279 num_bridges++;
281 + register_pci_controller(&bc->pc);
282 +
283 return 0;
284 }
286 +/**
287 + * bridge_alloc_irq - allocate the next available IRQ for a BRIDGE slot.
288 + * @dev: pointer to struct pci_dev of PCI device info.
289 + *
290 + * Casts dev->bus->sysdata to struct bridge_controller and returns the
291 + * outcome of the platform_data-defined 'alloc_irq' function.
292 + */
293 +inline int
294 +bridge_alloc_irq(struct pci_dev *dev)
295 +{
296 + const struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
297 +
298 + if (bc->alloc_irq)
299 + return bc->alloc_irq(dev);
300 +
301 + return -1;
302 +}
303 +
304 /*
305 * All observed requests have pin == 1. We could have a global here, that
306 * gets incremented and returned every time - unfortunately, pci_map_irq
307 * may be called on the same device over and over, and need to return the
308 * same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7].
309 *
310 - * A given PCI device, in general, should be able to intr any of the cpus
311 - * on any one of the hubs connected to its xbow.
312 + * A given PCI device, in general, should be able to interrupt any of the
313 + * cpus on any one of the HUBs or HEART connected to its xbow.
314 */
315 -int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
316 +int
317 +pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
318 {
319 return 0;
320 }
322 -static inline struct pci_dev *bridge_root_dev(struct pci_dev *dev)
323 -{
324 - while (dev->bus->parent) {
325 - /* Move up the chain of bridges. */
326 - dev = dev->bus->self;
327 - }
328 -
329 - return dev;
330 -}
331 -
332 /* Do platform specific device initialization at pci_enable_device() time */
333 -int pcibios_plat_dev_init(struct pci_dev *dev)
334 +int
335 +pcibios_plat_dev_init(struct pci_dev *dev)
336 {
337 struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
338 struct pci_dev *rdev = bridge_root_dev(dev);
339 @@ -182,42 +258,36 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
340 return 0;
341 }
343 -/*
344 - * Device might live on a subordinate PCI bus. XXX Walk up the chain of buses
345 - * to find the slot number in sense of the bridge device register.
346 - * XXX This also means multiple devices might rely on conflicting bridge
347 - * settings.
348 - */
349 -
350 -static inline void pci_disable_swapping(struct pci_dev *dev)
351 +static void
352 +bridge_disable_swapping_dma(struct pci_dev *dev)
353 {
354 - struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
355 - bridge_t *bridge = bc->base;
356 + u32 reg;
357 int slot = PCI_SLOT(dev->devfn);
358 -
359 - /* Turn off byte swapping */
360 - bridge->b_device[slot].reg &= ~BRIDGE_DEV_SWAP_DIR;
361 - bridge->b_widget.w_tflush; /* Flush */
362 -}
363 -
364 -static inline void pci_enable_swapping(struct pci_dev *dev)
365 -{
366 struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
367 - bridge_t *bridge = bc->base;
368 - int slot = PCI_SLOT(dev->devfn);
370 - /* Turn on byte swapping */
371 - bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR;
372 - bridge->b_widget.w_tflush; /* Flush */
373 + /* Turn off byte swapping */
374 + spin_lock(&bc->lock);
375 + reg = bridge_read_reg(bc, b_device(slot));
376 + reg &= ~BRIDGE_DEV_SWAP_BITS;
377 + bridge_write_reg(reg, bc, b_device(slot));
378 + BRIDGE_FLUSH(bc);
379 + spin_unlock(&bc->lock);
380 }
382 -static void pci_fixup_ioc3(struct pci_dev *d)
383 -{
384 - pci_disable_swapping(d);
385 -}
386 +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
387 + bridge_disable_swapping_dma);
389 +/* XXX: Temporarily defined here until the IP27 "mega update". */
390 #ifdef CONFIG_NUMA
391 -int pcibus_to_node(struct pci_bus *bus)
392 +/**
393 + * pcibus_to_node - fetch the nasid that the passed struct pci_bus lives on.
394 + * @bus: struct pci_bus pointer for a given PCI bus.
395 + *
396 + * casts bus->sysdata to struct bridge_controller and returns the nasid
397 + * member that references the specific node this PCI bus lives on.
398 + */
399 +int
400 +pcibus_to_node(struct pci_bus *bus)
401 {
402 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
404 @@ -226,5 +296,3 @@ int pcibus_to_node(struct pci_bus *bus)
405 EXPORT_SYMBOL(pcibus_to_node);
406 #endif /* CONFIG_NUMA */
408 -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
409 - pci_fixup_ioc3);