| blob | edc35d498d6d13c69ccbd5d253cb9d85dab35f3f |
1 diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
2 index ff861420b8f5..e61545a1cc62 100644
3 --- a/arch/ia64/Kconfig
4 +++ b/arch/ia64/Kconfig
5 @@ -504,8 +504,6 @@ config IA64_HP_AML_NFW
6 the "force" module parameter, e.g., with the "aml_nfw.force"
7 kernel command line option.
9 -source "drivers/sn/Kconfig"
10 -
11 config KEXEC
12 bool "kexec system call"
13 depends on !IA64_HP_SIM && (!SMP || HOTPLUG_CPU)
14 diff --git a/arch/mips/include/asm/sgi/ioc3.h b/arch/mips/include/asm/sgi/ioc3.h
15 new file mode 100644
16 index 000000000000..53344eaaec9d
17 --- /dev/null
18 +++ b/arch/mips/include/asm/sgi/ioc3.h
19 @@ -0,0 +1,597 @@
20 +/*
21 + * Copyright (C) 1999, 2000 Ralf Baechle
22 + * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
23 + */
24 +#ifndef MIPS_SGI_IOC3_H
25 +#define MIPS_SGI_IOC3_H
26 +
27 +#include <linux/types.h>
28 +
29 +/* serial port register map */
30 +struct ioc3_serialregs {
31 + uint32_t sscr;
32 + uint32_t stpir;
33 + uint32_t stcir;
34 + uint32_t srpir;
35 + uint32_t srcir;
36 + uint32_t srtr;
37 + uint32_t shadow;
38 +};
39 +
40 +/* SUPERIO uart register map */
41 +struct ioc3_uartregs {
42 + union {
43 + char rbr; /* read only, DLAB == 0 */
44 + char thr; /* write only, DLAB == 0 */
45 + char dll; /* DLAB == 1 */
46 + } u1;
47 + union {
48 + char ier; /* DLAB == 0 */
49 + char dlm; /* DLAB == 1 */
50 + } u2;
51 + union {
52 + char iir; /* read only */
53 + char fcr; /* write only */
54 + } u3;
55 + char iu_lcr;
56 + char iu_mcr;
57 + char iu_lsr;
58 + char iu_msr;
59 + char iu_scr;
60 +};
61 +
62 +#define iu_rbr u1.rbr
63 +#define iu_thr u1.thr
64 +#define iu_dll u1.dll
65 +#define iu_ier u2.ier
66 +#define iu_dlm u2.dlm
67 +#define iu_iir u3.iir
68 +#define iu_fcr u3.fcr
69 +
70 +struct ioc3_sioregs {
71 + char fill[0x141]; /* starts at 0x141 */
72 +
73 + char uartc;
74 + char kbdcg;
75 +
76 + char fill0[0x150 - 0x142 - 1];
77 +
78 + char pp_data;
79 + char pp_dsr;
80 + char pp_dcr;
81 +
82 + char fill1[0x158 - 0x152 - 1];
83 +
84 + char pp_fifa;
85 + char pp_cfgb;
86 + char pp_ecr;
87 +
88 + char fill2[0x168 - 0x15a - 1];
89 +
90 + char rtcad;
91 + char rtcdat;
92 +
93 + char fill3[0x170 - 0x169 - 1];
94 +
95 + struct ioc3_uartregs uartb; /* 0x20170 */
96 + struct ioc3_uartregs uarta; /* 0x20178 */
97 +};
98 +
99 +/* Register layout of IOC3 in configuration space. */
100 +struct ioc3 {
101 + /* PCI Config Space registers */
102 + uint32_t pci_id; /* 0x00000 */
103 + uint32_t pci_scr; /* 0x00004 */
104 + uint32_t pci_rev; /* 0x00008 */
105 + uint32_t pci_lat; /* 0x0000c */
106 + uint32_t pci_addr; /* 0x00010 */
107 + uint32_t pci_err_addr_l; /* 0x00014 */
108 + uint32_t pci_err_addr_h; /* 0x00018 */
109 +
110 + uint32_t sio_ir; /* 0x0001c */
111 + uint32_t sio_ies; /* 0x00020 */
112 + uint32_t sio_iec; /* 0x00024 */
113 + uint32_t sio_cr; /* 0x00028 */
114 + uint32_t int_out; /* 0x0002c */
115 + uint32_t mcr; /* 0x00030 */
116 +
117 + /* General Purpose I/O registers */
118 + uint32_t gpcr_s; /* 0x00034 */
119 + uint32_t gpcr_c; /* 0x00038 */
120 + uint32_t gpdr; /* 0x0003c */
121 + uint32_t gppr[16]; /* 0x00040 */
122 +
123 + /* Parallel Port Registers */
124 + uint32_t ppbr_h_a; /* 0x00080 */
125 + uint32_t ppbr_l_a; /* 0x00084 */
126 + uint32_t ppcr_a; /* 0x00088 */
127 + uint32_t ppcr; /* 0x0008c */
128 + uint32_t ppbr_h_b; /* 0x00090 */
129 + uint32_t ppbr_l_b; /* 0x00094 */
130 + uint32_t ppcr_b; /* 0x00098 */
131 +
132 + /* Keyboard and Mouse Registers */
133 + uint32_t km_csr; /* 0x0009c */
134 + uint32_t k_rd; /* 0x000a0 */
135 + uint32_t m_rd; /* 0x000a4 */
136 + uint32_t k_wd; /* 0x000a8 */
137 + uint32_t m_wd; /* 0x000ac */
138 +
139 + /* Serial Port Registers */
140 + uint32_t sbbr_h; /* 0x000b0 */
141 + uint32_t sbbr_l; /* 0x000b4 */
142 + struct ioc3_serialregs port_a;
143 + struct ioc3_serialregs port_b;
144 +
145 + /* Ethernet Registers */
146 + uint32_t emcr; /* 0x000f0 */
147 + uint32_t eisr; /* 0x000f4 */
148 + uint32_t eier; /* 0x000f8 */
149 + uint32_t ercsr; /* 0x000fc */
150 + uint32_t erbr_h; /* 0x00100 */
151 + uint32_t erbr_l; /* 0x00104 */
152 + uint32_t erbar; /* 0x00108 */
153 + uint32_t ercir; /* 0x0010c */
154 + uint32_t erpir; /* 0x00110 */
155 + uint32_t ertr; /* 0x00114 */
156 + uint32_t etcsr; /* 0x00118 */
157 + uint32_t ersr; /* 0x0011c */
158 + uint32_t etcdc; /* 0x00120 */
159 + uint32_t ebir; /* 0x00124 */
160 + uint32_t etbr_h; /* 0x00128 */
161 + uint32_t etbr_l; /* 0x0012c */
162 + uint32_t etcir; /* 0x00130 */
163 + uint32_t etpir; /* 0x00134 */
164 + uint32_t emar_h; /* 0x00138 */
165 + uint32_t emar_l; /* 0x0013c */
166 + uint32_t ehar_h; /* 0x00140 */
167 + uint32_t ehar_l; /* 0x00144 */
168 + uint32_t micr; /* 0x00148 */
169 + uint32_t midr_r; /* 0x0014c */
170 + uint32_t midr_w; /* 0x00150 */
171 + uint32_t pad1[(0x20000 - 0x00154) / 4];
172 +
173 +
174 + /* SuperIO Registers XXX */
175 + struct ioc3_sioregs sregs; /* 0x20000 */
176 + uint32_t pad2[(0x40000 - 0x20180) / 4];
177 +
178 + /* SSRAM Diagnostic Access */
179 + uint32_t ssram[(0x80000 - 0x40000) / 4];
180 +
181 + /* Bytebus device offsets
182 + 0x80000 - Access to the generic devices selected with DEV0
183 + 0x9FFFF bytebus DEV_SEL_0
184 + 0xA0000 - Access to the generic devices selected with DEV1
185 + 0xBFFFF bytebus DEV_SEL_1
186 + 0xC0000 - Access to the generic devices selected with DEV2
187 + 0xDFFFF bytebus DEV_SEL_2
188 + 0xE0000 - Access to the generic devices selected with DEV3
189 + 0xFFFFF bytebus DEV_SEL_3 */
190 +};
191 +
192 +
193 +#define PCI_LAT 0xc /* Latency Timer */
194 +#define PCI_SCR_DROP_MODE_EN 0x00008000 /* drop pios on parity err */
195 +#define UARTA_BASE 0x178
196 +#define UARTB_BASE 0x170
197 +
198 +/*
199 + * Bytebus device space
200 + */
201 +#define IOC3_BYTEBUS_DEV0 0x80000L
202 +#define IOC3_BYTEBUS_DEV1 0xa0000L
203 +#define IOC3_BYTEBUS_DEV2 0xc0000L
204 +#define IOC3_BYTEBUS_DEV3 0xe0000L
205 +
206 +/*
207 + * Ethernet RX Buffer
208 + */
209 +struct ioc3_erxbuf {
210 + u32 w0; /* first word (valid,bcnt,cksum) */
211 + u32 err; /* second word various errors */
212 + /* next comes n bytes of padding */
213 + /* then the received ethernet frame itself */
214 +};
215 +
216 +#define ERXBUF_IPCKSUM_MASK 0x0000ffff
217 +#define ERXBUF_BYTECNT_MASK 0x07ff0000
218 +#define ERXBUF_BYTECNT_SHIFT 16
219 +#define ERXBUF_V 0x80000000
220 +
221 +#define ERXBUF_CRCERR 0x00000001 /* aka RSV15 */
222 +#define ERXBUF_FRAMERR 0x00000002 /* aka RSV14 */
223 +#define ERXBUF_CODERR 0x00000004 /* aka RSV13 */
224 +#define ERXBUF_INVPREAMB 0x00000008 /* aka RSV18 */
225 +#define ERXBUF_LOLEN 0x00007000 /* aka RSV2_0 */
226 +#define ERXBUF_HILEN 0x03ff0000 /* aka RSV12_3 */
227 +#define ERXBUF_MULTICAST 0x04000000 /* aka RSV16 */
228 +#define ERXBUF_BROADCAST 0x08000000 /* aka RSV17 */
229 +#define ERXBUF_LONGEVENT 0x10000000 /* aka RSV19 */
230 +#define ERXBUF_BADPKT 0x20000000 /* aka RSV20 */
231 +#define ERXBUF_GOODPKT 0x40000000 /* aka RSV21 */
232 +#define ERXBUF_CARRIER 0x80000000 /* aka RSV22 */
233 +
234 +/*
235 + * Ethernet TX Descriptor
236 + */
237 +#define ETXD_DATALEN 104
238 +struct ioc3_etxd {
239 + u32 cmd; /* command field */
240 + u32 bufcnt; /* buffer counts field */
241 + u64 p1; /* buffer pointer 1 */
242 + u64 p2; /* buffer pointer 2 */
243 + u8 data[ETXD_DATALEN]; /* opt. tx data */
244 +};
245 +
246 +#define ETXD_BYTECNT_MASK 0x000007ff /* total byte count */
247 +#define ETXD_INTWHENDONE 0x00001000 /* intr when done */
248 +#define ETXD_D0V 0x00010000 /* data 0 valid */
249 +#define ETXD_B1V 0x00020000 /* buf 1 valid */
250 +#define ETXD_B2V 0x00040000 /* buf 2 valid */
251 +#define ETXD_DOCHECKSUM 0x00080000 /* insert ip cksum */
252 +#define ETXD_CHKOFF_MASK 0x07f00000 /* cksum byte offset */
253 +#define ETXD_CHKOFF_SHIFT 20
254 +
255 +#define ETXD_D0CNT_MASK 0x0000007f
256 +#define ETXD_B1CNT_MASK 0x0007ff00
257 +#define ETXD_B1CNT_SHIFT 8
258 +#define ETXD_B2CNT_MASK 0x7ff00000
259 +#define ETXD_B2CNT_SHIFT 20
260 +
261 +/* ------------------------------------------------------------------------- */
262 +
263 +/* Superio Registers (PIO Access) */
264 +#define IOC3_SIO_BASE 0x20000
265 +#define IOC3_SIO_UARTC (IOC3_SIO_BASE+0x141) /* UART Config */
266 +#define IOC3_SIO_KBDCG (IOC3_SIO_BASE+0x142) /* KBD Config */
267 +#define IOC3_SIO_PP_BASE (IOC3_SIO_BASE+PP_BASE) /* Parallel Port */
268 +#define IOC3_SIO_RTC_BASE (IOC3_SIO_BASE+0x168) /* Real Time Clock */
269 +#define IOC3_SIO_UB_BASE (IOC3_SIO_BASE+UARTB_BASE) /* UART B */
270 +#define IOC3_SIO_UA_BASE (IOC3_SIO_BASE+UARTA_BASE) /* UART A */
271 +
272 +/* SSRAM Diagnostic Access */
273 +#define IOC3_SSRAM IOC3_RAM_OFF /* base of SSRAM diagnostic access */
274 +#define IOC3_SSRAM_LEN 0x40000 /* 256kb (addrspc sz, may not be populated) */
275 +#define IOC3_SSRAM_DM 0x0000ffff /* data mask */
276 +#define IOC3_SSRAM_PM 0x00010000 /* parity mask */
277 +
278 +/* bitmasks for PCI_SCR */
279 +#define PCI_SCR_PAR_RESP_EN 0x00000040 /* enb PCI parity checking */
280 +#define PCI_SCR_SERR_EN 0x00000100 /* enable the SERR# driver */
281 +#define PCI_SCR_DROP_MODE_EN 0x00008000 /* drop pios on parity err */
282 +#define PCI_SCR_RX_SERR (0x1 << 16)
283 +#define PCI_SCR_DROP_MODE (0x1 << 17)
284 +#define PCI_SCR_SIG_PAR_ERR (0x1 << 24)
285 +#define PCI_SCR_SIG_TAR_ABRT (0x1 << 27)
286 +#define PCI_SCR_RX_TAR_ABRT (0x1 << 28)
287 +#define PCI_SCR_SIG_MST_ABRT (0x1 << 29)
288 +#define PCI_SCR_SIG_SERR (0x1 << 30)
289 +#define PCI_SCR_PAR_ERR (0x1 << 31)
290 +
291 +/* bitmasks for IOC3_KM_CSR */
292 +#define KM_CSR_K_WRT_PEND 0x00000001 /* kbd port xmitting or resetting */
293 +#define KM_CSR_M_WRT_PEND 0x00000002 /* mouse port xmitting or resetting */
294 +#define KM_CSR_K_LCB 0x00000004 /* Line Cntrl Bit for last KBD write */
295 +#define KM_CSR_M_LCB 0x00000008 /* same for mouse */
296 +#define KM_CSR_K_DATA 0x00000010 /* state of kbd data line */
297 +#define KM_CSR_K_CLK 0x00000020 /* state of kbd clock line */
298 +#define KM_CSR_K_PULL_DATA 0x00000040 /* pull kbd data line low */
299 +#define KM_CSR_K_PULL_CLK 0x00000080 /* pull kbd clock line low */
300 +#define KM_CSR_M_DATA 0x00000100 /* state of ms data line */
301 +#define KM_CSR_M_CLK 0x00000200 /* state of ms clock line */
302 +#define KM_CSR_M_PULL_DATA 0x00000400 /* pull ms data line low */
303 +#define KM_CSR_M_PULL_CLK 0x00000800 /* pull ms clock line low */
304 +#define KM_CSR_EMM_MODE 0x00001000 /* emulation mode */
305 +#define KM_CSR_SIM_MODE 0x00002000 /* clock X8 */
306 +#define KM_CSR_K_SM_IDLE 0x00004000 /* Keyboard is idle */
307 +#define KM_CSR_M_SM_IDLE 0x00008000 /* Mouse is idle */
308 +#define KM_CSR_K_TO 0x00010000 /* Keyboard trying to send/receive */
309 +#define KM_CSR_M_TO 0x00020000 /* Mouse trying to send/receive */
310 +#define KM_CSR_K_TO_EN 0x00040000 /* KM_CSR_K_TO + KM_CSR_K_TO_EN = cause
311 + SIO_IR to assert */
312 +#define KM_CSR_M_TO_EN 0x00080000 /* KM_CSR_M_TO + KM_CSR_M_TO_EN = cause
313 + SIO_IR to assert */
314 +#define KM_CSR_K_CLAMP_1 0x00100000 /* Pull K_CLK low aft recv 1 char */
315 +#define KM_CSR_M_CLAMP_1 0x00200000 /* Pull M_CLK low aft recv 1 char */
316 +#define KM_CSR_K_CLAMP_3 0x00400000 /* Pull K_CLK low aft recv 3 chars */
317 +#define KM_CSR_M_CLAMP_3 0x00800000 /* Pull M_CLK low aft recv 3 chars */
318 +
319 +/* bitmasks for IOC3_K_RD and IOC3_M_RD */
320 +#define KM_RD_DATA_2 0x000000ff /* 3rd char recvd since last read */
321 +#define KM_RD_DATA_2_SHIFT 0
322 +#define KM_RD_DATA_1 0x0000ff00 /* 2nd char recvd since last read */
323 +#define KM_RD_DATA_1_SHIFT 8
324 +#define KM_RD_DATA_0 0x00ff0000 /* 1st char recvd since last read */
325 +#define KM_RD_DATA_0_SHIFT 16
326 +#define KM_RD_FRAME_ERR_2 0x01000000 /* framing or parity error in byte 2 */
327 +#define KM_RD_FRAME_ERR_1 0x02000000 /* same for byte 1 */
328 +#define KM_RD_FRAME_ERR_0 0x04000000 /* same for byte 0 */
329 +
330 +#define KM_RD_KBD_MSE 0x08000000 /* 0 if from kbd, 1 if from mouse */
331 +#define KM_RD_OFLO 0x10000000 /* 4th char recvd before this read */
332 +#define KM_RD_VALID_2 0x20000000 /* DATA_2 valid */
333 +#define KM_RD_VALID_1 0x40000000 /* DATA_1 valid */
334 +#define KM_RD_VALID_0 0x80000000 /* DATA_0 valid */
335 +#define KM_RD_VALID_ALL (KM_RD_VALID_0|KM_RD_VALID_1|KM_RD_VALID_2)
336 +
337 +/* bitmasks for IOC3_K_WD & IOC3_M_WD */
338 +#define KM_WD_WRT_DATA 0x000000ff /* write to keyboard/mouse port */
339 +#define KM_WD_WRT_DATA_SHIFT 0
340 +
341 +/* bitmasks for serial RX status byte */
342 +#define RXSB_OVERRUN 0x01 /* char(s) lost */
343 +#define RXSB_PAR_ERR 0x02 /* parity error */
344 +#define RXSB_FRAME_ERR 0x04 /* framing error */
345 +#define RXSB_BREAK 0x08 /* break character */
346 +#define RXSB_CTS 0x10 /* state of CTS */
347 +#define RXSB_DCD 0x20 /* state of DCD */
348 +#define RXSB_MODEM_VALID 0x40 /* DCD, CTS and OVERRUN are valid */
349 +#define RXSB_DATA_VALID 0x80 /* data byte, FRAME_ERR PAR_ERR & BREAK valid */
350 +
351 +/* bitmasks for serial TX control byte */
352 +#define TXCB_INT_WHEN_DONE 0x20 /* interrupt after this byte is sent */
353 +#define TXCB_INVALID 0x00 /* byte is invalid */
354 +#define TXCB_VALID 0x40 /* byte is valid */
355 +#define TXCB_MCR 0x80 /* data<7:0> to modem control register */
356 +#define TXCB_DELAY 0xc0 /* delay data<7:0> mSec */
357 +
358 +/* bitmasks for IOC3_SBBR_L */
359 +#define SBBR_L_SIZE 0x00000001 /* 0 == 1KB rings, 1 == 4KB rings */
360 +#define SBBR_L_BASE 0xfffff000 /* lower serial ring base addr */
361 +
362 +/* bitmasks for IOC3_SSCR_<A:B> */
363 +#define SSCR_RX_THRESHOLD 0x000001ff /* hiwater mark */
364 +#define SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */
365 +#define SSCR_HFC_EN 0x00020000 /* hardware flow control enabled */
366 +#define SSCR_RX_RING_DCD 0x00040000 /* post RX record on delta-DCD */
367 +#define SSCR_RX_RING_CTS 0x00080000 /* post RX record on delta-CTS */
368 +#define SSCR_HIGH_SPD 0x00100000 /* 4X speed */
369 +#define SSCR_DIAG 0x00200000 /* bypass clock divider for sim */
370 +#define SSCR_RX_DRAIN 0x08000000 /* drain RX buffer to memory */
371 +#define SSCR_DMA_EN 0x10000000 /* enable ring buffer DMA */
372 +#define SSCR_DMA_PAUSE 0x20000000 /* pause DMA */
373 +#define SSCR_PAUSE_STATE 0x40000000 /* sets when PAUSE takes effect */
374 +#define SSCR_RESET 0x80000000 /* reset DMA channels */
375 +
376 +/* all producer/consumer pointers are the same bitfield */
377 +#define PROD_CONS_PTR_4K 0x00000ff8 /* for 4K buffers */
378 +#define PROD_CONS_PTR_1K 0x000003f8 /* for 1K buffers */
379 +#define PROD_CONS_PTR_OFF 3
380 +
381 +/* bitmasks for IOC3_SRCIR_<A:B> */
382 +#define SRCIR_ARM 0x80000000 /* arm RX timer */
383 +
384 +/* bitmasks for IOC3_SRPIR_<A:B> */
385 +#define SRPIR_BYTE_CNT 0x07000000 /* bytes in packer */
386 +#define SRPIR_BYTE_CNT_SHIFT 24
387 +
388 +/* bitmasks for IOC3_STCIR_<A:B> */
389 +#define STCIR_BYTE_CNT 0x0f000000 /* bytes in unpacker */
390 +#define STCIR_BYTE_CNT_SHIFT 24
391 +
392 +/* bitmasks for IOC3_SHADOW_<A:B> */
393 +#define SHADOW_DR 0x00000001 /* data ready */
394 +#define SHADOW_OE 0x00000002 /* overrun error */
395 +#define SHADOW_PE 0x00000004 /* parity error */
396 +#define SHADOW_FE 0x00000008 /* framing error */
397 +#define SHADOW_BI 0x00000010 /* break interrupt */
398 +#define SHADOW_THRE 0x00000020 /* transmit holding register empty */
399 +#define SHADOW_TEMT 0x00000040 /* transmit shift register empty */
400 +#define SHADOW_RFCE 0x00000080 /* char in RX fifo has an error */
401 +#define SHADOW_DCTS 0x00010000 /* delta clear to send */
402 +#define SHADOW_DDCD 0x00080000 /* delta data carrier detect */
403 +#define SHADOW_CTS 0x00100000 /* clear to send */
404 +#define SHADOW_DCD 0x00800000 /* data carrier detect */
405 +#define SHADOW_DTR 0x01000000 /* data terminal ready */
406 +#define SHADOW_RTS 0x02000000 /* request to send */
407 +#define SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */
408 +#define SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */
409 +#define SHADOW_LOOP 0x10000000 /* loopback enabled */
410 +
411 +/* bitmasks for IOC3_SRTR_<A:B> */
412 +#define SRTR_CNT 0x00000fff /* reload value for RX timer */
413 +#define SRTR_CNT_VAL 0x0fff0000 /* current value of RX timer */
414 +#define SRTR_CNT_VAL_SHIFT 16
415 +#define SRTR_HZ 16000 /* SRTR clock frequency */
416 +
417 +/* bitmasks for IOC3_SIO_IR, IOC3_SIO_IEC and IOC3_SIO_IES */
418 +#define SIO_IR_SA_TX_MT 0x00000001 /* Serial port A TX empty */
419 +#define SIO_IR_SA_RX_FULL 0x00000002 /* port A RX buf full */
420 +#define SIO_IR_SA_RX_HIGH 0x00000004 /* port A RX hiwat */
421 +#define SIO_IR_SA_RX_TIMER 0x00000008 /* port A RX timeout */
422 +#define SIO_IR_SA_DELTA_DCD 0x00000010 /* port A delta DCD */
423 +#define SIO_IR_SA_DELTA_CTS 0x00000020 /* port A delta CTS */
424 +#define SIO_IR_SA_INT 0x00000040 /* port A pass-thru intr */
425 +#define SIO_IR_SA_TX_EXPLICIT 0x00000080 /* port A explicit TX thru */
426 +#define SIO_IR_SA_MEMERR 0x00000100 /* port A PCI error */
427 +#define SIO_IR_SB_TX_MT 0x00000200 /* */
428 +#define SIO_IR_SB_RX_FULL 0x00000400 /* */
429 +#define SIO_IR_SB_RX_HIGH 0x00000800 /* */
430 +#define SIO_IR_SB_RX_TIMER 0x00001000 /* */
431 +#define SIO_IR_SB_DELTA_DCD 0x00002000 /* */
432 +#define SIO_IR_SB_DELTA_CTS 0x00004000 /* */
433 +#define SIO_IR_SB_INT 0x00008000 /* */
434 +#define SIO_IR_SB_TX_EXPLICIT 0x00010000 /* */
435 +#define SIO_IR_SB_MEMERR 0x00020000 /* */
436 +#define SIO_IR_PP_INT 0x00040000 /* P port pass-thru intr */
437 +#define SIO_IR_PP_INTA 0x00080000 /* PP context A thru */
438 +#define SIO_IR_PP_INTB 0x00100000 /* PP context B thru */
439 +#define SIO_IR_PP_MEMERR 0x00200000 /* PP PCI error */
440 +#define SIO_IR_KBD_INT 0x00400000 /* kbd/mouse intr */
441 +#define SIO_IR_RT_INT 0x08000000 /* RT output pulse */
442 +#define SIO_IR_GEN_INT1 0x10000000 /* RT input pulse */
443 +#define SIO_IR_GEN_INT_SHIFT 28
444 +
445 +/* per device interrupt masks */
446 +#define SIO_IR_SA (SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL | \
447 + SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER | \
448 + SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS | \
449 + SIO_IR_SA_INT | SIO_IR_SA_TX_EXPLICIT | \
450 + SIO_IR_SA_MEMERR)
451 +#define SIO_IR_SB (SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL | \
452 + SIO_IR_SB_RX_HIGH | SIO_IR_SB_RX_TIMER | \
453 + SIO_IR_SB_DELTA_DCD | SIO_IR_SB_DELTA_CTS | \
454 + SIO_IR_SB_INT | SIO_IR_SB_TX_EXPLICIT | \
455 + SIO_IR_SB_MEMERR)
456 +#define SIO_IR_PP (SIO_IR_PP_INT | SIO_IR_PP_INTA | \
457 + SIO_IR_PP_INTB | SIO_IR_PP_MEMERR)
458 +#define SIO_IR_RT (SIO_IR_RT_INT | SIO_IR_GEN_INT1)
459 +
460 +/* bitmasks for SIO_CR */
461 +#define SIO_CR_SIO_RESET 0x00000001 /* reset the SIO */
462 +#define SIO_CR_SER_A_BASE 0x000000fe /* DMA poll addr port A */
463 +#define SIO_CR_SER_A_BASE_SHIFT 1
464 +#define SIO_CR_SER_B_BASE 0x00007f00 /* DMA poll addr port B */
465 +#define SIO_CR_SER_B_BASE_SHIFT 8
466 +#define SIO_SR_CMD_PULSE 0x00078000 /* byte bus strobe length */
467 +#define SIO_CR_CMD_PULSE_SHIFT 15
468 +#define SIO_CR_ARB_DIAG 0x00380000 /* cur !enet PCI requet (ro) */
469 +#define SIO_CR_ARB_DIAG_TXA 0x00000000
470 +#define SIO_CR_ARB_DIAG_RXA 0x00080000
471 +#define SIO_CR_ARB_DIAG_TXB 0x00100000
472 +#define SIO_CR_ARB_DIAG_RXB 0x00180000
473 +#define SIO_CR_ARB_DIAG_PP 0x00200000
474 +#define SIO_CR_ARB_DIAG_IDLE 0x00400000 /* 0 -> active request (ro) */
475 +
476 +/* bitmasks for INT_OUT */
477 +#define INT_OUT_COUNT 0x0000ffff /* pulse interval timer */
478 +#define INT_OUT_MODE 0x00070000 /* mode mask */
479 +#define INT_OUT_MODE_0 0x00000000 /* set output to 0 */
480 +#define INT_OUT_MODE_1 0x00040000 /* set output to 1 */
481 +#define INT_OUT_MODE_1PULSE 0x00050000 /* send 1 pulse */
482 +#define INT_OUT_MODE_PULSES 0x00060000 /* send 1 pulse every interval */
483 +#define INT_OUT_MODE_SQW 0x00070000 /* toggle output every interval */
484 +#define INT_OUT_DIAG 0x40000000 /* diag mode */
485 +#define INT_OUT_INT_OUT 0x80000000 /* current state of INT_OUT */
486 +
487 +/* time constants for INT_OUT */
488 +#define INT_OUT_NS_PER_TICK (30 * 260) /* 30 ns PCI clock, divisor=260 */
489 +#define INT_OUT_TICKS_PER_PULSE 3 /* outgoing pulse lasts 3 ticks */
490 +#define INT_OUT_US_TO_COUNT(x) /* convert uS to a count value */ \
491 + (((x) * 10 + INT_OUT_NS_PER_TICK / 200) * \
492 + 100 / INT_OUT_NS_PER_TICK - 1)
493 +#define INT_OUT_COUNT_TO_US(x) /* convert count value to uS */ \
494 + (((x) + 1) * INT_OUT_NS_PER_TICK / 1000)
495 +#define INT_OUT_MIN_TICKS 3 /* min period is width of pulse in "ticks" */
496 +#define INT_OUT_MAX_TICKS INT_OUT_COUNT /* largest possible count */
497 +
498 +/* bitmasks for GPCR */
499 +#define GPCR_DIR 0x000000ff /* tristate pin input or output */
500 +#define GPCR_DIR_PIN(x) (1<<(x)) /* access one of the DIR bits */
501 +#define GPCR_EDGE 0x000f0000 /* extint edge or level sensitive */
502 +#define GPCR_EDGE_PIN(x) (1<<((x)+15)) /* access one of the EDGE bits */
503 +
504 +/* values for GPCR */
505 +#define GPCR_INT_OUT_EN 0x00100000 /* enable INT_OUT to pin 0 */
506 +#define GPCR_MLAN_EN 0x00200000 /* enable MCR to pin 8 */
507 +#define GPCR_DIR_SERA_XCVR 0x00000080 /* Port A Transceiver select enable */
508 +#define GPCR_DIR_SERB_XCVR 0x00000040 /* Port B Transceiver select enable */
509 +#define GPCR_DIR_PHY_RST 0x00000020 /* ethernet PHY reset enable */
510 +
511 +/* defs for some of the generic I/O pins */
512 +#define GPCR_PHY_RESET 0x20 /* pin is output to PHY reset */
513 +#define GPCR_UARTB_MODESEL 0x40 /* pin is output to port B mode sel */
514 +#define GPCR_UARTA_MODESEL 0x80 /* pin is output to port A mode sel */
515 +
516 +#define GPPR_PHY_RESET_PIN 5 /* GIO pin cntrlling phy reset */
517 +#define GPPR_UARTB_MODESEL_PIN 6 /* GIO pin cntrlling uart b mode sel */
518 +#define GPPR_UARTA_MODESEL_PIN 7 /* GIO pin cntrlling uart a mode sel */
519 +
520 +/* ethernet */
521 +#define EMCR_DUPLEX 0x00000001
522 +#define EMCR_PROMISC 0x00000002
523 +#define EMCR_PADEN 0x00000004
524 +#define EMCR_RXOFF_MASK 0x000001f8
525 +#define EMCR_RXOFF_SHIFT 3
526 +#define EMCR_RAMPAR 0x00000200
527 +#define EMCR_BADPAR 0x00000800
528 +#define EMCR_BUFSIZ 0x00001000
529 +#define EMCR_TXDMAEN 0x00002000
530 +#define EMCR_TXEN 0x00004000
531 +#define EMCR_RXDMAEN 0x00008000
532 +#define EMCR_RXEN 0x00010000
533 +#define EMCR_LOOPBACK 0x00020000
534 +#define EMCR_ARB_DIAG 0x001c0000
535 +#define EMCR_ARB_DIAG_IDLE 0x00200000
536 +#define EMCR_RST 0x80000000
537 +
538 +#define EISR_RXTIMERINT 0x00000001
539 +#define EISR_RXTHRESHINT 0x00000002
540 +#define EISR_RXOFLO 0x00000004
541 +#define EISR_RXBUFOFLO 0x00000008
542 +#define EISR_RXMEMERR 0x00000010
543 +#define EISR_RXPARERR 0x00000020
544 +#define EISR_TXEMPTY 0x00010000
545 +#define EISR_TXRTRY 0x00020000
546 +#define EISR_TXEXDEF 0x00040000
547 +#define EISR_TXLCOL 0x00080000
548 +#define EISR_TXGIANT 0x00100000
549 +#define EISR_TXBUFUFLO 0x00200000
550 +#define EISR_TXEXPLICIT 0x00400000
551 +#define EISR_TXCOLLWRAP 0x00800000
552 +#define EISR_TXDEFERWRAP 0x01000000
553 +#define EISR_TXMEMERR 0x02000000
554 +#define EISR_TXPARERR 0x04000000
555 +
556 +#define ERCSR_THRESH_MASK 0x000001ff /* enet RX threshold */
557 +#define ERCSR_RX_TMR 0x40000000 /* simulation only */
558 +#define ERCSR_DIAG_OFLO 0x80000000 /* simulation only */
559 +
560 +#define ERBR_ALIGNMENT 4096
561 +#define ERBR_L_RXRINGBASE_MASK 0xfffff000
562 +
563 +#define ERBAR_BARRIER_BIT 0x0100
564 +#define ERBAR_RXBARR_MASK 0xffff0000
565 +#define ERBAR_RXBARR_SHIFT 16
566 +
567 +#define ERCIR_RXCONSUME_MASK 0x00000fff
568 +
569 +#define ERPIR_RXPRODUCE_MASK 0x00000fff
570 +#define ERPIR_ARM 0x80000000
571 +
572 +#define ERTR_CNT_MASK 0x000007ff
573 +
574 +#define ETCSR_IPGT_MASK 0x0000007f
575 +#define ETCSR_IPGR1_MASK 0x00007f00
576 +#define ETCSR_IPGR1_SHIFT 8
577 +#define ETCSR_IPGR2_MASK 0x007f0000
578 +#define ETCSR_IPGR2_SHIFT 16
579 +#define ETCSR_NOTXCLK 0x80000000
580 +
581 +#define ETCDC_COLLCNT_MASK 0x0000ffff
582 +#define ETCDC_DEFERCNT_MASK 0xffff0000
583 +#define ETCDC_DEFERCNT_SHIFT 16
584 +
585 +#define ETBR_ALIGNMENT (64*1024)
586 +#define ETBR_L_RINGSZ_MASK 0x00000001
587 +#define ETBR_L_RINGSZ128 0
588 +#define ETBR_L_RINGSZ512 1
589 +#define ETBR_L_TXRINGBASE_MASK 0xffffc000
590 +
591 +#define ETCIR_TXCONSUME_MASK 0x0000ffff
592 +#define ETCIR_IDLE 0x80000000
593 +
594 +#define ETPIR_TXPRODUCE_MASK 0x0000ffff
595 +
596 +#define EBIR_TXBUFPROD_MASK 0x0000001f
597 +#define EBIR_TXBUFCONS_MASK 0x00001f00
598 +#define EBIR_TXBUFCONS_SHIFT 8
599 +#define EBIR_RXBUFPROD_MASK 0x007fc000
600 +#define EBIR_RXBUFPROD_SHIFT 14
601 +#define EBIR_RXBUFCONS_MASK 0xff800000
602 +#define EBIR_RXBUFCONS_SHIFT 23
603 +
604 +#define MICR_REGADDR_MASK 0x0000001f
605 +#define MICR_PHYADDR_MASK 0x000003e0
606 +#define MICR_PHYADDR_SHIFT 5
607 +#define MICR_READTRIG 0x00000400
608 +#define MICR_BUSY 0x00000800
609 +
610 +#define MIDR_DATA_MASK 0x0000ffff
611 +
612 +#if defined(CONFIG_SGI_IP27) || defined(CONFIG_SGI_IP30)
613 +extern int bridge_alloc_irq(struct pci_dev *dev);
614 +#endif
615 +
616 +#endif /* MIPS_SGI_IOC3_H */
617 diff --git a/arch/mips/sgi-ip27/ip27-console.c b/arch/mips/sgi-ip27/ip27-console.c
618 index 45fdfbcbd4c6..225a13ee52f4 100644
619 --- a/arch/mips/sgi-ip27/ip27-console.c
620 +++ b/arch/mips/sgi-ip27/ip27-console.c
621 @@ -10,7 +10,7 @@
622 #include <asm/sn/addrs.h>
623 #include <asm/sn/sn0/hub.h>
624 #include <asm/sn/klconfig.h>
625 -#include <asm/sn/ioc3.h>
626 +#include <asm/sgi/ioc3.h>
627 #include <asm/sn/sn_private.h>
629 #include <linux/serial.h>
630 diff --git a/arch/mips/sgi-ip27/ip27-init.c b/arch/mips/sgi-ip27/ip27-init.c
631 index e501c43c02db..4a9c05c0b147 100644
632 --- a/arch/mips/sgi-ip27/ip27-init.c
633 +++ b/arch/mips/sgi-ip27/ip27-init.c
634 @@ -22,7 +22,7 @@
635 #include <asm/sn/sn0/hubni.h>
636 #include <asm/sn/sn0/hubio.h>
637 #include <asm/sn/klconfig.h>
638 -#include <asm/sn/ioc3.h>
639 +#include <asm/sgi/ioc3.h>
640 #include <asm/mipsregs.h>
641 #include <asm/sn/gda.h>
642 #include <asm/sn/hub.h>
643 diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
644 index 9d55247533a5..833744641b01 100644
645 --- a/arch/mips/sgi-ip27/ip27-timer.c
646 +++ b/arch/mips/sgi-ip27/ip27-timer.c
647 @@ -21,7 +21,7 @@
648 #include <asm/time.h>
649 #include <asm/pgtable.h>
650 #include <asm/sgialib.h>
651 -#include <asm/sn/ioc3.h>
652 +#include <asm/sgi/ioc3.h>
653 #include <asm/sn/klconfig.h>
654 #include <asm/sn/arch.h>
655 #include <asm/sn/addrs.h>
656 diff --git a/drivers/Makefile b/drivers/Makefile
657 index 24cd47014657..6485f1093e33 100644
658 --- a/drivers/Makefile
659 +++ b/drivers/Makefile
660 @@ -132,7 +132,6 @@ obj-y += mmc/
661 obj-$(CONFIG_MEMSTICK) += memstick/
662 obj-$(CONFIG_NEW_LEDS) += leds/
663 obj-$(CONFIG_INFINIBAND) += infiniband/
664 -obj-$(CONFIG_SGI_SN) += sn/
665 obj-y += firmware/
666 obj-$(CONFIG_CRYPTO) += crypto/
667 obj-$(CONFIG_SUPERH) += sh/
668 diff --git a/drivers/input/serio/Kconfig b/drivers/input/serio/Kconfig
669 index d90d9f1098ff..a8d8b72b3e9b 100644
670 --- a/drivers/input/serio/Kconfig
671 +++ b/drivers/input/serio/Kconfig
672 @@ -164,6 +164,19 @@ config SERIO_MACEPS2
673 To compile this driver as a module, choose M here: the
674 module will be called maceps2.
676 +config SERIO_SGI_IOC3
677 + tristate "SGI IOC3 PS/2 controller"
678 + depends on SGI_IOC3
679 + default y
680 + help
681 + Say Y here if you have an SGI Onyx2, SGI Octane or IOC3 PCI card
682 + and you want to attach and use a keyboard, mouse, or both.
683 +
684 + Do not use on an SGI Origin 2000, as the IO6 board in those
685 + systems lacks the necessary PS/2 ports. You will need to add
686 + an IOC3 PCI card (CADduo) via a PCI Shoehorn XIO card or the
687 + PCI Cardcage (shoebox) first.
688 +
689 config SERIO_LIBPS2
690 tristate "PS/2 driver library"
691 depends on SERIO_I8042 || SERIO_I8042=n
692 diff --git a/drivers/input/serio/Makefile b/drivers/input/serio/Makefile
693 index 67950a5ccb3f..6d97bad7b844 100644
694 --- a/drivers/input/serio/Makefile
695 +++ b/drivers/input/serio/Makefile
696 @@ -20,6 +20,7 @@ obj-$(CONFIG_HIL_MLC) += hp_sdc_mlc.o hil_mlc.o
697 obj-$(CONFIG_SERIO_PCIPS2) += pcips2.o
698 obj-$(CONFIG_SERIO_PS2MULT) += ps2mult.o
699 obj-$(CONFIG_SERIO_MACEPS2) += maceps2.o
700 +obj-$(CONFIG_SERIO_SGI_IOC3) += ioc3kbd.o
701 obj-$(CONFIG_SERIO_LIBPS2) += libps2.o
702 obj-$(CONFIG_SERIO_RAW) += serio_raw.o
703 obj-$(CONFIG_SERIO_AMS_DELTA) += ams_delta_serio.o
704 diff --git a/drivers/input/serio/ioc3kbd.c b/drivers/input/serio/ioc3kbd.c
705 new file mode 100644
706 index 000000000000..fd0771143535
707 --- /dev/null
708 +++ b/drivers/input/serio/ioc3kbd.c
709 @@ -0,0 +1,176 @@
710 +/*
711 + * SGI IOC3 PS/2 controller driver for linux
712 + *
713 + * Copyright (C) 2005 Stanislaw Skowronek <skylark@unaligned.org>
714 + * 2009 Johannes Dickgreber <tanzy@gmx.de>
715 + */
716 +
717 +#include <linux/delay.h>
718 +#include <linux/init.h>
719 +#include <linux/io.h>
720 +#include <linux/pci.h>
721 +#include <linux/serio.h>
722 +#include <linux/module.h>
723 +
724 +#include <linux/ioc3.h>
725 +
726 +struct ioc3kbd_data {
727 + struct ioc3_driver_data *idd;
728 + struct serio *kbd, *aux;
729 +};
730 +
731 +static int ioc3kbd_write(struct serio *dev, u8 val)
732 +{
733 + struct ioc3kbd_data *d = (struct ioc3kbd_data *)(dev->port_data);
734 + struct ioc3_driver_data *idd = d->idd;
735 + u32 mask;
736 + unsigned long timeout = 0;
737 +
738 + mask = (dev == d->aux) ? KM_CSR_M_WRT_PEND : KM_CSR_K_WRT_PEND;
739 + while ((readl(&idd->vma->km_csr) & mask) && (timeout < 1000)) {
740 + udelay(100);
741 + timeout++;
742 + }
743 +
744 + if (dev == d->aux)
745 + writel(((u32)val) & 0x000000ff, &idd->vma->m_wd);
746 + else
747 + writel(((u32)val) & 0x000000ff, &idd->vma->k_wd);
748 +
749 + if (timeout >= 1000)
750 + return -1;
751 + return 0;
752 +}
753 +
754 +static int ioc3kbd_intr(struct ioc3_submodule *is,
755 + struct ioc3_driver_data *idd, u32 irq)
756 +{
757 + struct ioc3kbd_data *d = (struct ioc3kbd_data *)(idd->data[is->id]);
758 + u32 data_k, data_m;
759 +
760 + ioc3_ack(is, idd, irq);
761 + data_k = readl(&idd->vma->k_rd);
762 + data_m = readl(&idd->vma->m_rd);
763 +
764 + if (data_k & KM_RD_VALID_0)
765 + serio_interrupt(d->kbd,
766 + (data_k >> KM_RD_DATA_0_SHIFT) & 0xff, 0);
767 + if (data_k & KM_RD_VALID_1)
768 + serio_interrupt(d->kbd,
769 + (data_k >> KM_RD_DATA_1_SHIFT) & 0xff, 0);
770 + if (data_k & KM_RD_VALID_2)
771 + serio_interrupt(d->kbd,
772 + (data_k >> KM_RD_DATA_2_SHIFT) & 0xff, 0);
773 + if (data_m & KM_RD_VALID_0)
774 + serio_interrupt(d->aux,
775 + (data_m >> KM_RD_DATA_0_SHIFT) & 0xff, 0);
776 + if (data_m & KM_RD_VALID_1)
777 + serio_interrupt(d->aux,
778 + (data_m >> KM_RD_DATA_1_SHIFT) & 0xff, 0);
779 + if (data_m & KM_RD_VALID_2)
780 + serio_interrupt(d->aux,
781 + (data_m >> KM_RD_DATA_2_SHIFT) & 0xff, 0);
782 +
783 + return 0;
784 +}
785 +
786 +static int ioc3kbd_open(struct serio *dev)
787 +{
788 + return 0;
789 +}
790 +
791 +static void ioc3kbd_close(struct serio *dev)
792 +{
793 + /* Empty */
794 +}
795 +
796 +static struct ioc3kbd_data *ioc3kbd_allocate_port(int idx,
797 + struct ioc3_driver_data *idd)
798 +{
799 + struct serio *sk, *sa;
800 + struct ioc3kbd_data *d;
801 +
802 + sk = devm_kzalloc(&idd->pdev->dev, sizeof(struct serio), GFP_KERNEL);
803 + sa = devm_kzalloc(&idd->pdev->dev, sizeof(struct serio), GFP_KERNEL);
804 + d = devm_kzalloc(&idd->pdev->dev, sizeof(struct ioc3kbd_data),
805 + GFP_KERNEL);
806 +
807 + if (sk && sa && d) {
808 + sk->id.type = SERIO_8042;
809 + sk->write = ioc3kbd_write;
810 + sk->open = ioc3kbd_open;
811 + sk->close = ioc3kbd_close;
812 + snprintf(sk->name, sizeof(sk->name), "IOC3 keyboard %d", idx);
813 + snprintf(sk->phys, sizeof(sk->phys), "ioc3/serio%dkbd", idx);
814 + sk->port_data = d;
815 + sk->dev.parent = &idd->pdev->dev;
816 +
817 + sa->id.type = SERIO_8042;
818 + sa->write = ioc3kbd_write;
819 + sa->open = ioc3kbd_open;
820 + sa->close = ioc3kbd_close;
821 + snprintf(sa->name, sizeof(sa->name), "IOC3 auxiliary %d", idx);
822 + snprintf(sa->phys, sizeof(sa->phys), "ioc3/serio%daux", idx);
823 + sa->port_data = d;
824 + sa->dev.parent = &idd->pdev->dev;
825 +
826 + d->idd = idd;
827 + d->kbd = sk;
828 + d->aux = sa;
829 + return d;
830 + }
831 +
832 + return NULL;
833 +}
834 +
835 +static int ioc3kbd_probe(struct ioc3_submodule *is,
836 + struct ioc3_driver_data *idd)
837 +{
838 + struct ioc3kbd_data *d;
839 +
840 + if ((idd->class != IOC3_CLASS_BASE_IP30) &&
841 + (idd->class != IOC3_CLASS_CADDUO))
842 + return 1;
843 +
844 + d = ioc3kbd_allocate_port(idd->id, idd);
845 + if (!d)
846 + return 1;
847 +
848 + idd->data[is->id] = d;
849 + ioc3_enable(is, idd, is->irq_mask);
850 + serio_register_port(d->kbd);
851 + serio_register_port(d->aux);
852 +
853 + return 0;
854 +}
855 +
856 +static int ioc3kbd_remove(struct ioc3_submodule *is,
857 + struct ioc3_driver_data *idd)
858 +{
859 + struct ioc3kbd_data *d = (struct ioc3kbd_data *)(idd->data[is->id]);
860 +
861 + ioc3_disable(is, idd, is->irq_mask);
862 + serio_unregister_port(d->kbd);
863 + serio_unregister_port(d->aux);
864 + idd->data[is->id] = NULL;
865 +
866 + return 0;
867 +}
868 +
869 +static struct ioc3_submodule ioc3kbd_driver = {
870 + .name = "serio",
871 + .probe = ioc3kbd_probe,
872 + .remove = ioc3kbd_remove,
873 + .irq_mask = SIO_IR_KBD_INT,
874 + .reset_mask = 1,
875 + .intr = ioc3kbd_intr,
876 + .owner = THIS_MODULE,
877 +};
878 +
879 +ioc3_submodule_driver(ioc3kbd_driver);
880 +
881 +MODULE_AUTHOR("Stanislaw Skowronek <skylark@unaligned.org>");
882 +MODULE_DESCRIPTION("SGI IOC3 serio driver");
883 +MODULE_LICENSE("GPL");
884 +MODULE_VERSION("R27");
885 +
886 diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
887 index 3726eacdf65d..c136fc0a6939 100644
888 --- a/drivers/misc/Kconfig
889 +++ b/drivers/misc/Kconfig
890 @@ -152,6 +152,18 @@ config INTEL_MID_PTI
891 an Intel Atom (non-netbook) mobile device containing a MIPI
892 P1149.7 standard implementation.
894 +config SGI_IOC3
895 + tristate "SGI IOC3 Base IO support"
896 + depends on PCI
897 + ---help---
898 + This option enables basic support for the SGI IOC3-based BaseIO
899 + controller card. This option does not enable any specific
900 + functions on such a card, but provides necessary infrastructure
901 + for other drivers to utilize.
902 +
903 + If you have an SGI Altix, Origin, Octane, or a PCI IOC3 card,
904 + then say Y. Otherwise say N.
905 +
906 config SGI_IOC4
907 tristate "SGI IOC4 Base IO support"
908 depends on PCI
909 diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
910 index af22bbc3d00c..449ecd4e3307 100644
911 --- a/drivers/misc/Makefile
912 +++ b/drivers/misc/Makefile
913 @@ -20,6 +20,7 @@ obj-$(CONFIG_PHANTOM) += phantom.o
914 obj-$(CONFIG_QCOM_COINCELL) += qcom-coincell.o
915 obj-$(CONFIG_SENSORS_BH1770) += bh1770glc.o
916 obj-$(CONFIG_SENSORS_APDS990X) += apds990x.o
917 +obj-$(CONFIG_SGI_IOC3) += ioc3.o
918 obj-$(CONFIG_SGI_IOC4) += ioc4.o
919 obj-$(CONFIG_ENCLOSURE_SERVICES) += enclosure.o
920 obj-$(CONFIG_KGDB_TESTS) += kgdbts.o
921 diff --git a/drivers/misc/ioc3.c b/drivers/misc/ioc3.c
922 new file mode 100644
923 index 000000000000..af60f232ddd1
924 --- /dev/null
925 +++ b/drivers/misc/ioc3.c
926 @@ -0,0 +1,938 @@
927 +/*
928 + * SGI IOC3 master driver and IRQ demuxer
929 + *
930 + * Copyright (c) 2005 Stanislaw Skowronek <skylark@unaligned.org>
931 + * Copyright (c) 2011-2014 Joshua Kinard <kumba@gentoo.org> (fixes, upkeep)
932 + * Heavily based on similar work by:
933 + * Brent Casavant <bcasavan@sgi.com> - IOC4 master driver
934 + * Pat Gefre <pfg@sgi.com> - IOC3 serial port IRQ demuxer
935 + */
936 +
937 +#include <linux/errno.h>
938 +#include <linux/module.h>
939 +#include <linux/pci.h>
940 +#include <linux/dma-mapping.h>
941 +#include <linux/interrupt.h>
942 +#include <linux/spinlock.h>
943 +#include <linux/delay.h>
944 +#include <linux/ioc3.h>
945 +#include <linux/rwsem.h>
946 +#include <linux/slab.h>
947 +
948 +#define IOC3_PCI_SIZE 0x100000
949 +
950 +/* Ethernet submodule is always 0 */
951 +#define ETH_ID 0
952 +
953 +static DECLARE_RWSEM(ioc3_devices_rwsem);
954 +static DEFINE_RWLOCK(ioc3_subm_lock);
955 +static LIST_HEAD(ioc3_devices);
956 +static struct ioc3_submodule *ioc3_subm[IOC3_MAX_SUBMODULES];
957 +static int ioc3_counter;
958 +
959 +/* ----------------------------------------------------------------------- */
960 +/* NIC probing code */
961 +
962 +static inline u32
963 +mcr_pack(u32 pulse, u32 sample)
964 +{
965 + return ((pulse << 10) | (sample << 2));
966 +}
967 +
968 +static int
969 +ioc3_nic_wait(struct ioc3_driver_data *idd)
970 +{
971 + u32 mcr;
972 +
973 + do {
974 + mcr = readl(&idd->vma->mcr);
975 + } while (!(mcr & 2));
976 +
977 + return (mcr & 1);
978 +}
979 +
980 +static int
981 +ioc3_nic_reset(struct ioc3_driver_data *idd)
982 +{
983 + int presence;
984 + unsigned long flags;
985 +
986 + local_irq_save(flags);
987 + writel(mcr_pack(500, 65), &idd->vma->mcr);
988 + presence = ioc3_nic_wait(idd);
989 + local_irq_restore(flags);
990 +
991 + udelay(500);
992 +
993 + return presence;
994 +}
995 +
996 +static int
997 +ioc3_nic_read_bit(struct ioc3_driver_data *idd)
998 +{
999 + int result;
1000 + unsigned long flags;
1001 +
1002 + local_irq_save(flags);
1003 + writel(mcr_pack(6, 13), &idd->vma->mcr);
1004 + result = ioc3_nic_wait(idd);
1005 + local_irq_restore(flags);
1006 +
1007 + udelay(500);
1008 +
1009 + return result;
1010 +}
1011 +
1012 +static void
1013 +ioc3_nic_write_bit(struct ioc3_driver_data *idd, int bit)
1014 +{
1015 + if (bit)
1016 + writel(mcr_pack(6, 110), &idd->vma->mcr);
1017 + else
1018 + writel(mcr_pack(80, 30), &idd->vma->mcr);
1019 +
1020 + ioc3_nic_wait(idd);
1021 +}
1022 +
1023 +static u32
1024 +ioc3_nic_read_byte(struct ioc3_driver_data *idd)
1025 +{
1026 + u32 result = 0;
1027 + int i;
1028 +
1029 + for (i = 0; i < 8; i++)
1030 + result = ((result >> 1) | (ioc3_nic_read_bit(idd) << 7));
1031 +
1032 + return result;
1033 +}
1034 +
1035 +static void
1036 +ioc3_nic_write_byte(struct ioc3_driver_data *idd, int byte)
1037 +{
1038 + int i, bit;
1039 +
1040 + for (i = 8; i; i--) {
1041 + bit = (byte & 1);
1042 + byte >>= 1;
1043 +
1044 + ioc3_nic_write_bit(idd, bit);
1045 + }
1046 +}
1047 +
1048 +static unsigned long
1049 +ioc3_nic_find(struct ioc3_driver_data *idd, int *last, unsigned long addr)
1050 +{
1051 + int a, b, index, disc;
1052 +
1053 + ioc3_nic_reset(idd);
1054 +
1055 + /* Search ROM. */
1056 + ioc3_nic_write_byte(idd, 0xf0);
1057 +
1058 + /* Algorithm from ``Book of iButton Standards''. */
1059 + for (index = 0, disc = 0; index < 64; index++) {
1060 + a = ioc3_nic_read_bit(idd);
1061 + b = ioc3_nic_read_bit(idd);
1062 +
1063 + if (unlikely(a && b)) {
1064 + pr_warn("ioc3: NIC search failed.\n");
1065 + *last = 0;
1066 + return 0;
1067 + }
1068 +
1069 + if (!a && !b) {
1070 + if (index == *last)
1071 + addr |= 1UL << index;
1072 + else if (index > *last) {
1073 + addr &= ~(1UL << index);
1074 + disc = index;
1075 + } else if ((addr & (1UL << index)) == 0)
1076 + disc = index;
1077 + ioc3_nic_write_bit(idd, (addr >> index) & 1);
1078 + continue;
1079 + } else {
1080 + if (a)
1081 + addr |= (1UL << index);
1082 + else
1083 + addr &= ~(1UL << index);
1084 + ioc3_nic_write_bit(idd, a);
1085 + continue;
1086 + }
1087 + }
1088 + *last = disc;
1089 + return addr;
1090 +}
1091 +
1092 +static void
1093 +ioc3_nic_addr(struct ioc3_driver_data *idd, unsigned long addr)
1094 +{
1095 + int index;
1096 +
1097 + ioc3_nic_reset(idd);
1098 + ioc3_nic_write_byte(idd, 0xf0);
1099 +
1100 + for (index = 0; index < 64; index++) {
1101 + ioc3_nic_read_bit(idd);
1102 + ioc3_nic_read_bit(idd);
1103 + ioc3_nic_write_bit(idd, ((addr >> index) & 1));
1104 + }
1105 +}
1106 +
1107 +static void
1108 +crc16_byte(u32 *crc, u8 db)
1109 +{
1110 + int i;
1111 +
1112 + for (i = 0; i < 8; i++) {
1113 + *crc <<= 1;
1114 + if ((db ^ (*crc >> 16)) & 1)
1115 + *crc ^= 0x8005;
1116 + db >>= 1;
1117 + }
1118 + *crc &= 0xffff;
1119 +}
1120 +
1121 +static u32
1122 +crc16_area(u8 *dbs, int size, u32 crc)
1123 +{
1124 + while (size--)
1125 + crc16_byte(&crc, *(dbs++));
1126 +
1127 + return crc;
1128 +}
1129 +
1130 +static void
1131 +crc8_byte(u32 *crc, u8 db)
1132 +{
1133 + int i, f;
1134 +
1135 + for (i = 0; i < 8; i++) {
1136 + f = ((*crc ^ db) & 1);
1137 + *crc >>= 1;
1138 + db >>= 1;
1139 + if (f)
1140 + *crc ^= 0x8c;
1141 + }
1142 + *crc &= 0xff;
1143 +}
1144 +
1145 +static u32
1146 +crc8_addr(unsigned long addr)
1147 +{
1148 + int i;
1149 + u32 crc = 0x00;
1150 +
1151 + for (i = 0; i < 8; i++)
1152 + crc8_byte(&crc, addr >> (i << 3));
1153 + return crc;
1154 +}
1155 +
1156 +static void
1157 +ioc3_read_redir_page(struct ioc3_driver_data *idd, unsigned long addr,
1158 + int page, u8 *redir, u8 *data)
1159 +{
1160 + int loops = 16, i;
1161 +
1162 + while (redir[page] != 0xff) {
1163 + page = (redir[page] ^ 0xff);
1164 + loops--;
1165 + if (unlikely(loops < 0)) {
1166 + pr_err("ioc3: NIC circular redirection\n");
1167 + return;
1168 + }
1169 + }
1170 +
1171 + loops = 3;
1172 + while (loops > 0) {
1173 + ioc3_nic_addr(idd, addr);
1174 + ioc3_nic_write_byte(idd, 0xf0);
1175 + ioc3_nic_write_byte(idd, (page << 5) & 0xe0);
1176 + ioc3_nic_write_byte(idd, (page >> 3) & 0x1f);
1177 +
1178 + for (i = 0; i < 0x20; i++)
1179 + data[i] = ioc3_nic_read_byte(idd);
1180 +
1181 + if (crc16_area(data, 0x20, 0x0000) == 0x800d)
1182 + return;
1183 +
1184 + loops--;
1185 + }
1186 +
1187 + pr_err("ioc3: CRC error in data page\n");
1188 + for (i = 0; i < 0x20; i++)
1189 + data[i] = 0x00;
1190 +}
1191 +
1192 +static void
1193 +ioc3_read_redir_map(struct ioc3_driver_data *idd, unsigned long addr,
1194 + u8 *redir)
1195 +{
1196 + int i, j, crc_ok, loops = 3;
1197 + u32 crc;
1198 +
1199 + while (loops > 0) {
1200 + crc_ok = 1;
1201 + ioc3_nic_addr(idd, addr);
1202 + ioc3_nic_write_byte(idd, 0xaa);
1203 + ioc3_nic_write_byte(idd, 0x00);
1204 + ioc3_nic_write_byte(idd, 0x01);
1205 +
1206 + for (i = 0; i < 64; i += 8) {
1207 + for (j = 0; j < 8; j++)
1208 + redir[i + j] = ioc3_nic_read_byte(idd);
1209 +
1210 + crc = crc16_area(redir + i, 8,
1211 + ((i == 0) ? 0x8707 : 0x0000));
1212 +
1213 + crc16_byte(&crc, ioc3_nic_read_byte(idd));
1214 + crc16_byte(&crc, ioc3_nic_read_byte(idd));
1215 +
1216 + if (crc != 0x800d)
1217 + crc_ok = 0;
1218 + }
1219 + if (crc_ok)
1220 + return;
1221 + loops--;
1222 + }
1223 + pr_err("ioc3: CRC error in redirection page\n");
1224 + for (i = 0; i < 64; i++)
1225 + redir[i] = 0xff;
1226 +}
1227 +
1228 +static void
1229 +ioc3_read_nic(struct ioc3_driver_data *idd, unsigned long addr)
1230 +{
1231 + u8 redir[64];
1232 + u8 data[64], part[32];
1233 + int i, j;
1234 +
1235 + /* Read redirections */
1236 + ioc3_read_redir_map(idd, addr, redir);
1237 +
1238 + /* Read data pages */
1239 + ioc3_read_redir_page(idd, addr, 0, redir, data);
1240 + ioc3_read_redir_page(idd, addr, 1, redir, (data + 32));
1241 +
1242 + /* Assemble the part # */
1243 + j = 0;
1244 + for (i = 0; i < 19; i++)
1245 + if (data[i + 11] != ' ')
1246 + part[j++] = data[i + 11];
1247 +
1248 + for (i = 0; i < 6; i++)
1249 + if (data[i + 32] != ' ')
1250 + part[j++] = data[i + 32];
1251 +
1252 + part[j] = 0;
1253 +
1254 + /* Skip Octane (IP30) power supplies */
1255 + if (!(strncmp(part, "060-0035-", 9)) ||
1256 + !(strncmp(part, "060-0038-", 9)) ||
1257 + !(strncmp(part, "060-0028-", 9)))
1258 + return;
1259 +
1260 + strlcpy(idd->nic_part, part, sizeof(idd->nic_part));
1261 +
1262 + /* Assemble the serial # */
1263 + j = 0;
1264 + for (i = 0; i < 10; i++)
1265 + if (data[i + 1] != ' ')
1266 + idd->nic_serial[j++] = data[i + 1];
1267 + idd->nic_serial[j] = 0;
1268 +}
1269 +
1270 +static void
1271 +ioc3_read_mac(struct ioc3_driver_data *idd, unsigned long addr)
1272 +{
1273 + int i, loops = 3;
1274 + u8 data[13];
1275 +
1276 + while (loops > 0) {
1277 + ioc3_nic_addr(idd, addr);
1278 + ioc3_nic_write_byte(idd, 0xf0);
1279 + ioc3_nic_write_byte(idd, 0x00);
1280 + ioc3_nic_write_byte(idd, 0x00);
1281 + ioc3_nic_read_byte(idd);
1282 +
1283 + for (i = 0; i < 13; i++)
1284 + data[i] = ioc3_nic_read_byte(idd);
1285 +
1286 + if (crc16_area(data, 13, 0x0000) == 0x800d) {
1287 + for (i = 10; i > 4; i--)
1288 + idd->nic_mac[10 - i] = data[i];
1289 + return;
1290 + }
1291 + loops--;
1292 + }
1293 +
1294 + pr_err("ioc3: CRC error in MAC address\n");
1295 + for (i = 0; i < 6; i++)
1296 + idd->nic_mac[i] = 0x00;
1297 +}
1298 +
1299 +static void
1300 +ioc3_probe_nic(struct ioc3_driver_data *idd)
1301 +{
1302 + int save = 0, loops = 3;
1303 + unsigned long first, addr;
1304 +
1305 + writel(GPCR_MLAN_EN, &idd->vma->gpcr_s);
1306 +
1307 + while (loops > 0) {
1308 + idd->nic_part[0] = 0;
1309 + idd->nic_serial[0] = 0;
1310 + first = ioc3_nic_find(idd, &save, 0);
1311 + addr = first;
1312 +
1313 + if (unlikely(!first))
1314 + return;
1315 +
1316 + while (1) {
1317 + if (crc8_addr(addr))
1318 + break;
1319 +
1320 + switch (addr & 0xff) {
1321 + case 0x0b:
1322 + ioc3_read_nic(idd, addr);
1323 + break;
1324 + case 0x09:
1325 + case 0x89:
1326 + case 0x91:
1327 + ioc3_read_mac(idd, addr);
1328 + break;
1329 + }
1330 +
1331 + addr = ioc3_nic_find(idd, &save, addr);
1332 + if (addr == first)
1333 + return;
1334 + }
1335 + loops--;
1336 + }
1337 + pr_err("ioc3: CRC error in NIC address\n");
1338 +}
1339 +/* ----------------------------------------------------------------------- */
1340 +
1341 +
1342 +/* ----------------------------------------------------------------------- */
1343 +/* Interrupt handling */
1344 +
1345 +void
1346 +ioc3_write_sio_ireg(struct ioc3_driver_data *idd, uint32_t value, int reg)
1347 +{
1348 + unsigned long flags;
1349 +
1350 + spin_lock_irqsave(&idd->ir_lock, flags);
1351 + switch (reg) {
1352 + case IOC3_W_IES:
1353 + writel(value, &idd->vma->sio_ies);
1354 + break;
1355 + case IOC3_W_IEC:
1356 + writel(value, &idd->vma->sio_iec);
1357 + break;
1358 + }
1359 + spin_unlock_irqrestore(&idd->ir_lock, flags);
1360 +}
1361 +
1362 +static inline u32
1363 +get_pending_intrs(struct ioc3_driver_data *idd)
1364 +{
1365 + u32 intrs = 0;
1366 + unsigned long flags;
1367 +
1368 + spin_lock_irqsave(&idd->ir_lock, flags);
1369 + intrs = readl(&idd->vma->sio_ir);
1370 + intrs &= readl(&idd->vma->sio_ies);
1371 + spin_unlock_irqrestore(&idd->ir_lock, flags);
1372 +
1373 + return intrs;
1374 +}
1375 +
1376 +static irqreturn_t
1377 +ioc3_intr_io(int irq, void *arg)
1378 +{
1379 + u32 pending;
1380 + int i, pending_sub, ret, handled = 1;
1381 + unsigned long flags;
1382 + struct ioc3_driver_data *idd = arg;
1383 +
1384 + read_lock_irqsave(&ioc3_subm_lock, flags);
1385 + /* Send Ethernet IRQ to the driver */
1386 + if (idd->active[ETH_ID] && !idd->dual_irq)
1387 + if (readl(&idd->vma->eisr))
1388 + handled = !ioc3_subm[ETH_ID]->intr(ioc3_subm[ETH_ID],
1389 + idd, 0);
1390 +
1391 + /* Look at the I/O IRQs */
1392 + pending = get_pending_intrs(idd);
1393 + for (i = 1; i < IOC3_MAX_SUBMODULES; i++) {
1394 + if (!idd->active[i])
1395 + continue;
1396 +
1397 + /* Check for pending interrupts from specific submodule. */
1398 + pending_sub = (pending & ioc3_subm[i]->irq_mask);
1399 + if (!pending_sub)
1400 + continue;
1401 +
1402 + /* Clear interrupt */
1403 + ioc3_write_sio_ireg(idd, ioc3_subm[i]->irq_mask,
1404 + IOC3_W_IEC);
1405 +
1406 + /* Call submodule interrupt, if defined. */
1407 + if (ioc3_subm[i]->intr) {
1408 + ret = ioc3_subm[i]->intr(ioc3_subm[i], idd,
1409 + pending_sub);
1410 + if (!ret) {
1411 + pending &= ~ioc3_subm[i]->irq_mask;
1412 + handled = 1;
1413 + }
1414 + }
1415 +
1416 + /* If .reset_mask is true, then re-enable the interrupt. */
1417 + if (ioc3_subm[i]->reset_mask)
1418 + ioc3_write_sio_ireg(idd, ioc3_subm[i]->irq_mask,
1419 + IOC3_W_IES);
1420 + }
1421 + read_unlock_irqrestore(&ioc3_subm_lock, flags);
1422 +
1423 + if (pending) {
1424 + pr_warn("ioc3: Pending IRQs 0x%08x discarded and disabled\n",
1425 + pending);
1426 + ioc3_write_sio_ireg(idd, pending, IOC3_W_IEC);
1427 + handled = 1;
1428 + }
1429 + return handled ? IRQ_HANDLED : IRQ_NONE;
1430 +}
1431 +
1432 +static irqreturn_t
1433 +ioc3_intr_eth(int irq, void *arg)
1434 +{
1435 + int handled = 0;
1436 + unsigned long flags;
1437 + struct ioc3_driver_data *idd = (struct ioc3_driver_data *)arg;
1438 +
1439 + read_lock_irqsave(&ioc3_subm_lock, flags);
1440 + if (idd->active[ETH_ID] && idd->dual_irq)
1441 + handled = !ioc3_subm[ETH_ID]->intr(ioc3_subm[ETH_ID], idd, 0);
1442 + read_unlock_irqrestore(&ioc3_subm_lock, flags);
1443 +
1444 + return handled ? IRQ_HANDLED : IRQ_NONE;
1445 +}
1446 +
1447 +void
1448 +ioc3_enable(struct ioc3_submodule *is, struct ioc3_driver_data *idd, u32 irqs)
1449 +{
1450 + ioc3_write_sio_ireg(idd, irqs & is->irq_mask, IOC3_W_IES);
1451 +}
1452 +EXPORT_SYMBOL_GPL(ioc3_enable);
1453 +
1454 +void
1455 +ioc3_ack(struct ioc3_submodule *is, struct ioc3_driver_data *idd, u32 irqs)
1456 +{
1457 + writel(irqs & is->irq_mask, &idd->vma->sio_ir);
1458 +}
1459 +EXPORT_SYMBOL_GPL(ioc3_ack);
1460 +
1461 +void
1462 +ioc3_disable(struct ioc3_submodule *is, struct ioc3_driver_data *idd, u32 irqs)
1463 +{
1464 + ioc3_write_sio_ireg(idd, irqs & is->irq_mask, IOC3_W_IEC);
1465 +}
1466 +EXPORT_SYMBOL_GPL(ioc3_disable);
1467 +/* ----------------------------------------------------------------------- */
1468 +
1469 +
1470 +
1471 +/* ----------------------------------------------------------------------- */
1472 +/* Misc functions */
1473 +void
1474 +ioc3_gpcr_set(struct ioc3_driver_data *idd, u32 val)
1475 +{
1476 + unsigned long flags;
1477 +
1478 + spin_lock_irqsave(&idd->gpio_lock, flags);
1479 + writel(val, &idd->vma->gpcr_s);
1480 + spin_unlock_irqrestore(&idd->gpio_lock, flags);
1481 +}
1482 +EXPORT_SYMBOL_GPL(ioc3_gpcr_set);
1483 +
1484 +/* IP27, IP30 writes to gpdr to set GPIOs to 1 */
1485 +/* XXX: Kill this soon. Octane LED driver still uses it. */
1486 +void
1487 +ioc3_gpio(struct ioc3_driver_data *idd, u32 mask, u32 val)
1488 +{
1489 + unsigned long flags;
1490 +
1491 + spin_lock_irqsave(&idd->gpio_lock, flags);
1492 + idd->gpdr_shadow &= ~mask;
1493 + idd->gpdr_shadow |= (val & mask);
1494 + writel(idd->gpdr_shadow, &idd->vma->gpdr);
1495 + spin_unlock_irqrestore(&idd->gpio_lock, flags);
1496 +}
1497 +EXPORT_SYMBOL_GPL(ioc3_gpio);
1498 +
1499 +/* Keep it simple, stupid! */
1500 +static inline int
1501 +find_slot(void **tab, int max)
1502 +{
1503 + int i;
1504 +
1505 + for (i = 1; i < max; i++)
1506 + if (!(tab[i]))
1507 + return i;
1508 +
1509 + return -1;
1510 +}
1511 +/* ----------------------------------------------------------------------- */
1512 +
1513 +
1514 +
1515 +/* ----------------------------------------------------------------------- */
1516 +/* IOC3 submodule reg/unreg */
1517 +
1518 +int
1519 +ioc3_register_submodule(struct ioc3_submodule *is)
1520 +{
1521 + struct ioc3_driver_data *idd;
1522 + int alloc_id;
1523 + unsigned long flags;
1524 +
1525 + write_lock_irqsave(&ioc3_subm_lock, flags);
1526 + if (is->ethernet)
1527 + if (ioc3_subm[ETH_ID] == NULL)
1528 + alloc_id = ETH_ID;
1529 + else
1530 + alloc_id = -2;
1531 + else
1532 + alloc_id = find_slot((void **)ioc3_subm, IOC3_MAX_SUBMODULES);
1533 +
1534 + if (alloc_id >= 0)
1535 + ioc3_subm[alloc_id] = is;
1536 + write_unlock_irqrestore(&ioc3_subm_lock, flags);
1537 +
1538 + if (alloc_id == -1) {
1539 + pr_warn("ioc3: Increase IOC3_MAX_SUBMODULES!\n");
1540 + return -ENOMEM;
1541 + }
1542 +
1543 + if (alloc_id == -2) {
1544 + pr_warn("ioc3: Ethernet module already registered~\n");
1545 + return -ENODEV;
1546 + }
1547 +
1548 + is->id = alloc_id;
1549 +
1550 + /* Initialize submodule for each IOC3 */
1551 + if (!is->probe)
1552 + return 0;
1553 +
1554 + down_read(&ioc3_devices_rwsem);
1555 + list_for_each_entry(idd, &ioc3_devices, list) {
1556 + /* Set to 1 for IRQs in probe */
1557 + idd->active[alloc_id] = 1;
1558 + idd->active[alloc_id] = !is->probe(is, idd);
1559 + }
1560 + up_read(&ioc3_devices_rwsem);
1561 +
1562 + return 0;
1563 +}
1564 +EXPORT_SYMBOL_GPL(ioc3_register_submodule);
1565 +
1566 +void
1567 +ioc3_unregister_submodule(struct ioc3_submodule *is)
1568 +{
1569 + struct ioc3_driver_data *idd;
1570 + unsigned long flags;
1571 +
1572 + write_lock_irqsave(&ioc3_subm_lock, flags);
1573 + if (ioc3_subm[is->id] == is)
1574 + ioc3_subm[is->id] = NULL;
1575 + else
1576 + pr_warn("ioc3: submodule %s has wrong ID.\n", is->name);
1577 + write_unlock_irqrestore(&ioc3_subm_lock, flags);
1578 +
1579 + /* Remove submodule for each IOC3 */
1580 + down_read(&ioc3_devices_rwsem);
1581 + list_for_each_entry(idd, &ioc3_devices, list) {
1582 + if (!idd->active[is->id])
1583 + continue;
1584 +
1585 + if (is->remove && is->remove(is, idd))
1586 + pr_warn("ioc3: submodule %s remove failed for pci_dev %s.\n",
1587 + module_name(is->owner), pci_name(idd->pdev));
1588 +
1589 + idd->active[is->id] = 0;
1590 + if (is->irq_mask)
1591 + ioc3_write_sio_ireg(idd, is->irq_mask, IOC3_W_IEC);
1592 + }
1593 + up_read(&ioc3_devices_rwsem);
1594 +}
1595 +EXPORT_SYMBOL_GPL(ioc3_unregister_submodule);
1596 +/* ----------------------------------------------------------------------- */
1597 +
1598 +
1599 +
1600 +/* ----------------------------------------------------------------------- */
1601 +/* Device management */
1602 +
1603 +static char
1604 +*ioc3_class_names[] = {
1605 + "Unknown",
1606 + "IP27 BaseIO",
1607 + "IP30 System Board",
1608 + "MENET 1/2/3",
1609 + "MENET 4",
1610 + "CADduo",
1611 + "Altix Serial"
1612 +};
1613 +
1614 +static int
1615 +ioc3_class(struct ioc3_driver_data *idd)
1616 +{
1617 + int res = IOC3_CLASS_NONE;
1618 +
1619 + /* NIC-based logic */
1620 + if (!strncmp(idd->nic_part, "030-0891-", 9))
1621 + res = IOC3_CLASS_BASE_IP30;
1622 +
1623 + if (!strncmp(idd->nic_part, "030-1155-", 9))
1624 + res = IOC3_CLASS_CADDUO;
1625 +
1626 + if (!strncmp(idd->nic_part, "030-1657-", 9))
1627 + res = IOC3_CLASS_SERIAL;
1628 +
1629 + if (!strncmp(idd->nic_part, "030-1664-", 9))
1630 + res = IOC3_CLASS_SERIAL;
1631 +
1632 + /* total random heuristics */
1633 +#ifdef CONFIG_SGI_IP27
1634 + if (!idd->nic_part[0])
1635 + res = IOC3_CLASS_BASE_IP27;
1636 +#endif
1637 +
1638 + /* Print the IOC3 part info */
1639 + pr_info("ioc3: part: [%s], serial: [%s] => class %s\n",
1640 + idd->nic_part, idd->nic_serial, ioc3_class_names[res]);
1641 +
1642 + return res;
1643 +}
1644 +
1645 +/* Adds a new instance of an IOC3 card */
1646 +static int
1647 +ioc3_probe(struct pci_dev *pdev, const struct pci_device_id *pci_id)
1648 +{
1649 + struct ioc3_driver_data *idd;
1650 + int ret = -ENODEV, id, io_irqno;
1651 +
1652 + /* Enable IOC3 and take ownership of it */
1653 + if (pci_enable_device(pdev)) {
1654 + pr_warn("ioc3: Failed to enable pci_dev %s.\n",
1655 + pci_name(pdev));
1656 + goto out;
1657 + }
1658 +
1659 + if (pci_request_regions(pdev, "ioc3")) {
1660 + pr_warn("ioc3: Unable to request region for pci_dev %s.\n",
1661 + pci_name(pdev));
1662 + goto out_disable_dev;
1663 + }
1664 +
1665 + pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
1666 + pci_set_master(pdev);
1667 +
1668 +#ifdef USE_64BIT_DMA
1669 + ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1670 + if (!ret) {
1671 + ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1672 + if (ret < 0)
1673 + pr_warn("ioc3: Unable to obtain 64-bit DMA for consistent allocations\n");
1674 + }
1675 +#endif
1676 +
1677 + /* Set up per-IOC3 data */
1678 + idd = kzalloc(sizeof(struct ioc3_driver_data), GFP_KERNEL);
1679 + if (!idd) {
1680 + ret = -ENOMEM;
1681 + goto out_release_regions;
1682 + }
1683 + spin_lock_init(&idd->ir_lock);
1684 + spin_lock_init(&idd->gpio_lock);
1685 + idd->pdev = pdev;
1686 +
1687 + /*
1688 + * Map all IOC3 registers. These are shared between subdevices
1689 + * so the main IOC3 module manages them.
1690 + */
1691 + idd->vma = pci_ioremap_bar(pdev, 0);
1692 + if (!idd->vma) {
1693 + pr_warn("ioc3: Unable to remap PCI BAR for %s.\n",
1694 + pci_name(pdev));
1695 + goto out_free_idd;
1696 + }
1697 +
1698 + /* Track PCI-device specific data */
1699 + pci_set_drvdata(pdev, idd);
1700 + down_write(&ioc3_devices_rwsem);
1701 + list_add_tail(&idd->list, &ioc3_devices);
1702 + idd->id = ioc3_counter++;
1703 + up_write(&ioc3_devices_rwsem);
1704 +
1705 + idd->gpdr_shadow = readl(&idd->vma->gpdr);
1706 +
1707 + ioc3_probe_nic(idd);
1708 +
1709 + idd->class = ioc3_class(idd);
1710 +
1711 + /* Clear IRQs */
1712 + ioc3_write_sio_ireg(idd, ~0, IOC3_W_IEC);
1713 + writel(~0, &idd->vma->sio_ir);
1714 +
1715 + /* Set up IRQs */
1716 + switch (idd->class) {
1717 + case IOC3_CLASS_BASE_IP27:
1718 + case IOC3_CLASS_BASE_IP30:
1719 +#if defined(CONFIG_SGI_IP27) || defined(CONFIG_SGI_IP30)
1720 + io_irqno = bridge_alloc_irq(pdev);
1721 +#else
1722 + io_irqno = (pdev->irq + 2);
1723 +#endif
1724 +
1725 + writel(0, &idd->vma->eier);
1726 + writel(~0, &idd->vma->eisr);
1727 +
1728 + idd->dual_irq = 1;
1729 + if (!request_irq(pdev->irq, ioc3_intr_eth, IRQF_SHARED,
1730 + "ioc3-eth", (void *)idd))
1731 + idd->irq_eth = pdev->irq;
1732 + else
1733 + pr_warn("ioc3: request_irq fails for IRQ 0x%x\n",
1734 + pdev->irq);
1735 +
1736 + if (!request_irq(io_irqno, ioc3_intr_io, IRQF_SHARED,
1737 + "ioc3-io", (void *)idd))
1738 + idd->irq_io = io_irqno;
1739 + else
1740 + pr_warn("ioc3: request_irq fails for IRQ 0x%x\n",
1741 + io_irqno);
1742 + break;
1743 + default:
1744 + if (!request_irq(pdev->irq, ioc3_intr_io, IRQF_SHARED,
1745 + "ioc3", (void *)idd))
1746 + idd->irq_io = pdev->irq;
1747 + else
1748 + pr_warn("ioc3: request_irq fails for IRQ 0x%x\n",
1749 + pdev->irq);
1750 + }
1751 +
1752 + /* Add this IOC3 to all submodules */
1753 + for (id = 0; id < IOC3_MAX_SUBMODULES; id++)
1754 + if (ioc3_subm[id] && ioc3_subm[id]->probe) {
1755 + /* Set to 1 for IRQs in probe */
1756 + idd->active[id] = 1;
1757 + idd->active[id] = !ioc3_subm[id]->probe(ioc3_subm[id],
1758 + idd);
1759 + }
1760 +
1761 + pr_info("IOC3 Master Driver loaded for %s\n", pci_name(pdev));
1762 +
1763 + return 0;
1764 +
1765 +out_free_idd:
1766 + kfree(idd);
1767 +
1768 +out_release_regions:
1769 + pci_release_regions(pdev);
1770 +
1771 +out_disable_dev:
1772 + pci_disable_device(pdev);
1773 +
1774 +out:
1775 + return ret;
1776 +}
1777 +
1778 +/* Removes a particular instance of an IOC3 card. */
1779 +static void
1780 +ioc3_remove(struct pci_dev *pdev)
1781 +{
1782 + int id;
1783 + struct ioc3_driver_data *idd;
1784 +
1785 + idd = pci_get_drvdata(pdev);
1786 +
1787 + /* Remove this IOC3 from all submodules */
1788 + for (id = 0; id < IOC3_MAX_SUBMODULES; id++) {
1789 + if (!idd->active[id])
1790 + continue;
1791 +
1792 + if (ioc3_subm[id] && ioc3_subm[id]->remove)
1793 + if (ioc3_subm[id]->remove(ioc3_subm[id], idd))
1794 + pr_warn("ioc3: submodule 0x%s remove failed for pci_dev %s.\n",
1795 + module_name(ioc3_subm[id]->owner),
1796 + pci_name(pdev));
1797 +
1798 + idd->active[id] = 0;
1799 + }
1800 +
1801 + /* Clear and disable all IRQs */
1802 + ioc3_write_sio_ireg(idd, ~0, IOC3_W_IEC);
1803 + writel(~0, &idd->vma->sio_ir);
1804 +
1805 + /* Release resources */
1806 + free_irq(idd->irq_io, (void *)idd);
1807 + if (idd->dual_irq)
1808 + free_irq(idd->irq_eth, (void *)idd);
1809 + iounmap(idd->vma);
1810 + pci_release_regions(pdev);
1811 +
1812 + /* Disable IOC3 and relinquish */
1813 + pci_disable_device(pdev);
1814 +
1815 + /* Remove and free driver data */
1816 + down_write(&ioc3_devices_rwsem);
1817 + list_del(&idd->list);
1818 + up_write(&ioc3_devices_rwsem);
1819 + kfree(idd);
1820 +}
1821 +
1822 +static struct
1823 +pci_device_id ioc3_id_table[] = {
1824 + {PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1825 + {0,},
1826 +};
1827 +MODULE_DEVICE_TABLE(pci, ioc3_id_table);
1828 +
1829 +static struct
1830 +pci_driver ioc3_driver = {
1831 + .name = "IOC3",
1832 + .id_table = ioc3_id_table,
1833 + .probe = ioc3_probe,
1834 + .remove = ioc3_remove,
1835 +};
1836 +/* ----------------------------------------------------------------------- */
1837 +
1838 +
1839 +
1840 +/* ----------------------------------------------------------------------- */
1841 +/* Module management */
1842 +
1843 +static int __init
1844 +ioc3_init(void)
1845 +{
1846 + return pci_register_driver(&ioc3_driver);
1847 +}
1848 +
1849 +static void __exit
1850 +ioc3_exit(void)
1851 +{
1852 + pci_unregister_driver(&ioc3_driver);
1853 +}
1854 +/* ----------------------------------------------------------------------- */
1855 +
1856 +
1857 +module_init(ioc3_init);
1858 +module_exit(ioc3_exit);
1859 +
1860 +MODULE_AUTHOR("Stanislaw Skowronek <skylark@unaligned.org>");
1861 +MODULE_AUTHOR("Joshua Kinard <kumba@gentoo.org>");
1862 +MODULE_DESCRIPTION("SGI IOC3 PCI driver");
1863 +MODULE_LICENSE("GPL");
1864 +
1865 diff --git a/drivers/net/ethernet/sgi/Kconfig b/drivers/net/ethernet/sgi/Kconfig
1866 index fbbb21c13e95..e304e4f957d0 100644
1867 --- a/drivers/net/ethernet/sgi/Kconfig
1868 +++ b/drivers/net/ethernet/sgi/Kconfig
1869 @@ -18,7 +18,7 @@ if NET_VENDOR_SGI
1871 config SGI_IOC3_ETH
1872 bool "SGI IOC3 Ethernet"
1873 - depends on PCI && SGI_IP27
1874 + depends on PCI && SGI_IOC3
1875 select CRC32
1876 select MII
1877 ---help---
1878 diff --git a/drivers/net/ethernet/sgi/ioc3-eth.c b/drivers/net/ethernet/sgi/ioc3-eth.c
1879 index e5d68cba4766..42db23d42250 100644
1880 --- a/drivers/net/ethernet/sgi/ioc3-eth.c
1881 +++ b/drivers/net/ethernet/sgi/ioc3-eth.c
1882 @@ -7,6 +7,8 @@
1883 *
1884 * Copyright (C) 1999, 2000, 01, 03, 06 Ralf Baechle
1885 * Copyright (C) 1995, 1999, 2000, 2001 by Silicon Graphics, Inc.
1886 + * Copyright (C) 2005 Stanislaw Skowronek (port to meta-driver)
1887 + * 2009 Johannes Dickgreber <tanzy@gmx.de>
1888 *
1889 * References:
1890 * o IOC3 ASIC specification 4.51, 1996-04-18
1891 @@ -20,513 +22,252 @@
1892 * o Use prefetching for large packets. What is a good lower limit for
1893 * prefetching?
1894 * o We're probably allocating a bit too much memory.
1895 - * o Use hardware checksums.
1896 - * o Convert to using a IOC3 meta driver.
1897 * o Which PHYs might possibly be attached to the IOC3 in real live,
1898 * which workarounds are required for them? Do we ever have Lucent's?
1899 * o For the 2.5 branch kill the mii-tool ioctls.
1900 */
1902 #define IOC3_NAME "ioc3-eth"
1903 -#define IOC3_VERSION "2.6.3-4"
1904 +#define IOC3_VERSION "0.42-meta"
1906 +#include <net/ip.h>
1907 +
1908 +#include <linux/crc32.h>
1909 #include <linux/delay.h>
1910 +#include <linux/etherdevice.h>
1911 +#include <linux/ethtool.h>
1912 +#include <linux/init.h>
1913 #include <linux/kernel.h>
1914 -#include <linux/mm.h>
1915 -#include <linux/errno.h>
1916 -#include <linux/module.h>
1917 -#include <linux/pci.h>
1918 -#include <linux/crc32.h>
1919 #include <linux/mii.h>
1920 -#include <linux/in.h>
1921 -#include <linux/ip.h>
1922 +#include <linux/netdevice.h>
1923 #include <linux/tcp.h>
1924 #include <linux/udp.h>
1925 -#include <linux/dma-mapping.h>
1926 +#include <linux/module.h>
1927 #include <linux/gfp.h>
1929 -#ifdef CONFIG_SERIAL_8250
1930 -#include <linux/serial_core.h>
1931 -#include <linux/serial_8250.h>
1932 -#include <linux/serial_reg.h>
1933 -#endif
1934 -
1935 -#include <linux/netdevice.h>
1936 -#include <linux/etherdevice.h>
1937 -#include <linux/ethtool.h>
1938 -#include <linux/skbuff.h>
1939 -#include <net/ip.h>
1940 +#include <linux/ioc3.h>
1942 -#include <asm/byteorder.h>
1943 -#include <asm/io.h>
1944 -#include <asm/pgtable.h>
1945 -#include <linux/uaccess.h>
1946 -#include <asm/sn/types.h>
1947 -#include <asm/sn/ioc3.h>
1948 #include <asm/pci/bridge.h>
1950 -/*
1951 - * 64 RX buffers. This is tunable in the range of 16 <= x < 512.
1952 +#define IOC3_CACHELINE 128UL
1953 +
1954 +/* 64 RX buffers. This is tunable in the range of 16 <= x < 512.
1955 * The value must be a power of two.
1956 */
1957 -#define RX_BUFFS 64
1958 +#define RX_BUFFS 512
1959 +#define RX_MASK (RX_BUFFS - 1)
1961 -#define ETCSR_FD ((17 << ETCSR_IPGR2_SHIFT) | (11 << ETCSR_IPGR1_SHIFT) | 21)
1962 -#define ETCSR_HD ((21 << ETCSR_IPGR2_SHIFT) | (21 << ETCSR_IPGR1_SHIFT) | 21)
1963 +/* 128 TX buffers (not tunable) */
1964 +#define TX_BUFFS 128
1965 +#define TX_MASK (TX_BUFFS - 1)
1966 +
1967 +/* BEWARE: The IOC3 documentation documents the size of rx buffers as
1968 + * 1644 while it's actually 1664. This one was nasty to track down...
1969 + */
1970 +#define RX_OFFSET 18
1971 +//#define RX_OFFSET 10 /* XXX: Old value */
1972 +#define RX_BUF_SIZE 1664
1973 +#define RX_BUF_ALLOC_SIZE (RX_BUF_SIZE + RX_OFFSET + IOC3_CACHELINE)
1974 +
1975 +/* DMA barrier to separate cached and uncached accesses. */
1976 +#define BARRIER() \
1977 + __asm__("sync" : : : "memory")
1979 -/* Private per NIC data of the driver. */
1980 +/* Private per NIC data of the driver. */
1981 struct ioc3_private {
1982 - struct ioc3 *regs;
1983 + struct ioc3_driver_data *idd;
1984 unsigned long *rxr; /* pointer to receiver ring */
1985 struct ioc3_etxd *txr;
1986 - struct sk_buff *rx_skbs[512];
1987 - struct sk_buff *tx_skbs[128];
1988 + struct sk_buff *rx_skbs[RX_BUFFS];
1989 + struct sk_buff *tx_skbs[TX_BUFFS];
1990 int rx_ci; /* RX consumer index */
1991 int rx_pi; /* RX producer index */
1992 int tx_ci; /* TX consumer index */
1993 int tx_pi; /* TX producer index */
1994 - int txqlen;
1995 + int txbfree;
1996 u32 emcr, ehar_h, ehar_l;
1997 spinlock_t ioc3_lock;
1998 struct mii_if_info mii;
1999 + unsigned long flags;
2000 + #define IOC3_FLAG_RX_CHECKSUMS 1
2002 struct net_device *dev;
2003 - struct pci_dev *pdev;
2005 /* Members used by autonegotiation */
2006 struct timer_list ioc3_timer;
2007 };
2009 -static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
2010 -static void ioc3_set_multicast_list(struct net_device *dev);
2011 -static int ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev);
2012 -static void ioc3_timeout(struct net_device *dev);
2013 -static inline u32 ioc3_hash(const u8 *addr);
2014 -static inline void ioc3_stop(struct ioc3_private *ip);
2015 -static void ioc3_init(struct net_device *dev);
2016 -
2017 -static const char ioc3_str[] = "IOC3 Ethernet";
2018 -static const struct ethtool_ops ioc3_ethtool_ops;
2019 -
2020 /* We use this to acquire receive skb's that we can DMA directly into. */
2021 -
2022 -#define IOC3_CACHELINE 128UL
2023 -
2024 static inline unsigned long
2025 aligned_rx_skb_addr(unsigned long addr)
2026 {
2027 - return (~addr + 1) & (IOC3_CACHELINE - 1UL);
2028 + return ((addr + 127) & ~127UL) - addr;
2029 }
2031 -static inline struct sk_buff *
2032 -ioc3_alloc_skb(unsigned long length, u32 gfp_mask)
2033 +static struct sk_buff *
2034 +ioc3_alloc_skb(struct net_device *dev)
2035 {
2036 struct sk_buff *skb;
2038 - skb = alloc_skb(length + IOC3_CACHELINE - 1, gfp_mask);
2039 + skb = alloc_skb(RX_BUF_ALLOC_SIZE + IOC3_CACHELINE - 1, GFP_ATOMIC);
2040 if (likely(skb)) {
2041 int offset = aligned_rx_skb_addr((unsigned long) skb->data);
2042 if (offset)
2043 skb_reserve(skb, offset);
2044 + skb->dev = dev;
2045 }
2047 return skb;
2048 }
2050 -static inline unsigned long
2051 -ioc3_map(void *ptr, unsigned long vdev)
2052 +static unsigned long
2053 +ioc3_map(void *ptr, unsigned long dma_attr)
2054 {
2055 #ifdef CONFIG_SGI_IP27
2056 - vdev <<= 57; /* Shift to PCI64_ATTR_VIRTUAL */
2057 -
2058 - return vdev | (0xaUL << PCI64_ATTR_TARG_SHFT) | PCI64_ATTR_PREF |
2059 - ((unsigned long)ptr & TO_PHYS_MASK);
2060 + return ((0xaUL << PCI64_ATTR_TARG_SHFT) | dma_attr |
2061 + ((unsigned long)ptr & TO_PHYS_MASK));
2062 #else
2063 return virt_to_bus(ptr);
2064 #endif
2065 }
2067 -/* BEWARE: The IOC3 documentation documents the size of rx buffers as
2068 - * 1644 while it's actually 1664. This one was nasty to track down...
2069 - */
2070 -#define RX_OFFSET 10
2071 -#define RX_BUF_ALLOC_SIZE (1664 + RX_OFFSET + IOC3_CACHELINE)
2072 -
2073 -/* DMA barrier to separate cached and uncached accesses. */
2074 -#define BARRIER() \
2075 - __asm__("sync" ::: "memory")
2076 -
2077 -
2078 -#define IOC3_SIZE 0x100000
2079 -
2080 -/* IOC3 is a big endian device
2081 - *
2082 - * Unorthodox but makes the users of these macros more readable - the pointer
2083 - * to the IOC3's memory mapped registers is expected as struct ioc3 * ioc3
2084 - * in the environment.
2085 - */
2086 -#define ioc3_r_mcr() be32_to_cpu(ioc3->mcr)
2087 -#define ioc3_w_mcr(v) do { ioc3->mcr = cpu_to_be32(v); } while (0)
2088 -#define ioc3_w_gpcr_s(v) do { ioc3->gpcr_s = cpu_to_be32(v); } while (0)
2089 -#define ioc3_r_emcr() be32_to_cpu(ioc3->emcr)
2090 -#define ioc3_w_emcr(v) do { ioc3->emcr = cpu_to_be32(v); } while (0)
2091 -#define ioc3_r_eisr() be32_to_cpu(ioc3->eisr)
2092 -#define ioc3_w_eisr(v) do { ioc3->eisr = cpu_to_be32(v); } while (0)
2093 -#define ioc3_r_eier() be32_to_cpu(ioc3->eier)
2094 -#define ioc3_w_eier(v) do { ioc3->eier = cpu_to_be32(v); } while (0)
2095 -#define ioc3_r_ercsr() be32_to_cpu(ioc3->ercsr)
2096 -#define ioc3_w_ercsr(v) do { ioc3->ercsr = cpu_to_be32(v); } while (0)
2097 -#define ioc3_r_erbr_h() be32_to_cpu(ioc3->erbr_h)
2098 -#define ioc3_w_erbr_h(v) do { ioc3->erbr_h = cpu_to_be32(v); } while (0)
2099 -#define ioc3_r_erbr_l() be32_to_cpu(ioc3->erbr_l)
2100 -#define ioc3_w_erbr_l(v) do { ioc3->erbr_l = cpu_to_be32(v); } while (0)
2101 -#define ioc3_r_erbar() be32_to_cpu(ioc3->erbar)
2102 -#define ioc3_w_erbar(v) do { ioc3->erbar = cpu_to_be32(v); } while (0)
2103 -#define ioc3_r_ercir() be32_to_cpu(ioc3->ercir)
2104 -#define ioc3_w_ercir(v) do { ioc3->ercir = cpu_to_be32(v); } while (0)
2105 -#define ioc3_r_erpir() be32_to_cpu(ioc3->erpir)
2106 -#define ioc3_w_erpir(v) do { ioc3->erpir = cpu_to_be32(v); } while (0)
2107 -#define ioc3_r_ertr() be32_to_cpu(ioc3->ertr)
2108 -#define ioc3_w_ertr(v) do { ioc3->ertr = cpu_to_be32(v); } while (0)
2109 -#define ioc3_r_etcsr() be32_to_cpu(ioc3->etcsr)
2110 -#define ioc3_w_etcsr(v) do { ioc3->etcsr = cpu_to_be32(v); } while (0)
2111 -#define ioc3_r_ersr() be32_to_cpu(ioc3->ersr)
2112 -#define ioc3_w_ersr(v) do { ioc3->ersr = cpu_to_be32(v); } while (0)
2113 -#define ioc3_r_etcdc() be32_to_cpu(ioc3->etcdc)
2114 -#define ioc3_w_etcdc(v) do { ioc3->etcdc = cpu_to_be32(v); } while (0)
2115 -#define ioc3_r_ebir() be32_to_cpu(ioc3->ebir)
2116 -#define ioc3_w_ebir(v) do { ioc3->ebir = cpu_to_be32(v); } while (0)
2117 -#define ioc3_r_etbr_h() be32_to_cpu(ioc3->etbr_h)
2118 -#define ioc3_w_etbr_h(v) do { ioc3->etbr_h = cpu_to_be32(v); } while (0)
2119 -#define ioc3_r_etbr_l() be32_to_cpu(ioc3->etbr_l)
2120 -#define ioc3_w_etbr_l(v) do { ioc3->etbr_l = cpu_to_be32(v); } while (0)
2121 -#define ioc3_r_etcir() be32_to_cpu(ioc3->etcir)
2122 -#define ioc3_w_etcir(v) do { ioc3->etcir = cpu_to_be32(v); } while (0)
2123 -#define ioc3_r_etpir() be32_to_cpu(ioc3->etpir)
2124 -#define ioc3_w_etpir(v) do { ioc3->etpir = cpu_to_be32(v); } while (0)
2125 -#define ioc3_r_emar_h() be32_to_cpu(ioc3->emar_h)
2126 -#define ioc3_w_emar_h(v) do { ioc3->emar_h = cpu_to_be32(v); } while (0)
2127 -#define ioc3_r_emar_l() be32_to_cpu(ioc3->emar_l)
2128 -#define ioc3_w_emar_l(v) do { ioc3->emar_l = cpu_to_be32(v); } while (0)
2129 -#define ioc3_r_ehar_h() be32_to_cpu(ioc3->ehar_h)
2130 -#define ioc3_w_ehar_h(v) do { ioc3->ehar_h = cpu_to_be32(v); } while (0)
2131 -#define ioc3_r_ehar_l() be32_to_cpu(ioc3->ehar_l)
2132 -#define ioc3_w_ehar_l(v) do { ioc3->ehar_l = cpu_to_be32(v); } while (0)
2133 -#define ioc3_r_micr() be32_to_cpu(ioc3->micr)
2134 -#define ioc3_w_micr(v) do { ioc3->micr = cpu_to_be32(v); } while (0)
2135 -#define ioc3_r_midr_r() be32_to_cpu(ioc3->midr_r)
2136 -#define ioc3_w_midr_r(v) do { ioc3->midr_r = cpu_to_be32(v); } while (0)
2137 -#define ioc3_r_midr_w() be32_to_cpu(ioc3->midr_w)
2138 -#define ioc3_w_midr_w(v) do { ioc3->midr_w = cpu_to_be32(v); } while (0)
2139 -
2140 -static inline u32
2141 -mcr_pack(u32 pulse, u32 sample)
2142 -{
2143 - return (pulse << 10) | (sample << 2);
2144 -}
2145 -
2146 -static int
2147 -nic_wait(struct ioc3 *ioc3)
2148 -{
2149 - u32 mcr;
2150 -
2151 - do {
2152 - mcr = ioc3_r_mcr();
2153 - } while (!(mcr & 2));
2154 -
2155 - return mcr & 1;
2156 -}
2157 -
2158 -static int
2159 -nic_reset(struct ioc3 *ioc3)
2160 -{
2161 - int presence;
2162 -
2163 - ioc3_w_mcr(mcr_pack(500, 65));
2164 - presence = nic_wait(ioc3);
2165 -
2166 - ioc3_w_mcr(mcr_pack(0, 500));
2167 - nic_wait(ioc3);
2168 -
2169 - return presence;
2170 -}
2171 -
2172 -static inline
2173 -int nic_read_bit(struct ioc3 *ioc3)
2174 -{
2175 - int result;
2176 -
2177 - ioc3_w_mcr(mcr_pack(6, 13));
2178 - result = nic_wait(ioc3);
2179 - ioc3_w_mcr(mcr_pack(0, 100));
2180 - nic_wait(ioc3);
2181 -
2182 - return result;
2183 -}
2184 -
2185 -static inline void
2186 -nic_write_bit(struct ioc3 *ioc3, int bit)
2187 -{
2188 - if (bit)
2189 - ioc3_w_mcr(mcr_pack(6, 110));
2190 - else
2191 - ioc3_w_mcr(mcr_pack(80, 30));
2192 -
2193 - nic_wait(ioc3);
2194 -}
2195 -
2196 -/*
2197 - * Read a byte from an iButton device
2198 - */
2199 -static u32
2200 -nic_read_byte(struct ioc3 *ioc3)
2201 +static void
2202 +ioc3_get_eaddr(struct ioc3_driver_data *idd, struct net_device *dev)
2203 {
2204 - u32 result = 0;
2205 int i;
2207 - for (i = 0; i < 8; i++)
2208 - result = (result >> 1) | (nic_read_bit(ioc3) << 7);
2209 + for (i = 0; i < 6; i++)
2210 + dev->dev_addr[i] = idd->nic_mac[i];
2212 - return result;
2213 + printk(KERN_INFO "ioc3-eth: Ethernet address is %pM.\n", dev->dev_addr);
2214 }
2216 -/*
2217 - * Write a byte to an iButton device
2218 - */
2219 static void
2220 -nic_write_byte(struct ioc3 *ioc3, int byte)
2221 -{
2222 - int i, bit;
2223 -
2224 - for (i = 8; i; i--) {
2225 - bit = byte & 1;
2226 - byte >>= 1;
2227 -
2228 - nic_write_bit(ioc3, bit);
2229 - }
2230 -}
2231 -
2232 -static u64
2233 -nic_find(struct ioc3 *ioc3, int *last)
2234 +__ioc3_set_mac_address(struct net_device *dev, struct ioc3 *vma)
2235 {
2236 - int a, b, index, disc;
2237 - u64 address = 0;
2238 -
2239 - nic_reset(ioc3);
2240 - /* Search ROM. */
2241 - nic_write_byte(ioc3, 0xf0);
2242 -
2243 - /* Algorithm from ``Book of iButton Standards''. */
2244 - for (index = 0, disc = 0; index < 64; index++) {
2245 - a = nic_read_bit(ioc3);
2246 - b = nic_read_bit(ioc3);
2247 -
2248 - if (a && b) {
2249 - printk("NIC search failed (not fatal).\n");
2250 - *last = 0;
2251 - return 0;
2252 - }
2253 -
2254 - if (!a && !b) {
2255 - if (index == *last) {
2256 - address |= 1UL << index;
2257 - } else if (index > *last) {
2258 - address &= ~(1UL << index);
2259 - disc = index;
2260 - } else if ((address & (1UL << index)) == 0)
2261 - disc = index;
2262 - nic_write_bit(ioc3, address & (1UL << index));
2263 - continue;
2264 - } else {
2265 - if (a)
2266 - address |= 1UL << index;
2267 - else
2268 - address &= ~(1UL << index);
2269 - nic_write_bit(ioc3, a);
2270 - continue;
2271 - }
2272 - }
2273 -
2274 - *last = disc;
2275 -
2276 - return address;
2277 -}
2278 -
2279 -static int
2280 -nic_init(struct ioc3 *ioc3)
2281 -{
2282 - const char *unknown = "unknown";
2283 - const char *type = unknown;
2284 - u8 crc;
2285 - u8 serial[6];
2286 - int save = 0, i;
2287 -
2288 - while (1) {
2289 - u64 reg;
2290 - reg = nic_find(ioc3, &save);
2291 -
2292 - switch (reg & 0xff) {
2293 - case 0x91:
2294 - type = "DS1981U";
2295 - break;
2296 - default:
2297 - if (save == 0) {
2298 - /* Let the caller try again. */
2299 - return -1;
2300 - }
2301 - continue;
2302 - }
2303 -
2304 - nic_reset(ioc3);
2305 -
2306 - /* Match ROM. */
2307 - nic_write_byte(ioc3, 0x55);
2308 - for (i = 0; i < 8; i++)
2309 - nic_write_byte(ioc3, (reg >> (i << 3)) & 0xff);
2310 -
2311 - reg >>= 8; /* Shift out type. */
2312 - for (i = 0; i < 6; i++) {
2313 - serial[i] = reg & 0xff;
2314 - reg >>= 8;
2315 - }
2316 - crc = reg & 0xff;
2317 - break;
2318 - }
2319 -
2320 - printk("Found %s NIC", type);
2321 - if (type != unknown)
2322 - printk (" registration number %pM, CRC %02x", serial, crc);
2323 - printk(".\n");
2324 -
2325 - return 0;
2326 + writel((dev->dev_addr[5] << 8) |
2327 + dev->dev_addr[4],
2328 + &vma->emar_h);
2329 + writel((dev->dev_addr[3] << 24) |
2330 + (dev->dev_addr[2] << 16) |
2331 + (dev->dev_addr[1] << 8) |
2332 + dev->dev_addr[0],
2333 + &vma->emar_l);
2334 }
2336 /*
2337 - * Read the NIC (Number-In-a-Can) device used to store the MAC address on
2338 - * SN0 / SN00 nodeboards and PCI cards.
2339 + * Caller must hold the ioc3_lock ever for MII readers. This is also
2340 + * used to protect the transmitter side but it's low contention.
2341 */
2342 -static void
2343 -ioc3_get_eaddr_nic(struct ioc3_private *ip)
2344 +static int
2345 +ioc3_mdio_read(struct net_device *dev, int phy, int reg)
2346 {
2347 - struct ioc3 *ioc3 = ip->regs;
2348 - u8 nic[14];
2349 - int tries = 2; /* There may be some problem with the battery? */
2350 - int i;
2351 -
2352 - ioc3_w_gpcr_s(1 << 21);
2353 -
2354 - while (tries--) {
2355 - if (!nic_init(ioc3))
2356 - break;
2357 - udelay(500);
2358 - }
2359 -
2360 - if (tries < 0) {
2361 - printk("Failed to read MAC address\n");
2362 - return;
2363 - }
2364 -
2365 - /* Read Memory. */
2366 - nic_write_byte(ioc3, 0xf0);
2367 - nic_write_byte(ioc3, 0x00);
2368 - nic_write_byte(ioc3, 0x00);
2369 + struct ioc3_private *ip = netdev_priv(dev);
2370 + struct ioc3 *vma = ip->idd->vma;
2372 - for (i = 13; i >= 0; i--)
2373 - nic[i] = nic_read_byte(ioc3);
2374 + while (readl(&vma->micr) & MICR_BUSY)
2375 + ;
2376 + writel((phy << MICR_PHYADDR_SHIFT) | reg | MICR_READTRIG,
2377 + &vma->micr);
2378 + while (readl(&vma->micr) & MICR_BUSY)
2379 + ;
2381 - for (i = 2; i < 8; i++)
2382 - ip->dev->dev_addr[i - 2] = nic[i];
2383 + return readl(&vma->midr_r) & MIDR_DATA_MASK;
2384 }
2386 -/*
2387 - * Ok, this is hosed by design. It's necessary to know what machine the
2388 - * NIC is in in order to know how to read the NIC address. We also have
2389 - * to know if it's a PCI card or a NIC in on the node board ...
2390 - */
2391 static void
2392 -ioc3_get_eaddr(struct ioc3_private *ip)
2393 -{
2394 - ioc3_get_eaddr_nic(ip);
2395 -
2396 - printk("Ethernet address is %pM.\n", ip->dev->dev_addr);
2397 -}
2398 -
2399 -static void
2400 -__ioc3_set_mac_address(struct net_device *dev)
2401 +ioc3_mdio_write(struct net_device *dev, int phy, int reg, int data)
2402 {
2403 struct ioc3_private *ip = netdev_priv(dev);
2404 - struct ioc3 *ioc3 = ip->regs;
2405 -
2406 - ioc3_w_emar_h((dev->dev_addr[5] << 8) | dev->dev_addr[4]);
2407 - ioc3_w_emar_l((dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) |
2408 - (dev->dev_addr[1] << 8) | dev->dev_addr[0]);
2409 + struct ioc3 *vma = ip->idd->vma;
2410 +
2411 + while (readl(&vma->micr) & MICR_BUSY)
2412 + ;
2413 + writel(data, &vma->midr_w);
2414 + writel((phy << MICR_PHYADDR_SHIFT) | reg, &vma->micr);
2415 + while (readl(&vma->micr) & MICR_BUSY)
2416 + ;
2417 }
2419 -static int
2420 -ioc3_set_mac_address(struct net_device *dev, void *addr)
2421 +static void ioc3_stop(struct ioc3_private *ip)
2422 {
2423 - struct ioc3_private *ip = netdev_priv(dev);
2424 - struct sockaddr *sa = addr;
2425 -
2426 - memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
2427 + struct ioc3 *vma = ip->idd->vma;
2429 - spin_lock_irq(&ip->ioc3_lock);
2430 - __ioc3_set_mac_address(dev);
2431 - spin_unlock_irq(&ip->ioc3_lock);
2432 -
2433 - return 0;
2434 + writel(0, &vma->emcr); /* Shutup */
2435 + writel(0, &vma->eier); /* Disable interrupts */
2436 + (void)readl(&vma->eier); /* Flush */
2437 }
2439 /*
2440 - * Caller must hold the ioc3_lock ever for MII readers. This is also
2441 - * used to protect the transmitter side but it's low contention.
2442 + * Given a multicast ethernet address, this routine calculates the
2443 + * address's bit index in the logical address filter mask
2444 */
2445 -static int
2446 -ioc3_mdio_read(struct net_device *dev, int phy, int reg)
2447 +static u32
2448 +ioc3_hash(const u8 *addr)
2449 {
2450 - struct ioc3_private *ip = netdev_priv(dev);
2451 - struct ioc3 *ioc3 = ip->regs;
2452 + u32 crc, temp = 0;
2453 + int bits;
2454 +
2455 + crc = ether_crc_le(ETH_ALEN, addr);
2457 - while (ioc3_r_micr() & MICR_BUSY);
2458 - ioc3_w_micr((phy << MICR_PHYADDR_SHIFT) | reg | MICR_READTRIG);
2459 - while (ioc3_r_micr() & MICR_BUSY);
2460 + crc &= 0x3f; /* bit reverse lowest 6 bits for hash index */
2461 + for (bits = 6; --bits >= 0; ) {
2462 + temp <<= 1;
2463 + temp |= (crc & 0x1);
2464 + crc >>= 1;
2465 + }
2467 - return ioc3_r_midr_r() & MIDR_DATA_MASK;
2468 + return temp;
2469 }
2471 static void
2472 -ioc3_mdio_write(struct net_device *dev, int phy, int reg, int data)
2473 +ioc3_set_multicast_list(struct net_device *dev)
2474 {
2475 + struct netdev_hw_addr *ha;
2476 struct ioc3_private *ip = netdev_priv(dev);
2477 - struct ioc3 *ioc3 = ip->regs;
2478 -
2479 - while (ioc3_r_micr() & MICR_BUSY);
2480 - ioc3_w_midr_w(data);
2481 - ioc3_w_micr((phy << MICR_PHYADDR_SHIFT) | reg);
2482 - while (ioc3_r_micr() & MICR_BUSY);
2483 -}
2484 + struct ioc3 *vma = ip->idd->vma;
2485 + u64 ehar = 0;
2487 -static int
2488 -ioc3_mii_init(struct ioc3_private *ip);
2489 + spin_lock_irq(&ip->ioc3_lock);
2490 + if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
2491 + ip->emcr |= EMCR_PROMISC;
2492 + writel(ip->emcr, &vma->emcr);
2493 + (void)readl(&vma->emcr);
2494 + } else {
2495 + ip->emcr &= ~EMCR_PROMISC;
2496 + writel(ip->emcr, &vma->emcr); /* Clear promiscuous. */
2497 + (void)readl(&vma->emcr);
2499 -static struct net_device_stats *
2500 -ioc3_get_stats(struct net_device *dev)
2501 -{
2502 - struct ioc3_private *ip = netdev_priv(dev);
2503 - struct ioc3 *ioc3 = ip->regs;
2504 + if ((dev->flags & IFF_ALLMULTI) ||
2505 + (netdev_mc_count(dev) > 64)) {
2506 + /* Too many for hashing to make sense or we want all
2507 + * multicast packets anyway, so skip computing all
2508 + * the hashes and just accept all packets.
2509 + */
2510 + ip->ehar_h = 0xffffffff;
2511 + ip->ehar_l = 0xffffffff;
2512 + } else {
2513 + netdev_for_each_mc_addr(ha, dev) {
2514 + ehar |= (1UL << ioc3_hash(ha->addr));
2515 + }
2516 + ip->ehar_h = ehar >> 32;
2517 + ip->ehar_l = ehar & 0xffffffff;
2518 + }
2519 + writel(ip->ehar_h, &vma->ehar_h);
2520 + writel(ip->ehar_l, &vma->ehar_l);
2521 + }
2523 - dev->stats.collisions += (ioc3_r_etcdc() & ETCDC_COLLCNT_MASK);
2524 - return &dev->stats;
2525 + spin_unlock_irq(&ip->ioc3_lock);
2526 }
2528 static void
2529 ioc3_tcpudp_checksum(struct sk_buff *skb, u32 hwsum, int len)
2530 {
2531 struct ethhdr *eh = eth_hdr(skb);
2532 - u32 csum, ehsum, proto;
2533 struct iphdr *ih;
2534 - u16 *ew;
2535 u8 *cp;
2536 + u16 *ew;
2537 + u32 csum, ehsum, proto;
2539 /*
2540 * Did hardware handle the checksum at all? The cases we can handle
2541 @@ -587,209 +328,23 @@ ioc3_tcpudp_checksum(struct sk_buff *skb, u32 hwsum, int len)
2542 skb->ip_summed = CHECKSUM_UNNECESSARY;
2543 }
2545 -static inline void
2546 -ioc3_rx(struct net_device *dev)
2547 -{
2548 - struct ioc3_private *ip = netdev_priv(dev);
2549 - struct sk_buff *skb, *new_skb;
2550 - struct ioc3 *ioc3 = ip->regs;
2551 - int rx_entry, n_entry, len;
2552 - struct ioc3_erxbuf *rxb;
2553 - unsigned long *rxr;
2554 - u32 w0, err;
2555 -
2556 - rxr = ip->rxr; /* Ring base */
2557 - rx_entry = ip->rx_ci; /* RX consume index */
2558 - n_entry = ip->rx_pi;
2559 -
2560 - skb = ip->rx_skbs[rx_entry];
2561 - rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
2562 - w0 = be32_to_cpu(rxb->w0);
2563 -
2564 - while (w0 & ERXBUF_V) {
2565 - err = be32_to_cpu(rxb->err); /* It's valid */
2566 - if (err & ERXBUF_GOODPKT) {
2567 - len = ((w0 >> ERXBUF_BYTECNT_SHIFT) & 0x7ff) - 4;
2568 - skb_trim(skb, len);
2569 - skb->protocol = eth_type_trans(skb, dev);
2570 -
2571 - new_skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
2572 - if (!new_skb) {
2573 - /* Ouch, drop packet and just recycle packet
2574 - * to keep the ring filled.
2575 - */
2576 - dev->stats.rx_dropped++;
2577 - new_skb = skb;
2578 - goto next;
2579 - }
2580 -
2581 - if (likely(dev->features & NETIF_F_RXCSUM))
2582 - ioc3_tcpudp_checksum(skb,
2583 - w0 & ERXBUF_IPCKSUM_MASK, len);
2584 -
2585 - netif_rx(skb);
2586 -
2587 - ip->rx_skbs[rx_entry] = NULL; /* Poison */
2588 -
2589 - /* Because we reserve afterwards. */
2590 - skb_put(new_skb, (1664 + RX_OFFSET));
2591 - rxb = (struct ioc3_erxbuf *)new_skb->data;
2592 - skb_reserve(new_skb, RX_OFFSET);
2593 -
2594 - dev->stats.rx_packets++; /* Statistics */
2595 - dev->stats.rx_bytes += len;
2596 - } else {
2597 - /* The frame is invalid and the skb never reached the
2598 - * network layer so we can just recycle it.
2599 - */
2600 - new_skb = skb;
2601 - dev->stats.rx_errors++;
2602 - }
2603 -
2604 - /* Statistics */
2605 - if (err & ERXBUF_CRCERR)
2606 - dev->stats.rx_crc_errors++;
2607 - if (err & ERXBUF_FRAMERR)
2608 - dev->stats.rx_frame_errors++;
2609 -next:
2610 - ip->rx_skbs[n_entry] = new_skb;
2611 - rxr[n_entry] = cpu_to_be64(ioc3_map(rxb, 1));
2612 - rxb->w0 = 0; /* Clear valid flag */
2613 - n_entry = (n_entry + 1) & 0x1ff; /* Update erpir */
2614 -
2615 - /* Now go on to the next ring entry. */
2616 - rx_entry = (rx_entry + 1) & 0x1ff;
2617 - skb = ip->rx_skbs[rx_entry];
2618 - rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
2619 - w0 = be32_to_cpu(rxb->w0);
2620 - }
2621 - ioc3_w_erpir((n_entry << 3) | ERPIR_ARM);
2622 - ip->rx_pi = n_entry;
2623 - ip->rx_ci = rx_entry;
2624 -}
2625 -
2626 -static inline void
2627 -ioc3_tx(struct net_device *dev)
2628 -{
2629 - struct ioc3_private *ip = netdev_priv(dev);
2630 - unsigned long packets, bytes;
2631 - struct ioc3 *ioc3 = ip->regs;
2632 - int tx_entry, o_entry;
2633 - struct sk_buff *skb;
2634 - u32 etcir;
2635 -
2636 - spin_lock(&ip->ioc3_lock);
2637 - etcir = ioc3_r_etcir();
2638 -
2639 - tx_entry = (etcir >> 7) & 0x7f;
2640 - o_entry = ip->tx_ci;
2641 - packets = 0;
2642 - bytes = 0;
2643 -
2644 - while (o_entry != tx_entry) {
2645 - packets++;
2646 - skb = ip->tx_skbs[o_entry];
2647 - bytes += skb->len;
2648 - dev_kfree_skb_irq(skb);
2649 - ip->tx_skbs[o_entry] = NULL;
2650 -
2651 - o_entry = (o_entry + 1) & 0x7f; /* Next */
2652 -
2653 - etcir = ioc3_r_etcir(); /* More pkts sent? */
2654 - tx_entry = (etcir >> 7) & 0x7f;
2655 - }
2656 -
2657 - dev->stats.tx_packets += packets;
2658 - dev->stats.tx_bytes += bytes;
2659 - ip->txqlen -= packets;
2660 -
2661 - if (ip->txqlen < 128)
2662 - netif_wake_queue(dev);
2663 -
2664 - ip->tx_ci = o_entry;
2665 - spin_unlock(&ip->ioc3_lock);
2666 -}
2667 +#define ETCSR_FD ((17 << ETCSR_IPGR2_SHIFT) | (11 << ETCSR_IPGR1_SHIFT) | 21)
2668 +#define ETCSR_HD ((21 << ETCSR_IPGR2_SHIFT) | (21 << ETCSR_IPGR1_SHIFT) | 21)
2670 -/*
2671 - * Deal with fatal IOC3 errors. This condition might be caused by a hard or
2672 - * software problems, so we should try to recover
2673 - * more gracefully if this ever happens. In theory we might be flooded
2674 - * with such error interrupts if something really goes wrong, so we might
2675 - * also consider to take the interface down.
2676 - */
2677 static void
2678 -ioc3_error(struct net_device *dev, u32 eisr)
2679 -{
2680 - struct ioc3_private *ip = netdev_priv(dev);
2681 - u8 *iface = dev->name;
2682 -
2683 - spin_lock(&ip->ioc3_lock);
2684 -
2685 - if (eisr & EISR_RXOFLO)
2686 - printk(KERN_ERR "%s: RX overflow.\n", iface);
2687 - if (eisr & EISR_RXBUFOFLO)
2688 - printk(KERN_ERR "%s: RX buffer overflow.\n", iface);
2689 - if (eisr & EISR_RXMEMERR)
2690 - printk(KERN_ERR "%s: RX PCI error.\n", iface);
2691 - if (eisr & EISR_RXPARERR)
2692 - printk(KERN_ERR "%s: RX SSRAM parity error.\n", iface);
2693 - if (eisr & EISR_TXBUFUFLO)
2694 - printk(KERN_ERR "%s: TX buffer underflow.\n", iface);
2695 - if (eisr & EISR_TXMEMERR)
2696 - printk(KERN_ERR "%s: TX PCI error.\n", iface);
2697 -
2698 - ioc3_stop(ip);
2699 - ioc3_init(dev);
2700 - ioc3_mii_init(ip);
2701 -
2702 - netif_wake_queue(dev);
2703 -
2704 - spin_unlock(&ip->ioc3_lock);
2705 -}
2706 -
2707 -/* The interrupt handler does all of the Rx thread work and cleans up after
2708 - * the Tx thread.
2709 - */
2710 -static irqreturn_t
2711 -ioc3_interrupt(int irq, void *_dev)
2712 -{
2713 - struct net_device *dev = (struct net_device *)_dev;
2714 - struct ioc3_private *ip = netdev_priv(dev);
2715 - struct ioc3 *ioc3 = ip->regs;
2716 - const u32 enabled = EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO |
2717 - EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO |
2718 - EISR_TXEXPLICIT | EISR_TXMEMERR;
2719 - u32 eisr;
2720 -
2721 - eisr = ioc3_r_eisr() & enabled;
2722 -
2723 - ioc3_w_eisr(eisr);
2724 - (void)ioc3_r_eisr(); /* Flush */
2725 -
2726 - if (eisr & (EISR_RXOFLO | EISR_RXBUFOFLO | EISR_RXMEMERR |
2727 - EISR_RXPARERR | EISR_TXBUFUFLO | EISR_TXMEMERR))
2728 - ioc3_error(dev, eisr);
2729 - if (eisr & EISR_RXTIMERINT)
2730 - ioc3_rx(dev);
2731 - if (eisr & EISR_TXEXPLICIT)
2732 - ioc3_tx(dev);
2733 -
2734 - return IRQ_HANDLED;
2735 -}
2736 -
2737 -static inline void
2738 ioc3_setup_duplex(struct ioc3_private *ip)
2739 {
2740 - struct ioc3 *ioc3 = ip->regs;
2741 + struct ioc3 *vma = ip->idd->vma;
2743 if (ip->mii.full_duplex) {
2744 - ioc3_w_etcsr(ETCSR_FD);
2745 + writel(ETCSR_FD, &vma->etcsr);
2746 ip->emcr |= EMCR_DUPLEX;
2747 } else {
2748 - ioc3_w_etcsr(ETCSR_HD);
2749 + writel(ETCSR_HD, &vma->etcsr);
2750 ip->emcr &= ~EMCR_DUPLEX;
2751 }
2752 - ioc3_w_emcr(ip->emcr);
2753 + writel(ip->emcr, &vma->emcr);
2754 + (void)readl(&vma->emcr);
2755 }
2757 static void
2758 @@ -798,15 +353,14 @@ ioc3_timer(struct timer_list *t)
2759 struct ioc3_private *ip = from_timer(ip, t, ioc3_timer);
2761 /* Print the link status if it has changed */
2762 - mii_check_media(&ip->mii, 1, 0);
2763 - ioc3_setup_duplex(ip);
2764 + if (mii_check_media(&ip->mii, 1, 0))
2765 + ioc3_setup_duplex(ip);
2767 - ip->ioc3_timer.expires = jiffies + ((12 * HZ) / 10); /* 1.2s */
2768 + ip->ioc3_timer.expires = jiffies + (2 * HZ); /* 2s */
2769 add_timer(&ip->ioc3_timer);
2770 }
2772 -/*
2773 - * Try to find a PHY. There is no apparent relation between the MII addresses
2774 +/* Try to find a PHY. There is no apparent relation between the MII addresses
2775 * in the SGI documentation and what we find in reality, so we simply probe
2776 * for the PHY. It seems IOC3 PHYs usually live on address 31. One of my
2777 * onboard IOC3s has the special oddity that probing doesn't seem to find it
2778 @@ -830,9 +384,9 @@ ioc3_mii_init(struct ioc3_private *ip)
2779 }
2781 if (!found) {
2782 - if (ioc3_phy_workaround)
2783 + if (ioc3_phy_workaround) {
2784 i = 31;
2785 - else {
2786 + } else {
2787 ip->mii.phy_id = -1;
2788 res = -ENODEV;
2789 goto out;
2790 @@ -848,38 +402,35 @@ ioc3_mii_init(struct ioc3_private *ip)
2791 static void
2792 ioc3_mii_start(struct ioc3_private *ip)
2793 {
2794 - ip->ioc3_timer.expires = jiffies + (12 * HZ) / 10; /* 1.2 sec. */
2795 + ip->ioc3_timer.expires = jiffies + (2 * HZ); /* 2 sec. */
2796 add_timer(&ip->ioc3_timer);
2797 }
2799 -static inline void
2800 +static void
2801 ioc3_clean_rx_ring(struct ioc3_private *ip)
2802 {
2803 struct sk_buff *skb;
2804 + struct ioc3_erxbuf *rxb;
2805 int i;
2807 - for (i = ip->rx_ci; i & 15; i++) {
2808 - ip->rx_skbs[ip->rx_pi] = ip->rx_skbs[ip->rx_ci];
2809 - ip->rxr[ip->rx_pi++] = ip->rxr[ip->rx_ci++];
2810 - }
2811 - ip->rx_pi &= 0x1ff;
2812 - ip->rx_ci &= 0x1ff;
2813 -
2814 - for (i = ip->rx_ci; i != ip->rx_pi; i = (i + 1) & 0x1ff) {
2815 - struct ioc3_erxbuf *rxb;
2816 + for (i = 0; i < RX_BUFFS; i++) {
2817 skb = ip->rx_skbs[i];
2818 - rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
2819 - rxb->w0 = 0;
2820 + if (skb) {
2821 + rxb = (struct ioc3_erxbuf *)(skb->data - RX_OFFSET);
2822 + rxb->w0 = 0;
2823 + }
2824 }
2825 + ip->rx_ci = 0;
2826 + ip->rx_pi = RX_BUFFS - 16;
2827 }
2829 -static inline void
2830 +static void
2831 ioc3_clean_tx_ring(struct ioc3_private *ip)
2832 {
2833 struct sk_buff *skb;
2834 int i;
2836 - for (i=0; i < 128; i++) {
2837 + for (i = 0; i < TX_BUFFS; i++) {
2838 skb = ip->tx_skbs[i];
2839 if (skb) {
2840 ip->tx_skbs[i] = NULL;
2841 @@ -895,7 +446,7 @@ static void
2842 ioc3_free_rings(struct ioc3_private *ip)
2843 {
2844 struct sk_buff *skb;
2845 - int rx_entry, n_entry;
2846 + int i;
2848 if (ip->txr) {
2849 ioc3_clean_tx_ring(ip);
2850 @@ -904,15 +455,10 @@ ioc3_free_rings(struct ioc3_private *ip)
2851 }
2853 if (ip->rxr) {
2854 - n_entry = ip->rx_ci;
2855 - rx_entry = ip->rx_pi;
2856 -
2857 - while (n_entry != rx_entry) {
2858 - skb = ip->rx_skbs[n_entry];
2859 + for (i = 0; i < RX_BUFFS; i++) {
2860 + skb = ip->rx_skbs[i];
2861 if (skb)
2862 dev_kfree_skb_any(skb);
2863 -
2864 - n_entry = (n_entry + 1) & 0x1ff;
2865 }
2866 free_page((unsigned long)ip->rxr);
2867 ip->rxr = NULL;
2868 @@ -932,16 +478,16 @@ ioc3_alloc_rings(struct net_device *dev)
2869 ip->rxr = (unsigned long *) get_zeroed_page(GFP_ATOMIC);
2870 rxr = ip->rxr;
2871 if (!rxr)
2872 - printk("ioc3_alloc_rings(): get_zeroed_page() failed!\n");
2873 + printk(KERN_ERR "ioc3_alloc_rings(): get_zeroed_page() failed!\n");
2875 - /* Now the rx buffers. The RX ring may be larger but we only
2876 - * allocate 16 buffers for now. Need to tune this for
2877 - * performance and memory later.
2878 + /* Now the rx buffers. The RX ring may be larger but we
2879 + * only allocate RX_BUFFS buffers for now. Need to tune
2880 + * this for performance and memory later.
2881 */
2882 for (i = 0; i < RX_BUFFS; i++) {
2883 struct sk_buff *skb;
2885 - skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
2886 + skb = ioc3_alloc_skb(dev);
2887 if (!skb) {
2888 show_free_areas(0, NULL);
2889 continue;
2890 @@ -950,22 +496,19 @@ ioc3_alloc_rings(struct net_device *dev)
2891 ip->rx_skbs[i] = skb;
2893 /* Because we reserve afterwards. */
2894 - skb_put(skb, (1664 + RX_OFFSET));
2895 + skb_put(skb, (RX_BUF_SIZE + RX_OFFSET));
2896 rxb = (struct ioc3_erxbuf *) skb->data;
2897 - rxr[i] = cpu_to_be64(ioc3_map(rxb, 1));
2898 + rxr[i] = cpu_to_be64(ioc3_map(rxb, PCI64_ATTR_BAR));
2899 skb_reserve(skb, RX_OFFSET);
2900 }
2901 - ip->rx_ci = 0;
2902 - ip->rx_pi = RX_BUFFS;
2903 }
2905 if (ip->txr == NULL) {
2906 /* Allocate and initialize tx rings. 16kb = 128 bufs. */
2907 - ip->txr = (struct ioc3_etxd *)__get_free_pages(GFP_KERNEL, 2);
2908 + ip->txr = (struct ioc3_etxd *)__get_free_pages((GFP_ATOMIC |
2909 + __GFP_ZERO), 2);
2910 if (!ip->txr)
2911 - printk("ioc3_alloc_rings(): __get_free_pages() failed!\n");
2912 - ip->tx_pi = 0;
2913 - ip->tx_ci = 0;
2914 + printk(KERN_ERR "ioc3_alloc_rings(): __get_free_pages() failed!\n");
2915 }
2916 }
2918 @@ -973,104 +516,105 @@ static void
2919 ioc3_init_rings(struct net_device *dev)
2920 {
2921 struct ioc3_private *ip = netdev_priv(dev);
2922 - struct ioc3 *ioc3 = ip->regs;
2923 + struct ioc3 *vma = ip->idd->vma;
2924 unsigned long ring;
2926 ioc3_free_rings(ip);
2927 ioc3_alloc_rings(dev);
2928 -
2929 ioc3_clean_rx_ring(ip);
2930 ioc3_clean_tx_ring(ip);
2932 /* Now the rx ring base, consume & produce registers. */
2933 - ring = ioc3_map(ip->rxr, 0);
2934 - ioc3_w_erbr_h(ring >> 32);
2935 - ioc3_w_erbr_l(ring & 0xffffffff);
2936 - ioc3_w_ercir(ip->rx_ci << 3);
2937 - ioc3_w_erpir((ip->rx_pi << 3) | ERPIR_ARM);
2938 -
2939 - ring = ioc3_map(ip->txr, 0);
2940 -
2941 - ip->txqlen = 0; /* nothing queued */
2942 + ring = ioc3_map(ip->rxr, PCI64_ATTR_VIRTUAL | PCI64_ATTR_PREC);
2943 + writel(ring >> 32, &vma->erbr_h);
2944 + writel(ring & 0xffffffff, &vma->erbr_l);
2945 + writel(ip->rx_ci << 3, &vma->ercir);
2946 + writel((ip->rx_pi << 3) | ERPIR_ARM, &vma->erpir);
2948 /* Now the tx ring base, consume & produce registers. */
2949 - ioc3_w_etbr_h(ring >> 32);
2950 - ioc3_w_etbr_l(ring & 0xffffffff);
2951 - ioc3_w_etpir(ip->tx_pi << 7);
2952 - ioc3_w_etcir(ip->tx_ci << 7);
2953 - (void)ioc3_r_etcir(); /* Flush */
2954 + ring = ioc3_map(ip->txr, PCI64_ATTR_VIRTUAL | PCI64_ATTR_PREC);
2955 + ip->txbfree = TX_BUFFS; /* nothing queued */
2956 + writel(ring >> 32, &vma->etbr_h);
2957 + writel(ring & 0xffffffff, &vma->etbr_l);
2958 + writel(ip->tx_pi << 7, &vma->etpir);
2959 + writel(ip->tx_ci << 7, &vma->etcir);
2960 + (void)readl(&vma->etcir); /* Flush */
2961 }
2963 -static inline void
2964 +static void
2965 ioc3_ssram_disc(struct ioc3_private *ip)
2966 {
2967 - struct ioc3 *ioc3 = ip->regs;
2968 - volatile u32 *ssram0 = &ioc3->ssram[0x0000];
2969 - volatile u32 *ssram1 = &ioc3->ssram[0x4000];
2970 - u32 pattern = 0x5555;
2971 + struct ioc3 *vma = ip->idd->vma;
2972 + u32 *emcr_p = &vma->emcr;
2973 + u32 *ssram0 = &vma->ssram[0x0000];
2974 + u32 *ssram1 = &vma->ssram[0x4000];
2975 + const u32 pattern0 = 0x5555;
2976 + const u32 pattern1 = ~pattern0 & IOC3_SSRAM_DM;
2978 /* Assume the larger size SSRAM and enable parity checking */
2979 - ioc3_w_emcr(ioc3_r_emcr() | (EMCR_BUFSIZ | EMCR_RAMPAR));
2980 + writel(readl(emcr_p) | EMCR_BUFSIZ | EMCR_RAMPAR, emcr_p);
2981 + (void)readl(emcr_p);
2983 - *ssram0 = pattern;
2984 - *ssram1 = ~pattern & IOC3_SSRAM_DM;
2985 + writel(pattern0, ssram0);
2986 + writel(pattern1, ssram1);
2988 - if ((*ssram0 & IOC3_SSRAM_DM) != pattern ||
2989 - (*ssram1 & IOC3_SSRAM_DM) != (~pattern & IOC3_SSRAM_DM)) {
2990 + if (((readl(ssram0) & IOC3_SSRAM_DM) != pattern0) ||
2991 + ((readl(ssram1) & IOC3_SSRAM_DM) != pattern1)) {
2992 /* set ssram size to 64 KB */
2993 - ip->emcr = EMCR_RAMPAR;
2994 - ioc3_w_emcr(ioc3_r_emcr() & ~EMCR_BUFSIZ);
2995 - } else
2996 - ip->emcr = EMCR_BUFSIZ | EMCR_RAMPAR;
2997 + ip->emcr |= EMCR_RAMPAR;
2998 + writel(readl(emcr_p) & ~EMCR_BUFSIZ, emcr_p);
2999 + (void)readl(emcr_p);
3000 + } else {
3001 + ip->emcr |= EMCR_RAMPAR | EMCR_BUFSIZ;
3002 + }
3003 }
3005 static void
3006 ioc3_init(struct net_device *dev)
3007 {
3008 struct ioc3_private *ip = netdev_priv(dev);
3009 - struct ioc3 *ioc3 = ip->regs;
3010 + struct ioc3 *vma = ip->idd->vma;
3012 del_timer_sync(&ip->ioc3_timer); /* Kill if running */
3014 - ioc3_w_emcr(EMCR_RST); /* Reset */
3015 - (void)ioc3_r_emcr(); /* Flush WB */
3016 + writel(EMCR_RST, &vma->emcr); /* Reset */
3017 + (void)readl(&vma->emcr); /* Flush WB */
3018 udelay(4); /* Give it time... */
3019 - ioc3_w_emcr(0);
3020 - (void)ioc3_r_emcr();
3021 + writel(0, &vma->emcr);
3022 + (void)readl(&vma->emcr);
3024 /* Misc registers */
3025 #ifdef CONFIG_SGI_IP27
3026 - ioc3_w_erbar(PCI64_ATTR_BAR >> 32); /* Barrier on last store */
3027 + /* Barrier on last store */
3028 + writel(readl(&vma->erbar) |
3029 + (ERBAR_BARRIER_BIT << ERBAR_RXBARR_SHIFT), &vma->erbar);
3030 #else
3031 - ioc3_w_erbar(0); /* Let PCI API get it right */
3032 + /* Let PCI API get it right */
3033 + writel(0, &vma->erbar);
3034 #endif
3035 - (void)ioc3_r_etcdc(); /* Clear on read */
3036 - ioc3_w_ercsr(15); /* RX low watermark */
3037 - ioc3_w_ertr(0); /* Interrupt immediately */
3038 - __ioc3_set_mac_address(dev);
3039 - ioc3_w_ehar_h(ip->ehar_h);
3040 - ioc3_w_ehar_l(ip->ehar_l);
3041 - ioc3_w_ersr(42); /* XXX should be random */
3042 + (void)readl(&vma->etcdc); /* Clear on read */
3043 + writel(15, &vma->ercsr); /* RX low watermark */
3044 + writel(1, &vma->ertr); /* Interrupt immediately */
3045 + __ioc3_set_mac_address(dev, vma);
3046 + writel(ip->ehar_h, &vma->ehar_h);
3047 + writel(ip->ehar_l, &vma->ehar_l);
3048 + writel(42, &vma->ersr); /* XXX Should be random */
3050 ioc3_init_rings(dev);
3052 - ip->emcr |= (((RX_OFFSET / 2) << EMCR_RXOFF_SHIFT) | EMCR_TXDMAEN |
3053 - EMCR_TXEN | EMCR_RXDMAEN | EMCR_RXEN | EMCR_PADEN);
3054 - ioc3_w_emcr(ip->emcr);
3055 - ioc3_w_eier(EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO |
3056 - EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO |
3057 - EISR_TXEXPLICIT | EISR_TXMEMERR);
3058 - (void) ioc3_r_eier();
3059 -}
3060 -
3061 -static inline void
3062 -ioc3_stop(struct ioc3_private *ip)
3063 -{
3064 - struct ioc3 *ioc3 = ip->regs;
3065 -
3066 - ioc3_w_emcr(0); /* Shutup */
3067 - ioc3_w_eier(0); /* Disable interrupts */
3068 - (void)ioc3_r_eier(); /* Flush */
3069 + ip->emcr |= ((RX_OFFSET / 2) << EMCR_RXOFF_SHIFT) |
3070 + EMCR_TXDMAEN | EMCR_TXEN |
3071 + EMCR_RXDMAEN | EMCR_RXEN |
3072 + EMCR_PADEN;
3073 + writel(ip->emcr, &vma->emcr);
3074 + (void)readl(&vma->emcr);
3075 + writel(EISR_RXTIMERINT | EISR_RXTHRESHINT |
3076 + EISR_RXOFLO | EISR_RXBUFOFLO |
3077 + EISR_RXMEMERR | EISR_RXPARERR |
3078 + EISR_TXEXDEF |
3079 + EISR_TXBUFUFLO |
3080 + EISR_TXMEMERR, &vma->eier);
3081 + (void)readl(&vma->eier);
3082 }
3084 static int
3085 @@ -1078,18 +622,13 @@ ioc3_open(struct net_device *dev)
3086 {
3087 struct ioc3_private *ip = netdev_priv(dev);
3089 - if (request_irq(dev->irq, ioc3_interrupt, IRQF_SHARED, ioc3_str, dev)) {
3090 - printk(KERN_ERR "%s: Can't get irq %d\n", dev->name, dev->irq);
3091 -
3092 - return -EAGAIN;
3093 - }
3094 -
3095 ip->ehar_h = 0;
3096 ip->ehar_l = 0;
3097 ioc3_init(dev);
3098 + ioc3_mii_init(ip);
3099 ioc3_mii_start(ip);
3100 -
3101 netif_start_queue(dev);
3102 +
3103 return 0;
3104 }
3106 @@ -1101,352 +640,21 @@ ioc3_close(struct net_device *dev)
3107 del_timer_sync(&ip->ioc3_timer);
3108 netif_stop_queue(dev);
3109 ioc3_stop(ip);
3110 - free_irq(dev->irq, dev);
3111 ioc3_free_rings(ip);
3113 return 0;
3114 }
3116 -/*
3117 - * MENET cards have four IOC3 chips, which are attached to two sets of
3118 - * PCI slot resources each: the primary connections are on slots
3119 - * 0..3 and the secondaries are on 4..7
3120 - *
3121 - * All four ethernets are brought out to connectors; six serial ports
3122 - * (a pair from each of the first three IOC3s) are brought out to
3123 - * MiniDINs; all other subdevices are left swinging in the wind, leave
3124 - * them disabled.
3125 - */
3126 -static int
3127 -ioc3_adjacent_is_ioc3(struct pci_dev *pdev, int slot)
3128 -{
3129 - struct pci_dev *dev = pci_get_slot(pdev->bus, PCI_DEVFN(slot, 0));
3130 - int ret = 0;
3131 -
3132 - if (dev) {
3133 - if ((dev->vendor == PCI_VENDOR_ID_SGI) &&
3134 - (dev->device == PCI_DEVICE_ID_SGI_IOC3))
3135 - ret = 1;
3136 - pci_dev_put(dev);
3137 - }
3138 -
3139 - return ret;
3140 -}
3141 -
3142 -static int
3143 -ioc3_is_menet(struct pci_dev *pdev)
3144 -{
3145 - return pdev->bus->parent == NULL &&
3146 - ioc3_adjacent_is_ioc3(pdev, 0) &&
3147 - ioc3_adjacent_is_ioc3(pdev, 1) &&
3148 - ioc3_adjacent_is_ioc3(pdev, 2);
3149 -}
3150 -
3151 -#ifdef CONFIG_SERIAL_8250
3152 -/*
3153 - * Note about serial ports and consoles:
3154 - * For console output, everyone uses the IOC3 UARTA (offset 0x178)
3155 - * connected to the master node (look in ip27_setup_console() and
3156 - * ip27prom_console_write()).
3157 - *
3158 - * For serial (/dev/ttyS0 etc), we can not have hardcoded serial port
3159 - * addresses on a partitioned machine. Since we currently use the ioc3
3160 - * serial ports, we use dynamic serial port discovery that the serial.c
3161 - * driver uses for pci/pnp ports (there is an entry for the SGI ioc3
3162 - * boards in pci_boards[]). Unfortunately, UARTA's pio address is greater
3163 - * than UARTB's, although UARTA on o200s has traditionally been known as
3164 - * port 0. So, we just use one serial port from each ioc3 (since the
3165 - * serial driver adds addresses to get to higher ports).
3166 - *
3167 - * The first one to do a register_console becomes the preferred console
3168 - * (if there is no kernel command line console= directive). /dev/console
3169 - * (ie 5, 1) is then "aliased" into the device number returned by the
3170 - * "device" routine referred to in this console structure
3171 - * (ip27prom_console_dev).
3172 - *
3173 - * Also look in ip27-pci.c:pci_fixup_ioc3() for some comments on working
3174 - * around ioc3 oddities in this respect.
3175 - *
3176 - * The IOC3 serials use a 22MHz clock rate with an additional divider which
3177 - * can be programmed in the SCR register if the DLAB bit is set.
3178 - *
3179 - * Register to interrupt zero because we share the interrupt with
3180 - * the serial driver which we don't properly support yet.
3181 - *
3182 - * Can't use UPF_IOREMAP as the whole of IOC3 resources have already been
3183 - * registered.
3184 - */
3185 -static void
3186 -ioc3_8250_register(struct ioc3_uartregs __iomem *uart)
3187 -{
3188 -#define COSMISC_CONSTANT 6
3189 -
3190 - struct uart_8250_port port = {
3191 - .port = {
3192 - .irq = 0,
3193 - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
3194 - .iotype = UPIO_MEM,
3195 - .regshift = 0,
3196 - .uartclk = (22000000 << 1) / COSMISC_CONSTANT,
3197 - .membase = (u8 __iomem *)uart,
3198 - .mapbase = (unsigned long)uart,
3199 - }
3200 - };
3201 - u8 lcr;
3202 -
3203 - lcr = uart->iu_lcr;
3204 - uart->iu_lcr = lcr | UART_LCR_DLAB;
3205 - uart->iu_scr = COSMISC_CONSTANT,
3206 - uart->iu_lcr = lcr;
3207 - uart->iu_lcr;
3208 - serial8250_register_8250_port(&port);
3209 -}
3210 -
3211 -static void
3212 -ioc3_serial_probe(struct pci_dev *pdev, struct ioc3 *ioc3)
3213 -{
3214 - /* We need to recognice and treat the fourth MENET serial as it
3215 - * does not have an SuperIO chip attached to it, therefore attempting
3216 - * to access it will result in bus errors. We call something an
3217 - * MENET if PCI slot 0, 1, 2 and 3 of a master PCI bus all have an IOC3
3218 - * in it. This is paranoid but we want to avoid blowing up on a
3219 - * showhorn PCI box that happens to have 4 IOC3 cards in it so it's
3220 - * not paranoid enough ...
3221 - */
3222 - if (ioc3_is_menet(pdev) && PCI_SLOT(pdev->devfn) == 3)
3223 - return;
3224 -
3225 - /* Switch IOC3 to PIO mode. It probably already was but let's be
3226 - * paranoid
3227 - */
3228 - ioc3->gpcr_s = GPCR_UARTA_MODESEL | GPCR_UARTB_MODESEL;
3229 - ioc3->gpcr_s;
3230 - ioc3->gppr_6 = 0;
3231 - ioc3->gppr_6;
3232 - ioc3->gppr_7 = 0;
3233 - ioc3->gppr_7;
3234 - ioc3->sscr_a = ioc3->sscr_a & ~SSCR_DMA_EN;
3235 - ioc3->sscr_a;
3236 - ioc3->sscr_b = ioc3->sscr_b & ~SSCR_DMA_EN;
3237 - ioc3->sscr_b;
3238 - /* Disable all SA/B interrupts except for SA/B_INT in SIO_IEC. */
3239 - ioc3->sio_iec &= ~ (SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL |
3240 - SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER |
3241 - SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS |
3242 - SIO_IR_SA_TX_EXPLICIT | SIO_IR_SA_MEMERR);
3243 - ioc3->sio_iec |= SIO_IR_SA_INT;
3244 - ioc3->sscr_a = 0;
3245 - ioc3->sio_iec &= ~ (SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL |
3246 - SIO_IR_SB_RX_HIGH | SIO_IR_SB_RX_TIMER |
3247 - SIO_IR_SB_DELTA_DCD | SIO_IR_SB_DELTA_CTS |
3248 - SIO_IR_SB_TX_EXPLICIT | SIO_IR_SB_MEMERR);
3249 - ioc3->sio_iec |= SIO_IR_SB_INT;
3250 - ioc3->sscr_b = 0;
3251 -
3252 - ioc3_8250_register(&ioc3->sregs.uarta);
3253 - ioc3_8250_register(&ioc3->sregs.uartb);
3254 -}
3255 -#endif
3256 -
3257 -static const struct net_device_ops
3258 -ioc3_netdev_ops = {
3259 - .ndo_open = ioc3_open,
3260 - .ndo_stop = ioc3_close,
3261 - .ndo_start_xmit = ioc3_start_xmit,
3262 - .ndo_tx_timeout = ioc3_timeout,
3263 - .ndo_get_stats = ioc3_get_stats,
3264 - .ndo_set_rx_mode = ioc3_set_multicast_list,
3265 - .ndo_do_ioctl = ioc3_ioctl,
3266 - .ndo_validate_addr = eth_validate_addr,
3267 - .ndo_set_mac_address = ioc3_set_mac_address,
3268 -};
3269 -
3270 -static int
3271 -ioc3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3272 -{
3273 - u32 sw_physid1, sw_physid2;
3274 - struct net_device *dev = NULL;
3275 - struct ioc3_private *ip;
3276 - struct ioc3 *ioc3;
3277 - unsigned long ioc3_base, ioc3_size;
3278 - u32 vendor, model, rev;
3279 - int err, pci_using_dac;
3280 -
3281 - /* Configure DMA attributes. */
3282 - err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3283 - if (!err) {
3284 - pci_using_dac = 1;
3285 - err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3286 - if (err < 0) {
3287 - printk(KERN_ERR "%s: Unable to obtain 64 bit DMA "
3288 - "for consistent allocations\n", pci_name(pdev));
3289 - goto out;
3290 - }
3291 - } else {
3292 - err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3293 - if (err) {
3294 - printk(KERN_ERR "%s: No usable DMA configuration, "
3295 - "aborting.\n", pci_name(pdev));
3296 - goto out;
3297 - }
3298 - pci_using_dac = 0;
3299 - }
3300 -
3301 - if (pci_enable_device(pdev))
3302 - return -ENODEV;
3303 -
3304 - dev = alloc_etherdev(sizeof(struct ioc3_private));
3305 - if (!dev) {
3306 - err = -ENOMEM;
3307 - goto out_disable;
3308 - }
3309 -
3310 - if (pci_using_dac)
3311 - dev->features |= NETIF_F_HIGHDMA;
3312 -
3313 - err = pci_request_regions(pdev, "ioc3");
3314 - if (err)
3315 - goto out_free;
3316 -
3317 - SET_NETDEV_DEV(dev, &pdev->dev);
3318 -
3319 - ip = netdev_priv(dev);
3320 - ip->dev = dev;
3321 -
3322 - dev->irq = pdev->irq;
3323 -
3324 - ioc3_base = pci_resource_start(pdev, 0);
3325 - ioc3_size = pci_resource_len(pdev, 0);
3326 - ioc3 = (struct ioc3 *) ioremap(ioc3_base, ioc3_size);
3327 - if (!ioc3) {
3328 - printk(KERN_CRIT "ioc3eth(%s): ioremap failed, goodbye.\n",
3329 - pci_name(pdev));
3330 - err = -ENOMEM;
3331 - goto out_res;
3332 - }
3333 - ip->regs = ioc3;
3334 -
3335 -#ifdef CONFIG_SERIAL_8250
3336 - ioc3_serial_probe(pdev, ioc3);
3337 -#endif
3338 -
3339 - spin_lock_init(&ip->ioc3_lock);
3340 - timer_setup(&ip->ioc3_timer, ioc3_timer, 0);
3341 -
3342 - ioc3_stop(ip);
3343 - ioc3_init(dev);
3344 -
3345 - ip->pdev = pdev;
3346 -
3347 - ip->mii.phy_id_mask = 0x1f;
3348 - ip->mii.reg_num_mask = 0x1f;
3349 - ip->mii.dev = dev;
3350 - ip->mii.mdio_read = ioc3_mdio_read;
3351 - ip->mii.mdio_write = ioc3_mdio_write;
3352 -
3353 - ioc3_mii_init(ip);
3354 -
3355 - if (ip->mii.phy_id == -1) {
3356 - printk(KERN_CRIT "ioc3-eth(%s): Didn't find a PHY, goodbye.\n",
3357 - pci_name(pdev));
3358 - err = -ENODEV;
3359 - goto out_stop;
3360 - }
3361 -
3362 - ioc3_mii_start(ip);
3363 - ioc3_ssram_disc(ip);
3364 - ioc3_get_eaddr(ip);
3365 -
3366 - /* The IOC3-specific entries in the device structure. */
3367 - dev->watchdog_timeo = 5 * HZ;
3368 - dev->netdev_ops = &ioc3_netdev_ops;
3369 - dev->ethtool_ops = &ioc3_ethtool_ops;
3370 - dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
3371 - dev->features = NETIF_F_IP_CSUM;
3372 -
3373 - sw_physid1 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID1);
3374 - sw_physid2 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID2);
3375 -
3376 - err = register_netdev(dev);
3377 - if (err)
3378 - goto out_stop;
3379 -
3380 - mii_check_media(&ip->mii, 1, 1);
3381 - ioc3_setup_duplex(ip);
3382 -
3383 - vendor = (sw_physid1 << 12) | (sw_physid2 >> 4);
3384 - model = (sw_physid2 >> 4) & 0x3f;
3385 - rev = sw_physid2 & 0xf;
3386 - printk(KERN_INFO "%s: Using PHY %d, vendor 0x%x, model %d, "
3387 - "rev %d.\n", dev->name, ip->mii.phy_id, vendor, model, rev);
3388 - printk(KERN_INFO "%s: IOC3 SSRAM has %d kbyte.\n", dev->name,
3389 - ip->emcr & EMCR_BUFSIZ ? 128 : 64);
3390 -
3391 - return 0;
3392 -
3393 -out_stop:
3394 - ioc3_stop(ip);
3395 - del_timer_sync(&ip->ioc3_timer);
3396 - ioc3_free_rings(ip);
3397 -out_res:
3398 - pci_release_regions(pdev);
3399 -out_free:
3400 - free_netdev(dev);
3401 -out_disable:
3402 - /*
3403 - * We should call pci_disable_device(pdev); here if the IOC3 wasn't
3404 - * such a weird device ...
3405 - */
3406 -out:
3407 - return err;
3408 -}
3409 -
3410 -static void
3411 -ioc3_remove_one(struct pci_dev *pdev)
3412 -{
3413 - struct net_device *dev = pci_get_drvdata(pdev);
3414 - struct ioc3_private *ip = netdev_priv(dev);
3415 - struct ioc3 *ioc3 = ip->regs;
3416 -
3417 - unregister_netdev(dev);
3418 - del_timer_sync(&ip->ioc3_timer);
3419 -
3420 - iounmap(ioc3);
3421 - pci_release_regions(pdev);
3422 - free_netdev(dev);
3423 - /*
3424 - * We should call pci_disable_device(pdev); here if the IOC3 wasn't
3425 - * such a weird device ...
3426 - */
3427 -}
3428 -
3429 -static const struct pci_device_id
3430 -ioc3_pci_tbl[] = {
3431 - { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, PCI_ANY_ID, PCI_ANY_ID },
3432 - { 0 }
3433 -};
3434 -MODULE_DEVICE_TABLE(pci, ioc3_pci_tbl);
3435 -
3436 -static struct pci_driver
3437 -ioc3_driver = {
3438 - .name = "ioc3-eth",
3439 - .id_table = ioc3_pci_tbl,
3440 - .probe = ioc3_probe,
3441 - .remove = ioc3_remove_one,
3442 -};
3443 -
3444 static int
3445 ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3446 {
3447 struct ioc3_private *ip = netdev_priv(dev);
3448 - struct ioc3 *ioc3 = ip->regs;
3449 struct ioc3_etxd *desc;
3450 unsigned long data;
3451 u32 len, w0 = 0;
3452 int produce;
3454 - /*
3455 - * IOC3 has a fairly simple minded checksumming hardware which simply
3456 + /* IOC3 has a fairly simple minded checksumming hardware which simply
3457 * adds up the 1's complement checksum for the entire packet and
3458 * inserts it at an offset which can be specified in the descriptor
3459 * into the transmit packet. This means we have to compensate for the
3460 @@ -1454,8 +662,8 @@ ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3461 * manually.
3462 */
3463 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3464 - const struct iphdr *ih = ip_hdr(skb);
3465 - const u32 proto = ntohs(ih->protocol);
3466 + struct iphdr *ih = ip_hdr(skb);
3467 + u32 proto = ntohs(ih->protocol);
3468 u32 csoff, csum, ehsum;
3469 u16 *eh;
3471 @@ -1492,7 +700,15 @@ ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3473 spin_lock_irq(&ip->ioc3_lock);
3475 - data = (unsigned long) skb->data;
3476 + if ((ip->txbfree <= 0)) {
3477 + netif_stop_queue(dev);
3478 + spin_unlock_irq(&ip->ioc3_lock);
3479 + printk(KERN_ERR "%s: BUG! Tx Ring full when queue awake!\n",
3480 + dev->name);
3481 + return NETDEV_TX_BUSY;
3482 + }
3483 +
3484 + data = (unsigned long)skb->data;
3485 len = skb->len;
3487 produce = ip->tx_pi;
3488 @@ -1517,25 +733,27 @@ ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3489 ETXD_B1V | ETXD_B2V | w0);
3490 desc->bufcnt = cpu_to_be32((s1 << ETXD_B1CNT_SHIFT) |
3491 (s2 << ETXD_B2CNT_SHIFT));
3492 - desc->p1 = cpu_to_be64(ioc3_map(skb->data, 1));
3493 - desc->p2 = cpu_to_be64(ioc3_map((void *) b2, 1));
3494 + desc->p1 = cpu_to_be64(ioc3_map(skb->data,
3495 + PCI64_ATTR_PREF));
3496 + desc->p2 = cpu_to_be64(ioc3_map((void *)b2,
3497 + PCI64_ATTR_PREF));
3498 } else {
3499 /* Normal sized packet that doesn't cross a page boundary. */
3500 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_B1V | w0);
3501 desc->bufcnt = cpu_to_be32(len << ETXD_B1CNT_SHIFT);
3502 - desc->p1 = cpu_to_be64(ioc3_map(skb->data, 1));
3503 + desc->p1 = cpu_to_be64(ioc3_map(skb->data,
3504 + PCI64_ATTR_PREF));
3505 }
3507 BARRIER();
3509 - ip->tx_skbs[produce] = skb; /* Remember skb */
3510 - produce = (produce + 1) & 0x7f;
3511 + ip->tx_skbs[produce] = skb; /* Remember skb */
3512 + produce = (produce + 1) & TX_MASK;
3513 ip->tx_pi = produce;
3514 - ioc3_w_etpir(produce << 7); /* Fire! */
3515 -
3516 - ip->txqlen++;
3517 + writel(produce << 7, &ip->idd->vma->etpir); /* Fire! */
3519 - if (ip->txqlen >= 127)
3520 + ip->txbfree--;
3521 + if (ip->txbfree == 0)
3522 netif_stop_queue(dev);
3524 spin_unlock_irq(&ip->ioc3_lock);
3525 @@ -1543,6 +761,35 @@ ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3526 return NETDEV_TX_OK;
3527 }
3529 +static int
3530 +ioc3_set_mac_address(struct net_device *dev, void *addr)
3531 +{
3532 + struct ioc3_private *ip = netdev_priv(dev);
3533 + struct ioc3 *vma = ip->idd->vma;
3534 + struct sockaddr *sa = addr;
3535 +
3536 + memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
3537 +
3538 + spin_lock_irq(&ip->ioc3_lock);
3539 + __ioc3_set_mac_address(dev, vma);
3540 + spin_unlock_irq(&ip->ioc3_lock);
3541 +
3542 + return 0;
3543 +}
3544 +
3545 +static int
3546 +ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3547 +{
3548 + struct ioc3_private *ip = netdev_priv(dev);
3549 + int rc;
3550 +
3551 + spin_lock_irq(&ip->ioc3_lock);
3552 + rc = generic_mii_ioctl(&ip->mii, if_mii(rq), cmd, NULL);
3553 + spin_unlock_irq(&ip->ioc3_lock);
3554 +
3555 + return rc;
3556 +}
3557 +
3558 static void
3559 ioc3_timeout(struct net_device *dev)
3560 {
3561 @@ -1550,42 +797,37 @@ ioc3_timeout(struct net_device *dev)
3563 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
3565 - spin_lock_irq(&ip->ioc3_lock);
3566 -
3567 ioc3_stop(ip);
3568 ioc3_init(dev);
3569 ioc3_mii_init(ip);
3570 ioc3_mii_start(ip);
3572 - spin_unlock_irq(&ip->ioc3_lock);
3573 -
3574 netif_wake_queue(dev);
3575 }
3577 -/*
3578 - * Given a multicast ethernet address, this routine calculates the
3579 - * address's bit index in the logical address filter mask
3580 - */
3581 -
3582 -static inline u32
3583 -ioc3_hash(const u8 *addr)
3584 +static struct net_device_stats *
3585 +ioc3_get_stats(struct net_device *dev)
3586 {
3587 - u32 temp = 0;
3588 - u32 crc;
3589 - int bits;
3590 -
3591 - crc = ether_crc_le(ETH_ALEN, addr);
3592 -
3593 - crc &= 0x3f; /* bit reverse lowest 6 bits for hash index */
3594 - for (bits = 6; --bits >= 0; ) {
3595 - temp <<= 1;
3596 - temp |= (crc & 0x1);
3597 - crc >>= 1;
3598 - }
3599 + struct ioc3_private *ip = netdev_priv(dev);
3600 + struct ioc3 *vma = ip->idd->vma;
3602 - return temp;
3603 + dev->stats.collisions += (readl(&vma->etcdc) & ETCDC_COLLCNT_MASK);
3604 + return &dev->stats;
3605 }
3607 +static const struct net_device_ops
3608 +ioc3_netdev_ops = {
3609 + .ndo_open = ioc3_open,
3610 + .ndo_stop = ioc3_close,
3611 + .ndo_start_xmit = ioc3_start_xmit,
3612 + .ndo_tx_timeout = ioc3_timeout,
3613 + .ndo_get_stats = ioc3_get_stats,
3614 + .ndo_set_rx_mode = ioc3_set_multicast_list,
3615 + .ndo_do_ioctl = ioc3_ioctl,
3616 + .ndo_validate_addr = eth_validate_addr,
3617 + .ndo_set_mac_address = ioc3_set_mac_address,
3618 +};
3619 +
3620 static void
3621 ioc3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3622 {
3623 @@ -1593,7 +835,8 @@ ioc3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3625 strlcpy(info->driver, IOC3_NAME, sizeof(info->driver));
3626 strlcpy(info->version, IOC3_VERSION, sizeof(info->version));
3627 - strlcpy(info->bus_info, pci_name(ip->pdev), sizeof(info->bus_info));
3628 + strlcpy(info->bus_info, pci_name(ip->idd->pdev),
3629 + sizeof(info->bus_info));
3630 }
3632 static int
3633 @@ -1658,61 +901,303 @@ ioc3_ethtool_ops = {
3634 .set_link_ksettings = ioc3_set_link_ksettings,
3635 };
3637 -static int
3638 -ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3639 +/* Deal with fatal IOC3 errors. This condition might be caused by a hard or
3640 + * software problems, so we should try to recover
3641 + * more gracefully if this ever happens. In theory we might be flooded
3642 + * with such error interrupts if something really goes wrong, so we might
3643 + * also consider to take the interface down.
3644 + */
3645 +static noinline void
3646 +ioc3_error(struct ioc3_private *ip, struct net_device *dev, u32 eisr)
3647 {
3648 - struct ioc3_private *ip = netdev_priv(dev);
3649 - int rc;
3650 + u8 *iface = dev->name;
3652 - spin_lock_irq(&ip->ioc3_lock);
3653 - rc = generic_mii_ioctl(&ip->mii, if_mii(rq), cmd, NULL);
3654 - spin_unlock_irq(&ip->ioc3_lock);
3655 + if (eisr & EISR_RXOFLO)
3656 + printk(KERN_ERR "%s: RX overflow.\n", iface);
3657 + if (eisr & EISR_RXBUFOFLO)
3658 + printk(KERN_ERR "%s: RX buffer overflow.\n", iface);
3659 + if (eisr & EISR_RXMEMERR)
3660 + printk(KERN_ERR "%s: RX PCI error.\n", iface);
3661 + if (eisr & EISR_RXPARERR)
3662 + printk(KERN_ERR "%s: RX SSRAM parity error.\n", iface);
3663 + if (eisr & EISR_TXBUFUFLO)
3664 + printk(KERN_ERR "%s: TX buffer underflow.\n", iface);
3665 + if (eisr & EISR_TXMEMERR)
3666 + printk(KERN_ERR "%s: TX PCI error.\n", iface);
3668 - return rc;
3669 + ioc3_stop(ip);
3670 +
3671 + /* This can trigger a BUG(): sleeping function called */
3672 + ioc3_init(dev);
3673 + ioc3_mii_init(ip);
3674 + ioc3_mii_start(ip);
3675 +
3676 + netif_wake_queue(dev);
3677 }
3679 -static void
3680 -ioc3_set_multicast_list(struct net_device *dev)
3681 +static noinline void
3682 +ioc3_rx(struct ioc3_private *ip, struct net_device *dev)
3683 {
3684 - struct netdev_hw_addr *ha;
3685 - struct ioc3_private *ip = netdev_priv(dev);
3686 - struct ioc3 *ioc3 = ip->regs;
3687 - u64 ehar = 0;
3688 + struct sk_buff *skb, *new_skb;
3689 + struct ioc3_erxbuf *rxb;
3690 + int rx_entry, n_entry, len;
3691 + u32 w0, err;
3693 - netif_stop_queue(dev); /* Lock out others. */
3694 + rx_entry = ip->rx_ci; /* RX consume index */
3695 + n_entry = ip->rx_pi;
3697 - if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
3698 - ip->emcr |= EMCR_PROMISC;
3699 - ioc3_w_emcr(ip->emcr);
3700 - (void) ioc3_r_emcr();
3701 - } else {
3702 - ip->emcr &= ~EMCR_PROMISC;
3703 - ioc3_w_emcr(ip->emcr); /* Clear promiscuous. */
3704 - (void) ioc3_r_emcr();
3705 + skb = ip->rx_skbs[rx_entry];
3706 + rxb = (struct ioc3_erxbuf *)(skb->data - RX_OFFSET);
3707 + w0 = be32_to_cpu(rxb->w0);
3709 - if ((dev->flags & IFF_ALLMULTI) ||
3710 - (netdev_mc_count(dev) > 64)) {
3711 - /* Too many for hashing to make sense or we want all
3712 - * multicast packets anyway, so skip computing all
3713 - * the hashes and just accept all packets.
3714 - */
3715 - ip->ehar_h = 0xffffffff;
3716 - ip->ehar_l = 0xffffffff;
3717 - } else {
3718 - netdev_for_each_mc_addr(ha, dev) {
3719 - ehar |= (1UL << ioc3_hash(ha->addr));
3720 + while (w0 & ERXBUF_V) {
3721 + err = be32_to_cpu(rxb->err); /* It's valid */
3722 + if (err & ERXBUF_GOODPKT) {
3723 + len = ((w0 >> ERXBUF_BYTECNT_SHIFT) & 0x7ff) - 4;
3724 + skb_trim(skb, len);
3725 + skb->protocol = eth_type_trans(skb, dev);
3726 +
3727 + new_skb = ioc3_alloc_skb(dev);
3728 + if (!new_skb) {
3729 + /* Ouch, drop packet and just recycle packet
3730 + * to keep the ring filled.
3731 + */
3732 + dev->stats.rx_dropped++;
3733 + new_skb = skb;
3734 + goto next;
3735 }
3736 - ip->ehar_h = ehar >> 32;
3737 - ip->ehar_l = ehar & 0xffffffff;
3738 +
3739 + if (likely(ip->flags & IOC3_FLAG_RX_CHECKSUMS))
3740 + ioc3_tcpudp_checksum(skb,
3741 + (w0 & ERXBUF_IPCKSUM_MASK),
3742 + len);
3743 +
3744 + netif_rx(skb);
3745 +
3746 + ip->rx_skbs[rx_entry] = NULL; /* Poison */
3747 +
3748 + /* Because we reserve afterwards. */
3749 + skb_put(new_skb, (RX_BUF_SIZE + RX_OFFSET));
3750 + rxb = (struct ioc3_erxbuf *)new_skb->data;
3751 + skb_reserve(new_skb, RX_OFFSET);
3752 +
3753 + dev->stats.rx_packets++; /* Statistics */
3754 + dev->stats.rx_bytes += len;
3755 + } else {
3756 + /* The frame is invalid and the skb never reached the
3757 + * network layer so we can just recycle it.
3758 + */
3759 + new_skb = skb;
3760 + dev->stats.rx_errors++;
3761 }
3762 - ioc3_w_ehar_h(ip->ehar_h);
3763 - ioc3_w_ehar_l(ip->ehar_l);
3764 +
3765 + /* Statistics */
3766 + if (err & ERXBUF_CRCERR)
3767 + dev->stats.rx_crc_errors++;
3768 + if (err & ERXBUF_FRAMERR)
3769 + dev->stats.rx_frame_errors++;
3770 +next:
3771 + ip->rx_skbs[rx_entry] = new_skb;
3772 + ip->rxr[rx_entry] = cpu_to_be64(ioc3_map(rxb, PCI64_ATTR_BAR));
3773 + rxb->w0 = 0; /* Clear valid flag */
3774 +
3775 + /* Now go on to the next ring entry. */
3776 + n_entry++;
3777 + n_entry &= RX_MASK;
3778 + rx_entry++;
3779 + rx_entry &= RX_MASK;
3780 +
3781 + skb = ip->rx_skbs[rx_entry];
3782 + rxb = (struct ioc3_erxbuf *)(skb->data - RX_OFFSET);
3783 + w0 = be32_to_cpu(rxb->w0);
3784 + }
3785 + ip->rx_ci = rx_entry;
3786 + ip->rx_pi = n_entry;
3787 + writel((n_entry << 3) | ERPIR_ARM, &ip->idd->vma->erpir);
3788 +}
3789 +
3790 +static noinline void
3791 +ioc3_tx(struct ioc3_private *ip, struct net_device *dev)
3792 +{
3793 + struct sk_buff *skb;
3794 + struct ioc3 *vma = ip->idd->vma;
3795 + unsigned long packets = 0;
3796 + unsigned long bytes = 0;
3797 + int tx_entry, o_entry;
3798 + u32 etcir;
3799 +
3800 + etcir = readl(&vma->etcir);
3801 + tx_entry = (etcir >> 7) & TX_MASK;
3802 + o_entry = ip->tx_ci;
3803 +
3804 + while (o_entry != tx_entry) {
3805 + packets++;
3806 + skb = ip->tx_skbs[o_entry];
3807 + bytes += skb->len;
3808 + dev_kfree_skb_irq(skb);
3809 + ip->tx_skbs[o_entry] = NULL;
3810 +
3811 + etcir = readl(&vma->etcir); /* More pkts sent? */
3812 + tx_entry = (etcir >> 7) & TX_MASK;
3813 + o_entry = (o_entry + 1) & TX_MASK; /* Next */
3814 }
3815 + ip->tx_ci = o_entry;
3817 - netif_wake_queue(dev); /* Let us get going again. */
3818 + dev->stats.tx_bytes += bytes;
3819 + dev->stats.tx_packets += packets;
3820 + ip->txbfree += packets;
3821 +
3822 + if (netif_queue_stopped(dev) && (ip->txbfree > 0))
3823 + netif_wake_queue(dev);
3824 }
3826 -module_pci_driver(ioc3_driver);
3827 +/* The interrupt handler does all of the Rx thread work
3828 + * and cleans up after the Tx thread.
3829 + */
3830 +static int
3831 +ioc3eth_intr(struct ioc3_submodule *is, struct ioc3_driver_data *idd, u32 irq)
3832 +{
3833 + struct net_device *dev = (struct net_device *)(idd->data[is->id]);
3834 + struct ioc3_private *ip = netdev_priv(dev);
3835 + struct ioc3 *vma = idd->vma;
3836 + u32 eisr;
3837 +
3838 + spin_lock(&ip->ioc3_lock);
3839 +
3840 + eisr = readl(&vma->eisr);
3841 +
3842 + writel(eisr, &vma->eisr);
3843 + (void)readl(&vma->eisr); /* Flush */
3844 +
3845 + if (eisr & (EISR_RXTIMERINT | EISR_RXTHRESHINT))
3846 + ioc3_rx(ip, dev);
3847 +
3848 + if (eisr & (EISR_TXEMPTY | EISR_TXEXDEF | EISR_TXEXPLICIT))
3849 + ioc3_tx(ip, dev);
3850 +
3851 + if (eisr & (EISR_RXOFLO | EISR_RXBUFOFLO |
3852 + EISR_RXMEMERR | EISR_RXPARERR |
3853 + EISR_TXBUFUFLO | EISR_TXMEMERR))
3854 + ioc3_error(ip, dev, eisr);
3855 +
3856 + spin_unlock(&ip->ioc3_lock);
3857 +
3858 + return 0;
3859 +}
3860 +
3861 +static int
3862 +ioc3eth_probe(struct ioc3_submodule *is, struct ioc3_driver_data *idd)
3863 +{
3864 + struct net_device *dev;
3865 + struct ioc3_private *ip;
3866 + u32 sw_physid1, sw_physid2, vendor, model, rev;
3867 + int err;
3868 +
3869 + /* check for board type */
3870 + if (idd->class == IOC3_CLASS_SERIAL)
3871 + return 1;
3872 +
3873 + dev = alloc_etherdev(sizeof(struct ioc3_private));
3874 + if (!dev) {
3875 + err = -ENOMEM;
3876 + goto out;
3877 + }
3878 +
3879 + /* The IOC3-specific entries in the device structure. */
3880 + dev->watchdog_timeo = 5 * HZ;
3881 + dev->netdev_ops = &ioc3_netdev_ops;
3882 + dev->ethtool_ops = &ioc3_ethtool_ops;
3883 + dev->features = NETIF_F_IP_CSUM | NETIF_F_HIGHDMA;
3884 +
3885 + idd->data[is->id] = dev;
3886 + SET_NETDEV_DEV(dev, &idd->pdev->dev);
3887 + dev->irq = idd->pdev->irq;
3888 +
3889 + ip = netdev_priv(dev);
3890 + ip->dev = dev;
3891 + ip->idd = idd;
3892 +
3893 + spin_lock_init(&ip->ioc3_lock);
3894 + timer_setup(&ip->ioc3_timer, ioc3_timer, 0);
3895 +
3896 + ioc3_stop(ip);
3897 + ioc3_init(dev);
3898 +
3899 + ip->mii.phy_id_mask = 0x1f;
3900 + ip->mii.reg_num_mask = 0x1f;
3901 + ip->mii.dev = dev;
3902 + ip->mii.mdio_read = ioc3_mdio_read;
3903 + ip->mii.mdio_write = ioc3_mdio_write;
3904 +
3905 + ioc3_mii_init(ip);
3906 +
3907 + if (ip->mii.phy_id == -1) {
3908 + printk(KERN_CRIT "ioc3-eth(%s): Didn't find a PHY, goodbye.\n",
3909 + pci_name(idd->pdev));
3910 + err = -ENODEV;
3911 + goto out_stop;
3912 + }
3913 +
3914 + ioc3_mii_start(ip);
3915 + ioc3_ssram_disc(ip);
3916 + ioc3_get_eaddr(idd, dev);
3917 +
3918 + sw_physid1 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID1);
3919 + sw_physid2 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID2);
3920 +
3921 + err = register_netdev(dev);
3922 + if (err)
3923 + goto out_stop;
3924 +
3925 + mii_check_media(&ip->mii, 1, 1);
3926 + ioc3_setup_duplex(ip);
3927 +
3928 + vendor = (sw_physid1 << 12) | (sw_physid2 >> 4);
3929 + model = (sw_physid2 >> 4) & 0x3f;
3930 + rev = sw_physid2 & 0xf;
3931 + printk(KERN_INFO "%s: Using PHY %d, vendor 0x%x, model %d, rev %d.\n",
3932 + dev->name, ip->mii.phy_id, vendor, model, rev);
3933 + printk(KERN_INFO "%s: IOC3 SSRAM has %d kbyte.\n", dev->name,
3934 + (ip->emcr & EMCR_BUFSIZ ? 128 : 64));
3935 +
3936 + return 0;
3937 +
3938 +out_stop:
3939 + ioc3_stop(ip);
3940 + del_timer_sync(&ip->ioc3_timer);
3941 + ioc3_free_rings(ip);
3942 + free_netdev(dev);
3943 +out:
3944 + return err;
3945 +}
3946 +
3947 +static int
3948 +ioc3eth_remove(struct ioc3_submodule *is, struct ioc3_driver_data *idd)
3949 +{
3950 + struct net_device *dev = idd->data[is->id];
3951 + struct ioc3_private *ip = netdev_priv(dev);
3952 +
3953 + unregister_netdev(dev);
3954 + del_timer_sync(&ip->ioc3_timer);
3955 + ioc3_free_rings(ip);
3956 + free_netdev(dev);
3957 +
3958 + return 0;
3959 +}
3960 +
3961 +static struct
3962 +ioc3_submodule ioc3eth_driver = {
3963 + .name = "Ethernet",
3964 + .probe = ioc3eth_probe,
3965 + .remove = ioc3eth_remove,
3966 + .ethernet = 1,
3967 + .intr = ioc3eth_intr,
3968 + .owner = THIS_MODULE,
3969 +};
3970 +
3971 +ioc3_submodule_driver(ioc3eth_driver);
3972 +
3973 MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
3974 MODULE_DESCRIPTION("SGI IOC3 Ethernet driver");
3975 MODULE_LICENSE("GPL");
3976 +
3977 diff --git a/drivers/sn/Kconfig b/drivers/sn/Kconfig
3978 deleted file mode 100644
3979 index c66ba9ad833d..000000000000
3980 --- a/drivers/sn/Kconfig
3981 +++ /dev/null
3982 @@ -1,21 +0,0 @@
3983 -#
3984 -# Miscellaneous SN-specific devices
3985 -#
3986 -
3987 -menu "SN Devices"
3988 - depends on SGI_SN
3989 -
3990 -config SGI_IOC3
3991 - tristate "SGI IOC3 Base IO support"
3992 - default m
3993 - ---help---
3994 - This option enables basic support for the SGI IOC3-based Base IO
3995 - controller card. This option does not enable any specific
3996 - functions on such a card, but provides necessary infrastructure
3997 - for other drivers to utilize.
3998 -
3999 - If you have an SGI Altix with an IOC3-based
4000 - I/O controller or a PCI IOC3 serial card say Y.
4001 - Otherwise say N.
4002 -
4003 -endmenu
4004 diff --git a/drivers/sn/Makefile b/drivers/sn/Makefile
4005 deleted file mode 100644
4006 index 693db8bb8d9c..000000000000
4007 --- a/drivers/sn/Makefile
4008 +++ /dev/null
4009 @@ -1,6 +0,0 @@
4010 -#
4011 -# Makefile for the Altix device drivers.
4012 -#
4013 -#
4014 -
4015 -obj-$(CONFIG_SGI_IOC3) += ioc3.o
4016 diff --git a/drivers/sn/ioc3.c b/drivers/sn/ioc3.c
4017 deleted file mode 100644
4018 index fb7ea0d9a734..000000000000
4019 --- a/drivers/sn/ioc3.c
4020 +++ /dev/null
4021 @@ -1,843 +0,0 @@
4022 -/*
4023 - * SGI IOC3 master driver and IRQ demuxer
4024 - *
4025 - * Copyright (c) 2005 Stanislaw Skowronek <skylark@linux-mips.org>
4026 - * Heavily based on similar work by:
4027 - * Brent Casavant <bcasavan@sgi.com> - IOC4 master driver
4028 - * Pat Gefre <pfg@sgi.com> - IOC3 serial port IRQ demuxer
4029 - */
4030 -
4031 -#include <linux/errno.h>
4032 -#include <linux/module.h>
4033 -#include <linux/pci.h>
4034 -#include <linux/dma-mapping.h>
4035 -#include <linux/interrupt.h>
4036 -#include <linux/spinlock.h>
4037 -#include <linux/delay.h>
4038 -#include <linux/ioc3.h>
4039 -#include <linux/rwsem.h>
4040 -#include <linux/slab.h>
4041 -
4042 -#define IOC3_PCI_SIZE 0x100000
4043 -
4044 -static LIST_HEAD(ioc3_devices);
4045 -static int ioc3_counter;
4046 -static DECLARE_RWSEM(ioc3_devices_rwsem);
4047 -
4048 -static struct ioc3_submodule *ioc3_submodules[IOC3_MAX_SUBMODULES];
4049 -static struct ioc3_submodule *ioc3_ethernet;
4050 -static DEFINE_RWLOCK(ioc3_submodules_lock);
4051 -
4052 -/* NIC probing code */
4053 -
4054 -#define GPCR_MLAN_EN 0x00200000 /* enable MCR to pin 8 */
4055 -
4056 -static inline unsigned mcr_pack(unsigned pulse, unsigned sample)
4057 -{
4058 - return (pulse << 10) | (sample << 2);
4059 -}
4060 -
4061 -static int nic_wait(struct ioc3_driver_data *idd)
4062 -{
4063 - unsigned mcr;
4064 -
4065 - do {
4066 - mcr = readl(&idd->vma->mcr);
4067 - } while (!(mcr & 2));
4068 -
4069 - return mcr & 1;
4070 -}
4071 -
4072 -static int nic_reset(struct ioc3_driver_data *idd)
4073 -{
4074 - int presence;
4075 - unsigned long flags;
4076 -
4077 - local_irq_save(flags);
4078 - writel(mcr_pack(500, 65), &idd->vma->mcr);
4079 - presence = nic_wait(idd);
4080 - local_irq_restore(flags);
4081 -
4082 - udelay(500);
4083 -
4084 - return presence;
4085 -}
4086 -
4087 -static int nic_read_bit(struct ioc3_driver_data *idd)
4088 -{
4089 - int result;
4090 - unsigned long flags;
4091 -
4092 - local_irq_save(flags);
4093 - writel(mcr_pack(6, 13), &idd->vma->mcr);
4094 - result = nic_wait(idd);
4095 - local_irq_restore(flags);
4096 -
4097 - udelay(500);
4098 -
4099 - return result;
4100 -}
4101 -
4102 -static void nic_write_bit(struct ioc3_driver_data *idd, int bit)
4103 -{
4104 - if (bit)
4105 - writel(mcr_pack(6, 110), &idd->vma->mcr);
4106 - else
4107 - writel(mcr_pack(80, 30), &idd->vma->mcr);
4108 -
4109 - nic_wait(idd);
4110 -}
4111 -
4112 -static unsigned nic_read_byte(struct ioc3_driver_data *idd)
4113 -{
4114 - unsigned result = 0;
4115 - int i;
4116 -
4117 - for (i = 0; i < 8; i++)
4118 - result = (result >> 1) | (nic_read_bit(idd) << 7);
4119 -
4120 - return result;
4121 -}
4122 -
4123 -static void nic_write_byte(struct ioc3_driver_data *idd, int byte)
4124 -{
4125 - int i, bit;
4126 -
4127 - for (i = 8; i; i--) {
4128 - bit = byte & 1;
4129 - byte >>= 1;
4130 -
4131 - nic_write_bit(idd, bit);
4132 - }
4133 -}
4134 -
4135 -static unsigned long
4136 -nic_find(struct ioc3_driver_data *idd, int *last, unsigned long addr)
4137 -{
4138 - int a, b, index, disc;
4139 -
4140 - nic_reset(idd);
4141 -
4142 - /* Search ROM. */
4143 - nic_write_byte(idd, 0xF0);
4144 -
4145 - /* Algorithm from ``Book of iButton Standards''. */
4146 - for (index = 0, disc = 0; index < 64; index++) {
4147 - a = nic_read_bit(idd);
4148 - b = nic_read_bit(idd);
4149 -
4150 - if (a && b) {
4151 - printk(KERN_WARNING "IOC3 NIC search failed.\n");
4152 - *last = 0;
4153 - return 0;
4154 - }
4155 -
4156 - if (!a && !b) {
4157 - if (index == *last) {
4158 - addr |= 1UL << index;
4159 - } else if (index > *last) {
4160 - addr &= ~(1UL << index);
4161 - disc = index;
4162 - } else if ((addr & (1UL << index)) == 0)
4163 - disc = index;
4164 - nic_write_bit(idd, (addr>>index)&1);
4165 - continue;
4166 - } else {
4167 - if (a)
4168 - addr |= 1UL << index;
4169 - else
4170 - addr &= ~(1UL << index);
4171 - nic_write_bit(idd, a);
4172 - continue;
4173 - }
4174 - }
4175 - *last = disc;
4176 - return addr;
4177 -}
4178 -
4179 -static void nic_addr(struct ioc3_driver_data *idd, unsigned long addr)
4180 -{
4181 - int index;
4182 -
4183 - nic_reset(idd);
4184 - nic_write_byte(idd, 0xF0);
4185 - for (index = 0; index < 64; index++) {
4186 - nic_read_bit(idd);
4187 - nic_read_bit(idd);
4188 - nic_write_bit(idd, (addr>>index)&1);
4189 - }
4190 -}
4191 -
4192 -static void crc16_byte(unsigned int *crc, unsigned char db)
4193 -{
4194 - int i;
4195 -
4196 - for(i=0;i<8;i++) {
4197 - *crc <<= 1;
4198 - if((db^(*crc>>16)) & 1)
4199 - *crc ^= 0x8005;
4200 - db >>= 1;
4201 - }
4202 - *crc &= 0xFFFF;
4203 -}
4204 -
4205 -static unsigned int crc16_area(unsigned char *dbs, int size, unsigned int crc)
4206 -{
4207 - while(size--)
4208 - crc16_byte(&crc, *(dbs++));
4209 - return crc;
4210 -}
4211 -
4212 -static void crc8_byte(unsigned int *crc, unsigned char db)
4213 -{
4214 - int i,f;
4215 -
4216 - for(i=0;i<8;i++) {
4217 - f = (*crc ^ db) & 1;
4218 - *crc >>= 1;
4219 - db >>= 1;
4220 - if(f)
4221 - *crc ^= 0x8c;
4222 - }
4223 - *crc &= 0xff;
4224 -}
4225 -
4226 -static unsigned int crc8_addr(unsigned long addr)
4227 -{
4228 - int i;
4229 - unsigned int crc = 0x00;
4230 -
4231 - for(i=0;i<8;i++)
4232 - crc8_byte(&crc, addr>>(i<<3));
4233 - return crc;
4234 -}
4235 -
4236 -static void
4237 -read_redir_page(struct ioc3_driver_data *idd, unsigned long addr, int page,
4238 - unsigned char *redir, unsigned char *data)
4239 -{
4240 - int loops = 16, i;
4241 -
4242 - while(redir[page] != 0xFF) {
4243 - page = redir[page]^0xFF;
4244 - loops--;
4245 - if(loops<0) {
4246 - printk(KERN_ERR "IOC3: NIC circular redirection\n");
4247 - return;
4248 - }
4249 - }
4250 - loops = 3;
4251 - while(loops>0) {
4252 - nic_addr(idd, addr);
4253 - nic_write_byte(idd, 0xF0);
4254 - nic_write_byte(idd, (page << 5) & 0xE0);
4255 - nic_write_byte(idd, (page >> 3) & 0x1F);
4256 - for(i=0;i<0x20;i++)
4257 - data[i] = nic_read_byte(idd);
4258 - if(crc16_area(data, 0x20, 0x0000) == 0x800d)
4259 - return;
4260 - loops--;
4261 - }
4262 - printk(KERN_ERR "IOC3: CRC error in data page\n");
4263 - for(i=0;i<0x20;i++)
4264 - data[i] = 0x00;
4265 -}
4266 -
4267 -static void
4268 -read_redir_map(struct ioc3_driver_data *idd, unsigned long addr,
4269 - unsigned char *redir)
4270 -{
4271 - int i,j,loops = 3,crc_ok;
4272 - unsigned int crc;
4273 -
4274 - while(loops>0) {
4275 - crc_ok = 1;
4276 - nic_addr(idd, addr);
4277 - nic_write_byte(idd, 0xAA);
4278 - nic_write_byte(idd, 0x00);
4279 - nic_write_byte(idd, 0x01);
4280 - for(i=0;i<64;i+=8) {
4281 - for(j=0;j<8;j++)
4282 - redir[i+j] = nic_read_byte(idd);
4283 - crc = crc16_area(redir+i, 8, (i==0)?0x8707:0x0000);
4284 - crc16_byte(&crc, nic_read_byte(idd));
4285 - crc16_byte(&crc, nic_read_byte(idd));
4286 - if(crc != 0x800d)
4287 - crc_ok = 0;
4288 - }
4289 - if(crc_ok)
4290 - return;
4291 - loops--;
4292 - }
4293 - printk(KERN_ERR "IOC3: CRC error in redirection page\n");
4294 - for(i=0;i<64;i++)
4295 - redir[i] = 0xFF;
4296 -}
4297 -
4298 -static void read_nic(struct ioc3_driver_data *idd, unsigned long addr)
4299 -{
4300 - unsigned char redir[64];
4301 - unsigned char data[64],part[32];
4302 - int i,j;
4303 -
4304 - /* read redirections */
4305 - read_redir_map(idd, addr, redir);
4306 - /* read data pages */
4307 - read_redir_page(idd, addr, 0, redir, data);
4308 - read_redir_page(idd, addr, 1, redir, data+32);
4309 - /* assemble the part # */
4310 - j=0;
4311 - for(i=0;i<19;i++)
4312 - if(data[i+11] != ' ')
4313 - part[j++] = data[i+11];
4314 - for(i=0;i<6;i++)
4315 - if(data[i+32] != ' ')
4316 - part[j++] = data[i+32];
4317 - part[j] = 0;
4318 - /* skip Octane power supplies */
4319 - if(!strncmp(part, "060-0035-", 9))
4320 - return;
4321 - if(!strncmp(part, "060-0038-", 9))
4322 - return;
4323 - strcpy(idd->nic_part, part);
4324 - /* assemble the serial # */
4325 - j=0;
4326 - for(i=0;i<10;i++)
4327 - if(data[i+1] != ' ')
4328 - idd->nic_serial[j++] = data[i+1];
4329 - idd->nic_serial[j] = 0;
4330 -}
4331 -
4332 -static void read_mac(struct ioc3_driver_data *idd, unsigned long addr)
4333 -{
4334 - int i, loops = 3;
4335 - unsigned char data[13];
4336 -
4337 - while(loops>0) {
4338 - nic_addr(idd, addr);
4339 - nic_write_byte(idd, 0xF0);
4340 - nic_write_byte(idd, 0x00);
4341 - nic_write_byte(idd, 0x00);
4342 - nic_read_byte(idd);
4343 - for(i=0;i<13;i++)
4344 - data[i] = nic_read_byte(idd);
4345 - if(crc16_area(data, 13, 0x0000) == 0x800d) {
4346 - for(i=10;i>4;i--)
4347 - idd->nic_mac[10-i] = data[i];
4348 - return;
4349 - }
4350 - loops--;
4351 - }
4352 - printk(KERN_ERR "IOC3: CRC error in MAC address\n");
4353 - for(i=0;i<6;i++)
4354 - idd->nic_mac[i] = 0x00;
4355 -}
4356 -
4357 -static void probe_nic(struct ioc3_driver_data *idd)
4358 -{
4359 - int save = 0, loops = 3;
4360 - unsigned long first, addr;
4361 -
4362 - writel(GPCR_MLAN_EN, &idd->vma->gpcr_s);
4363 -
4364 - while(loops>0) {
4365 - idd->nic_part[0] = 0;
4366 - idd->nic_serial[0] = 0;
4367 - addr = first = nic_find(idd, &save, 0);
4368 - if(!first)
4369 - return;
4370 - while(1) {
4371 - if(crc8_addr(addr))
4372 - break;
4373 - else {
4374 - switch(addr & 0xFF) {
4375 - case 0x0B:
4376 - read_nic(idd, addr);
4377 - break;
4378 - case 0x09:
4379 - case 0x89:
4380 - case 0x91:
4381 - read_mac(idd, addr);
4382 - break;
4383 - }
4384 - }
4385 - addr = nic_find(idd, &save, addr);
4386 - if(addr == first)
4387 - return;
4388 - }
4389 - loops--;
4390 - }
4391 - printk(KERN_ERR "IOC3: CRC error in NIC address\n");
4392 -}
4393 -
4394 -/* Interrupts */
4395 -
4396 -static void write_ireg(struct ioc3_driver_data *idd, uint32_t val, int which)
4397 -{
4398 - unsigned long flags;
4399 -
4400 - spin_lock_irqsave(&idd->ir_lock, flags);
4401 - switch (which) {
4402 - case IOC3_W_IES:
4403 - writel(val, &idd->vma->sio_ies);
4404 - break;
4405 - case IOC3_W_IEC:
4406 - writel(val, &idd->vma->sio_iec);
4407 - break;
4408 - }
4409 - spin_unlock_irqrestore(&idd->ir_lock, flags);
4410 -}
4411 -static inline uint32_t get_pending_intrs(struct ioc3_driver_data *idd)
4412 -{
4413 - unsigned long flag;
4414 - uint32_t intrs = 0;
4415 -
4416 - spin_lock_irqsave(&idd->ir_lock, flag);
4417 - intrs = readl(&idd->vma->sio_ir);
4418 - intrs &= readl(&idd->vma->sio_ies);
4419 - spin_unlock_irqrestore(&idd->ir_lock, flag);
4420 - return intrs;
4421 -}
4422 -
4423 -static irqreturn_t ioc3_intr_io(int irq, void *arg)
4424 -{
4425 - unsigned long flags;
4426 - struct ioc3_driver_data *idd = arg;
4427 - int handled = 1, id;
4428 - unsigned int pending;
4429 -
4430 - read_lock_irqsave(&ioc3_submodules_lock, flags);
4431 -
4432 - if(idd->dual_irq && readb(&idd->vma->eisr)) {
4433 - /* send Ethernet IRQ to the driver */
4434 - if(ioc3_ethernet && idd->active[ioc3_ethernet->id] &&
4435 - ioc3_ethernet->intr) {
4436 - handled = handled && !ioc3_ethernet->intr(ioc3_ethernet,
4437 - idd, 0);
4438 - }
4439 - }
4440 - pending = get_pending_intrs(idd); /* look at the IO IRQs */
4441 -
4442 - for(id=0;id<IOC3_MAX_SUBMODULES;id++) {
4443 - if(idd->active[id] && ioc3_submodules[id]
4444 - && (pending & ioc3_submodules[id]->irq_mask)
4445 - && ioc3_submodules[id]->intr) {
4446 - write_ireg(idd, ioc3_submodules[id]->irq_mask,
4447 - IOC3_W_IEC);
4448 - if(!ioc3_submodules[id]->intr(ioc3_submodules[id],
4449 - idd, pending & ioc3_submodules[id]->irq_mask))
4450 - pending &= ~ioc3_submodules[id]->irq_mask;
4451 - if (ioc3_submodules[id]->reset_mask)
4452 - write_ireg(idd, ioc3_submodules[id]->irq_mask,
4453 - IOC3_W_IES);
4454 - }
4455 - }
4456 - read_unlock_irqrestore(&ioc3_submodules_lock, flags);
4457 - if(pending) {
4458 - printk(KERN_WARNING
4459 - "IOC3: Pending IRQs 0x%08x discarded and disabled\n",pending);
4460 - write_ireg(idd, pending, IOC3_W_IEC);
4461 - handled = 1;
4462 - }
4463 - return handled?IRQ_HANDLED:IRQ_NONE;
4464 -}
4465 -
4466 -static irqreturn_t ioc3_intr_eth(int irq, void *arg)
4467 -{
4468 - unsigned long flags;
4469 - struct ioc3_driver_data *idd = (struct ioc3_driver_data *)arg;
4470 - int handled = 1;
4471 -
4472 - if(!idd->dual_irq)
4473 - return IRQ_NONE;
4474 - read_lock_irqsave(&ioc3_submodules_lock, flags);
4475 - if(ioc3_ethernet && idd->active[ioc3_ethernet->id]
4476 - && ioc3_ethernet->intr)
4477 - handled = handled && !ioc3_ethernet->intr(ioc3_ethernet, idd, 0);
4478 - read_unlock_irqrestore(&ioc3_submodules_lock, flags);
4479 - return handled?IRQ_HANDLED:IRQ_NONE;
4480 -}
4481 -
4482 -void ioc3_enable(struct ioc3_submodule *is,
4483 - struct ioc3_driver_data *idd, unsigned int irqs)
4484 -{
4485 - write_ireg(idd, irqs & is->irq_mask, IOC3_W_IES);
4486 -}
4487 -
4488 -void ioc3_ack(struct ioc3_submodule *is, struct ioc3_driver_data *idd,
4489 - unsigned int irqs)
4490 -{
4491 - writel(irqs & is->irq_mask, &idd->vma->sio_ir);
4492 -}
4493 -
4494 -void ioc3_disable(struct ioc3_submodule *is,
4495 - struct ioc3_driver_data *idd, unsigned int irqs)
4496 -{
4497 - write_ireg(idd, irqs & is->irq_mask, IOC3_W_IEC);
4498 -}
4499 -
4500 -void ioc3_gpcr_set(struct ioc3_driver_data *idd, unsigned int val)
4501 -{
4502 - unsigned long flags;
4503 - spin_lock_irqsave(&idd->gpio_lock, flags);
4504 - writel(val, &idd->vma->gpcr_s);
4505 - spin_unlock_irqrestore(&idd->gpio_lock, flags);
4506 -}
4507 -
4508 -/* Keep it simple, stupid! */
4509 -static int find_slot(void **tab, int max)
4510 -{
4511 - int i;
4512 - for(i=0;i<max;i++)
4513 - if(!(tab[i]))
4514 - return i;
4515 - return -1;
4516 -}
4517 -
4518 -/* Register an IOC3 submodule */
4519 -int ioc3_register_submodule(struct ioc3_submodule *is)
4520 -{
4521 - struct ioc3_driver_data *idd;
4522 - int alloc_id;
4523 - unsigned long flags;
4524 -
4525 - write_lock_irqsave(&ioc3_submodules_lock, flags);
4526 - alloc_id = find_slot((void **)ioc3_submodules, IOC3_MAX_SUBMODULES);
4527 - if(alloc_id != -1) {
4528 - ioc3_submodules[alloc_id] = is;
4529 - if(is->ethernet) {
4530 - if(ioc3_ethernet==NULL)
4531 - ioc3_ethernet=is;
4532 - else
4533 - printk(KERN_WARNING
4534 - "IOC3 Ethernet module already registered!\n");
4535 - }
4536 - }
4537 - write_unlock_irqrestore(&ioc3_submodules_lock, flags);
4538 -
4539 - if(alloc_id == -1) {
4540 - printk(KERN_WARNING "Increase IOC3_MAX_SUBMODULES!\n");
4541 - return -ENOMEM;
4542 - }
4543 -
4544 - is->id=alloc_id;
4545 -
4546 - /* Initialize submodule for each IOC3 */
4547 - if (!is->probe)
4548 - return 0;
4549 -
4550 - down_read(&ioc3_devices_rwsem);
4551 - list_for_each_entry(idd, &ioc3_devices, list) {
4552 - /* set to 1 for IRQs in probe */
4553 - idd->active[alloc_id] = 1;
4554 - idd->active[alloc_id] = !is->probe(is, idd);
4555 - }
4556 - up_read(&ioc3_devices_rwsem);
4557 -
4558 - return 0;
4559 -}
4560 -
4561 -/* Unregister an IOC3 submodule */
4562 -void ioc3_unregister_submodule(struct ioc3_submodule *is)
4563 -{
4564 - struct ioc3_driver_data *idd;
4565 - unsigned long flags;
4566 -
4567 - write_lock_irqsave(&ioc3_submodules_lock, flags);
4568 - if(ioc3_submodules[is->id]==is)
4569 - ioc3_submodules[is->id]=NULL;
4570 - else
4571 - printk(KERN_WARNING
4572 - "IOC3 submodule %s has wrong ID.\n",is->name);
4573 - if(ioc3_ethernet==is)
4574 - ioc3_ethernet = NULL;
4575 - write_unlock_irqrestore(&ioc3_submodules_lock, flags);
4576 -
4577 - /* Remove submodule for each IOC3 */
4578 - down_read(&ioc3_devices_rwsem);
4579 - list_for_each_entry(idd, &ioc3_devices, list)
4580 - if(idd->active[is->id]) {
4581 - if(is->remove)
4582 - if(is->remove(is, idd))
4583 - printk(KERN_WARNING
4584 - "%s: IOC3 submodule %s remove failed "
4585 - "for pci_dev %s.\n",
4586 - __func__, module_name(is->owner),
4587 - pci_name(idd->pdev));
4588 - idd->active[is->id] = 0;
4589 - if(is->irq_mask)
4590 - write_ireg(idd, is->irq_mask, IOC3_W_IEC);
4591 - }
4592 - up_read(&ioc3_devices_rwsem);
4593 -}
4594 -
4595 -/*********************
4596 - * Device management *
4597 - *********************/
4598 -
4599 -static char *ioc3_class_names[] = { "unknown", "IP27 BaseIO", "IP30 system",
4600 - "MENET 1/2/3", "MENET 4", "CADduo", "Altix Serial" };
4601 -
4602 -static int ioc3_class(struct ioc3_driver_data *idd)
4603 -{
4604 - int res = IOC3_CLASS_NONE;
4605 - /* NIC-based logic */
4606 - if(!strncmp(idd->nic_part, "030-0891-", 9))
4607 - res = IOC3_CLASS_BASE_IP30;
4608 - if(!strncmp(idd->nic_part, "030-1155-", 9))
4609 - res = IOC3_CLASS_CADDUO;
4610 - if(!strncmp(idd->nic_part, "030-1657-", 9))
4611 - res = IOC3_CLASS_SERIAL;
4612 - if(!strncmp(idd->nic_part, "030-1664-", 9))
4613 - res = IOC3_CLASS_SERIAL;
4614 - /* total random heuristics */
4615 -#ifdef CONFIG_SGI_IP27
4616 - if(!idd->nic_part[0])
4617 - res = IOC3_CLASS_BASE_IP27;
4618 -#endif
4619 - /* print educational message */
4620 - printk(KERN_INFO "IOC3 part: [%s], serial: [%s] => class %s\n",
4621 - idd->nic_part, idd->nic_serial, ioc3_class_names[res]);
4622 - return res;
4623 -}
4624 -/* Adds a new instance of an IOC3 card */
4625 -static int ioc3_probe(struct pci_dev *pdev, const struct pci_device_id *pci_id)
4626 -{
4627 - struct ioc3_driver_data *idd;
4628 - uint32_t pcmd;
4629 - int ret, id;
4630 -
4631 - /* Enable IOC3 and take ownership of it */
4632 - if ((ret = pci_enable_device(pdev))) {
4633 - printk(KERN_WARNING
4634 - "%s: Failed to enable IOC3 device for pci_dev %s.\n",
4635 - __func__, pci_name(pdev));
4636 - goto out;
4637 - }
4638 - pci_set_master(pdev);
4639 -
4640 -#ifdef USE_64BIT_DMA
4641 - ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
4642 - if (!ret) {
4643 - ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4644 - if (ret < 0) {
4645 - printk(KERN_WARNING "%s: Unable to obtain 64 bit DMA "
4646 - "for consistent allocations\n",
4647 - __func__);
4648 - }
4649 - }
4650 -#endif
4651 -
4652 - /* Set up per-IOC3 data */
4653 - idd = kzalloc(sizeof(struct ioc3_driver_data), GFP_KERNEL);
4654 - if (!idd) {
4655 - printk(KERN_WARNING
4656 - "%s: Failed to allocate IOC3 data for pci_dev %s.\n",
4657 - __func__, pci_name(pdev));
4658 - ret = -ENODEV;
4659 - goto out_idd;
4660 - }
4661 - spin_lock_init(&idd->ir_lock);
4662 - spin_lock_init(&idd->gpio_lock);
4663 - idd->pdev = pdev;
4664 -
4665 - /* Map all IOC3 registers. These are shared between subdevices
4666 - * so the main IOC3 module manages them.
4667 - */
4668 - idd->pma = pci_resource_start(pdev, 0);
4669 - if (!idd->pma) {
4670 - printk(KERN_WARNING
4671 - "%s: Unable to find IOC3 resource "
4672 - "for pci_dev %s.\n",
4673 - __func__, pci_name(pdev));
4674 - ret = -ENODEV;
4675 - goto out_pci;
4676 - }
4677 - if (!request_mem_region(idd->pma, IOC3_PCI_SIZE, "ioc3")) {
4678 - printk(KERN_WARNING
4679 - "%s: Unable to request IOC3 region "
4680 - "for pci_dev %s.\n",
4681 - __func__, pci_name(pdev));
4682 - ret = -ENODEV;
4683 - goto out_pci;
4684 - }
4685 - idd->vma = ioremap(idd->pma, IOC3_PCI_SIZE);
4686 - if (!idd->vma) {
4687 - printk(KERN_WARNING
4688 - "%s: Unable to remap IOC3 region "
4689 - "for pci_dev %s.\n",
4690 - __func__, pci_name(pdev));
4691 - ret = -ENODEV;
4692 - goto out_misc_region;
4693 - }
4694 -
4695 - /* Track PCI-device specific data */
4696 - pci_set_drvdata(pdev, idd);
4697 - down_write(&ioc3_devices_rwsem);
4698 - list_add_tail(&idd->list, &ioc3_devices);
4699 - idd->id = ioc3_counter++;
4700 - up_write(&ioc3_devices_rwsem);
4701 -
4702 - idd->gpdr_shadow = readl(&idd->vma->gpdr);
4703 -
4704 - /* Read IOC3 NIC contents */
4705 - probe_nic(idd);
4706 -
4707 - /* Detect IOC3 class */
4708 - idd->class = ioc3_class(idd);
4709 -
4710 - /* Initialize IOC3 */
4711 - pci_read_config_dword(pdev, PCI_COMMAND, &pcmd);
4712 - pci_write_config_dword(pdev, PCI_COMMAND,
4713 - pcmd | PCI_COMMAND_MEMORY |
4714 - PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
4715 - PCI_SCR_DROP_MODE_EN);
4716 -
4717 - write_ireg(idd, ~0, IOC3_W_IEC);
4718 - writel(~0, &idd->vma->sio_ir);
4719 -
4720 - /* Set up IRQs */
4721 - if(idd->class == IOC3_CLASS_BASE_IP30
4722 - || idd->class == IOC3_CLASS_BASE_IP27) {
4723 - writel(0, &idd->vma->eier);
4724 - writel(~0, &idd->vma->eisr);
4725 -
4726 - idd->dual_irq = 1;
4727 - if (!request_irq(pdev->irq, ioc3_intr_eth, IRQF_SHARED,
4728 - "ioc3-eth", (void *)idd)) {
4729 - idd->irq_eth = pdev->irq;
4730 - } else {
4731 - printk(KERN_WARNING
4732 - "%s : request_irq fails for IRQ 0x%x\n ",
4733 - __func__, pdev->irq);
4734 - }
4735 - if (!request_irq(pdev->irq+2, ioc3_intr_io, IRQF_SHARED,
4736 - "ioc3-io", (void *)idd)) {
4737 - idd->irq_io = pdev->irq+2;
4738 - } else {
4739 - printk(KERN_WARNING
4740 - "%s : request_irq fails for IRQ 0x%x\n ",
4741 - __func__, pdev->irq+2);
4742 - }
4743 - } else {
4744 - if (!request_irq(pdev->irq, ioc3_intr_io, IRQF_SHARED,
4745 - "ioc3", (void *)idd)) {
4746 - idd->irq_io = pdev->irq;
4747 - } else {
4748 - printk(KERN_WARNING
4749 - "%s : request_irq fails for IRQ 0x%x\n ",
4750 - __func__, pdev->irq);
4751 - }
4752 - }
4753 -
4754 - /* Add this IOC3 to all submodules */
4755 - for(id=0;id<IOC3_MAX_SUBMODULES;id++)
4756 - if(ioc3_submodules[id] && ioc3_submodules[id]->probe) {
4757 - idd->active[id] = 1;
4758 - idd->active[id] = !ioc3_submodules[id]->probe
4759 - (ioc3_submodules[id], idd);
4760 - }
4761 -
4762 - printk(KERN_INFO "IOC3 Master Driver loaded for %s\n", pci_name(pdev));
4763 -
4764 - return 0;
4765 -
4766 -out_misc_region:
4767 - release_mem_region(idd->pma, IOC3_PCI_SIZE);
4768 -out_pci:
4769 - kfree(idd);
4770 -out_idd:
4771 - pci_disable_device(pdev);
4772 -out:
4773 - return ret;
4774 -}
4775 -
4776 -/* Removes a particular instance of an IOC3 card. */
4777 -static void ioc3_remove(struct pci_dev *pdev)
4778 -{
4779 - int id;
4780 - struct ioc3_driver_data *idd;
4781 -
4782 - idd = pci_get_drvdata(pdev);
4783 -
4784 - /* Remove this IOC3 from all submodules */
4785 - for(id=0;id<IOC3_MAX_SUBMODULES;id++)
4786 - if(idd->active[id]) {
4787 - if(ioc3_submodules[id] && ioc3_submodules[id]->remove)
4788 - if(ioc3_submodules[id]->remove(ioc3_submodules[id],
4789 - idd))
4790 - printk(KERN_WARNING
4791 - "%s: IOC3 submodule 0x%s remove failed "
4792 - "for pci_dev %s.\n",
4793 - __func__,
4794 - module_name(ioc3_submodules[id]->owner),
4795 - pci_name(pdev));
4796 - idd->active[id] = 0;
4797 - }
4798 -
4799 - /* Clear and disable all IRQs */
4800 - write_ireg(idd, ~0, IOC3_W_IEC);
4801 - writel(~0, &idd->vma->sio_ir);
4802 -
4803 - /* Release resources */
4804 - free_irq(idd->irq_io, (void *)idd);
4805 - if(idd->dual_irq)
4806 - free_irq(idd->irq_eth, (void *)idd);
4807 - iounmap(idd->vma);
4808 - release_mem_region(idd->pma, IOC3_PCI_SIZE);
4809 -
4810 - /* Disable IOC3 and relinquish */
4811 - pci_disable_device(pdev);
4812 -
4813 - /* Remove and free driver data */
4814 - down_write(&ioc3_devices_rwsem);
4815 - list_del(&idd->list);
4816 - up_write(&ioc3_devices_rwsem);
4817 - kfree(idd);
4818 -}
4819 -
4820 -static struct pci_device_id ioc3_id_table[] = {
4821 - {PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, PCI_ANY_ID, PCI_ANY_ID},
4822 - {0}
4823 -};
4824 -
4825 -static struct pci_driver ioc3_driver = {
4826 - .name = "IOC3",
4827 - .id_table = ioc3_id_table,
4828 - .probe = ioc3_probe,
4829 - .remove = ioc3_remove,
4830 -};
4831 -
4832 -MODULE_DEVICE_TABLE(pci, ioc3_id_table);
4833 -
4834 -/*********************
4835 - * Module management *
4836 - *********************/
4837 -
4838 -/* Module load */
4839 -static int __init ioc3_init(void)
4840 -{
4841 - if (ia64_platform_is("sn2"))
4842 - return pci_register_driver(&ioc3_driver);
4843 - return -ENODEV;
4844 -}
4845 -
4846 -/* Module unload */
4847 -static void __exit ioc3_exit(void)
4848 -{
4849 - pci_unregister_driver(&ioc3_driver);
4850 -}
4851 -
4852 -module_init(ioc3_init);
4853 -module_exit(ioc3_exit);
4854 -
4855 -MODULE_AUTHOR("Stanislaw Skowronek <skylark@linux-mips.org>");
4856 -MODULE_DESCRIPTION("PCI driver for SGI IOC3");
4857 -MODULE_LICENSE("GPL");
4858 -
4859 -EXPORT_SYMBOL_GPL(ioc3_register_submodule);
4860 -EXPORT_SYMBOL_GPL(ioc3_unregister_submodule);
4861 -EXPORT_SYMBOL_GPL(ioc3_ack);
4862 -EXPORT_SYMBOL_GPL(ioc3_gpcr_set);
4863 -EXPORT_SYMBOL_GPL(ioc3_disable);
4864 -EXPORT_SYMBOL_GPL(ioc3_enable);
4865 diff --git a/drivers/tty/serial/8250/8250_ioc3.c b/drivers/tty/serial/8250/8250_ioc3.c
4866 new file mode 100644
4867 index 000000000000..df86a9941f25
4868 --- /dev/null
4869 +++ b/drivers/tty/serial/8250/8250_ioc3.c
4870 @@ -0,0 +1,128 @@
4871 +/*
4872 + * SGI IOC3 bridge for UARTs
4873 + *
4874 + * Copyright (C) 2005 Stanislaw Skowronek <skylark@unaligned.org>
4875 + * Copyright (C) 2014 Joshua Kinard <kumba@gentoo.org>
4876 + */
4877 +#include <linux/module.h>
4878 +#include <linux/init.h>
4879 +#include <linux/serio.h>
4880 +#include <linux/errno.h>
4881 +#include <linux/interrupt.h>
4882 +#include <linux/io.h>
4883 +#include <linux/ioport.h>
4884 +#include <linux/delay.h>
4885 +#include <linux/device.h>
4886 +#include <linux/slab.h>
4887 +#include <linux/spinlock.h>
4888 +#include <linux/err.h>
4889 +#include <linux/pci.h>
4890 +
4891 +#include <asm/irq.h>
4892 +#include <linux/ioc3.h>
4893 +
4894 +#include <linux/serial.h>
4895 +#include <asm/serial.h>
4896 +
4897 +#include "8250.h"
4898 +
4899 +#define IOC3_UARTCLK (22000000 / 3)
4900 +
4901 +struct ioc3uart_data {
4902 + int line_a, line_b;
4903 + int irq;
4904 +};
4905 +
4906 +static int
4907 +serial8250_ioc3_probe(struct ioc3_submodule *is, struct ioc3_driver_data *idd)
4908 +{
4909 + struct uart_8250_port up;
4910 + struct ioc3uart_data *d;
4911 +
4912 + /* Check for UART-less add-on boards */
4913 + if (idd->class == IOC3_CLASS_MENET_4 ||
4914 + idd->class == IOC3_CLASS_CADDUO)
4915 + return 1;
4916 +
4917 + /* Set PIO mode for SuperIO UARTs. */
4918 + ioc3_gpcr_set(idd, (GPCR_UARTA_MODESEL | GPCR_UARTB_MODESEL));
4919 + idd->vma->gppr[6] = 0;
4920 + idd->vma->gppr[7] = 0;
4921 + udelay(1000);
4922 + idd->vma->port_a.sscr &= ~(SSCR_DMA_EN);
4923 + idd->vma->port_b.sscr &= ~(SSCR_DMA_EN);
4924 + udelay(1000);
4925 +
4926 + /* Disable all SA/B interrupts except for SA/B_INT in SIO_IEC. */
4927 + idd->vma->sio_iec = (SIO_IR_SA_TX_MT | SIO_IR_SB_TX_MT |
4928 + SIO_IR_SA_RX_FULL | SIO_IR_SB_RX_FULL |
4929 + SIO_IR_SA_RX_HIGH | SIO_IR_SB_RX_HIGH |
4930 + SIO_IR_SA_RX_TIMER | SIO_IR_SB_RX_TIMER |
4931 + SIO_IR_SA_DELTA_DCD | SIO_IR_SB_DELTA_DCD |
4932 + SIO_IR_SA_DELTA_CTS | SIO_IR_SB_DELTA_CTS |
4933 + SIO_IR_SA_TX_EXPLICIT | SIO_IR_SB_TX_EXPLICIT |
4934 + SIO_IR_SA_MEMERR | SIO_IR_SB_MEMERR);
4935 + idd->vma->sio_ies = (SIO_IR_SA_INT | SIO_IR_SB_INT);
4936 + udelay(1000);
4937 +
4938 + idd->vma->sregs.uarta.iu_fcr = 0;
4939 + idd->vma->sregs.uartb.iu_fcr = 0;
4940 + udelay(1000);
4941 +
4942 + /* Assign IRQ0 to cause 8250_core.c to use a timer to poll the port */
4943 + d = devm_kzalloc(&idd->pdev->dev, sizeof(struct ioc3uart_data),
4944 + GFP_KERNEL);
4945 + d->irq = 0;
4946 + idd->data[is->id] = d;
4947 +
4948 + /* Register serial ports with 8250.c */
4949 + memset(&up, 0, sizeof(struct uart_8250_port));
4950 + up.port.iotype = UPIO_IOC3;
4951 + up.port.uartclk = IOC3_UARTCLK;
4952 + up.port.type = PORT_16550A;
4953 + up.port.irq = d->irq;
4954 + up.port.flags = (UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ);
4955 + up.port.regshift = 0;
4956 + up.port.dev = &idd->pdev->dev;
4957 +
4958 + up.port.membase = (unsigned char *)&idd->vma->sregs.uarta;
4959 + up.port.mapbase = (((unsigned long)up.port.membase) & 0xffffffffff);
4960 + d->line_a = serial8250_register_8250_port(&up);
4961 +
4962 + up.port.membase = (unsigned char *)&idd->vma->sregs.uartb;
4963 + up.port.mapbase = (((unsigned long)up.port.membase) & 0xffffffffff);
4964 + d->line_b = serial8250_register_8250_port(&up);
4965 +
4966 + ioc3_enable(is, idd, is->irq_mask);
4967 + return 0;
4968 +}
4969 +
4970 +static int
4971 +serial8250_ioc3_remove(struct ioc3_submodule *is, struct ioc3_driver_data *idd)
4972 +{
4973 + struct ioc3uart_data *d = (struct ioc3uart_data *)(idd->data[is->id]);
4974 +
4975 + ioc3_disable(is, idd, is->irq_mask);
4976 + serial8250_unregister_port(d->line_a);
4977 + serial8250_unregister_port(d->line_b);
4978 + idd->data[is->id] = NULL;
4979 + return 0;
4980 +}
4981 +
4982 +static struct
4983 +ioc3_submodule ioc3uart_submodule = {
4984 + .name = "uart",
4985 + .probe = serial8250_ioc3_probe,
4986 + .remove = serial8250_ioc3_remove,
4987 + .irq_mask = SIO_IR_SA_INT | SIO_IR_SB_INT,
4988 + .reset_mask = 1,
4989 + .owner = THIS_MODULE,
4990 +};
4991 +
4992 +ioc3_submodule_driver(ioc3uart_submodule);
4993 +
4994 +MODULE_AUTHOR("Stanislaw Skowronek <skylark@unaligned.org>");
4995 +MODULE_AUTHOR("Joshua Kinard <kumba@gentoo.org>");
4996 +MODULE_DESCRIPTION("SGI IOC3 8250 UART driver");
4997 +MODULE_LICENSE("GPL");
4998 +MODULE_VERSION("0.42.1");
4999 diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
5000 index cf541aab2bd0..a83e8370a754 100644
5001 --- a/drivers/tty/serial/8250/8250_port.c
5002 +++ b/drivers/tty/serial/8250/8250_port.c
5003 @@ -382,6 +382,20 @@ static void au_serial_dl_write(struct uart_8250_port *up, int value)
5005 #endif
5007 +#if defined(CONFIG_SGI_IOC3) || defined(CONFIG_SERIAL_8250_IOC3)
5008 +static unsigned int ioc3_serial_in(struct uart_port *p, int offset)
5009 +{
5010 + offset = offset << p->regshift;
5011 + return readb(p->membase + (offset ^ 3));
5012 +}
5013 +
5014 +static void ioc3_serial_out(struct uart_port *p, int offset, int value)
5015 +{
5016 + offset = offset << p->regshift;
5017 + writeb(value, p->membase + (offset ^ 3));
5018 +}
5019 +#endif
5020 +
5021 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
5022 {
5023 offset = offset << p->regshift;
5024 @@ -500,6 +514,13 @@ static void set_io_from_upio(struct uart_port *p)
5025 break;
5026 #endif
5028 +#if defined(CONFIG_SGI_IOC3) || defined(CONFIG_SERIAL_8250_IOC3)
5029 + case UPIO_IOC3:
5030 + p->serial_in = ioc3_serial_in;
5031 + p->serial_out = ioc3_serial_out;
5032 + break;
5033 +#endif
5034 +
5035 default:
5036 p->serial_in = io_serial_in;
5037 p->serial_out = io_serial_out;
5038 @@ -519,6 +540,7 @@ serial_port_out_sync(struct uart_port *p, int offset, int value)
5039 case UPIO_MEM32:
5040 case UPIO_MEM32BE:
5041 case UPIO_AU:
5042 + case UPIO_IOC3:
5043 p->serial_out(p, offset, value);
5044 p->serial_in(p, UART_LCR); /* safe, no side-effects */
5045 break;
5046 @@ -2865,6 +2887,8 @@ static int serial8250_request_std_resource(struct uart_8250_port *up)
5047 if (!request_region(port->iobase, size, "serial"))
5048 ret = -EBUSY;
5049 break;
5050 + case UPIO_IOC3:
5051 + break;
5052 }
5053 return ret;
5054 }
5055 @@ -2896,6 +2920,8 @@ static void serial8250_release_std_resource(struct uart_8250_port *up)
5056 case UPIO_PORT:
5057 release_region(port->iobase, size);
5058 break;
5059 + case UPIO_IOC3:
5060 + break;
5061 }
5062 }
5064 diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig
5065 index f005eaf8bc57..acf9b223fb12 100644
5066 --- a/drivers/tty/serial/8250/Kconfig
5067 +++ b/drivers/tty/serial/8250/Kconfig
5068 @@ -364,6 +364,17 @@ config SERIAL_8250_EM
5069 port hardware found on the Emma Mobile line of processors.
5070 If unsure, say N.
5072 +config SERIAL_8250_IOC3
5073 + tristate "SGI IOC3 8250 UART support"
5074 + depends on SGI_IOC3 && SERIAL_8250
5075 + select SERIAL_8250_EXTENDED
5076 + select SERIAL_8250_SHARE_IRQ
5077 + help
5078 + Enable this if you have a SGI Origin or Octane machine. This module
5079 + provides basic serial support by directly driving the UART chip
5080 + behind the IOC3 device on those systems. Maximum baud speed is
5081 + 38400bps using this driver.
5082 +
5083 config SERIAL_8250_RT288X
5084 bool "Ralink RT288x/RT305x/RT3662/RT3883 serial port support"
5085 depends on SERIAL_8250
5086 diff --git a/drivers/tty/serial/8250/Makefile b/drivers/tty/serial/8250/Makefile
5087 index 18751bc63a84..79f74b4d57e5 100644
5088 --- a/drivers/tty/serial/8250/Makefile
5089 +++ b/drivers/tty/serial/8250/Makefile
5090 @@ -27,6 +27,7 @@ obj-$(CONFIG_SERIAL_8250_FSL) += 8250_fsl.o
5091 obj-$(CONFIG_SERIAL_8250_MEN_MCB) += 8250_men_mcb.o
5092 obj-$(CONFIG_SERIAL_8250_DW) += 8250_dw.o
5093 obj-$(CONFIG_SERIAL_8250_EM) += 8250_em.o
5094 +obj-$(CONFIG_SERIAL_8250_IOC3) += 8250_ioc3.o
5095 obj-$(CONFIG_SERIAL_8250_OMAP) += 8250_omap.o
5096 obj-$(CONFIG_SERIAL_8250_LPC18XX) += 8250_lpc18xx.o
5097 obj-$(CONFIG_SERIAL_8250_MT6577) += 8250_mtk.o
5098 diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
5099 index df8bd0c7b97d..ca583af9ed53 100644
5100 --- a/drivers/tty/serial/Kconfig
5101 +++ b/drivers/tty/serial/Kconfig
5102 @@ -971,8 +971,8 @@ config SERIAL_SGI_IOC4
5103 Otherwise, say N.
5105 config SERIAL_SGI_IOC3
5106 - tristate "SGI Altix IOC3 serial support"
5107 - depends on (IA64_GENERIC || IA64_SGI_SN2) && SGI_IOC3
5108 + tristate "SGI IOC3 serial support"
5109 + depends on SGI_IOC3
5110 select SERIAL_CORE
5111 help
5112 If you have an SGI Altix with an IOC3 serial card,
5113 diff --git a/drivers/tty/serial/ioc3_serial.c b/drivers/tty/serial/ioc3_serial.c
5114 index d8a1cdd6a53d..51e26c6017d6 100644
5115 --- a/drivers/tty/serial/ioc3_serial.c
5116 +++ b/drivers/tty/serial/ioc3_serial.c
5117 @@ -20,6 +20,9 @@
5118 #include <linux/ioc3.h>
5119 #include <linux/slab.h>
5121 +#include <asm/pci/bridge.h>
5122 +#include <asm/sgi/ioc3.h>
5123 +
5124 /*
5125 * Interesting things about the ioc3
5126 */
5127 @@ -33,7 +36,6 @@
5128 /* determine given the sio_ir what port it applies to */
5129 #define GET_PORT_FROM_SIO_IR(_x) (_x & SIO_IR_SA) ? 0 : 1
5131 -
5132 /*
5133 * we have 2 logical ports (rs232, rs422) for each physical port
5134 * evens are rs232, odds are rs422
5135 @@ -47,15 +49,20 @@ static unsigned int Num_of_ioc3_cards;
5136 static unsigned int Submodule_slot;
5138 /* defining this will get you LOTS of great debug info */
5139 -//#define DEBUG_INTERRUPTS
5140 -#define DPRINT_CONFIG(_x...) ;
5141 -//#define DPRINT_CONFIG(_x...) printk _x
5142 -#define NOT_PROGRESS() ;
5143 -//#define NOT_PROGRESS() printk("%s : fails %d\n", __func__, __LINE__)
5144 +#undef DEBUG_INTERRUPTS
5145 +#define DEBUG 1
5146 +#if DEBUG
5147 +#define DPRINT_CONFIG(_x...) (printk _x)
5148 +#define NOT_PROGRESS() \
5149 + (printk(KERN_DEBUG "%s : fails %d\n", __func__, __LINE__))
5150 +#else
5151 +#define DPRINT_CONFIG(_x...)
5152 +#define NOT_PROGRESS()
5153 +#endif
5155 /* number of characters we want to transmit to the lower level at a time */
5156 #define MAX_CHARS 256
5157 -#define FIFO_SIZE (MAX_CHARS-1) /* it's a uchar */
5158 +#define FIFO_SIZE (MAX_CHARS - 1) /* it's a uchar */
5160 /* Device name we're using */
5161 #define DEVICE_NAME "ttySIOC"
5162 @@ -116,6 +123,18 @@ static unsigned int Submodule_slot;
5164 #define TOTAL_RING_BUF_SIZE (RING_BUF_SIZE * 4)
5166 +
5167 +static unsigned long ioc3_map(void *ptr, unsigned long dma_attr)
5168 +{
5169 +#if defined(CONFIG_SGI_IP27)
5170 + return (0xaUL << PCI64_ATTR_TARG_SHFT) | dma_attr |
5171 + ((unsigned long)ptr & TO_PHYS_MASK);
5172 +#else
5173 + return virt_to_bus(ptr);
5174 +#endif
5175 +}
5176 +
5177 +
5178 /* driver specific - one per card */
5179 struct ioc3_card {
5180 struct {
5181 @@ -298,17 +317,17 @@ struct ring_buffer {
5184 /**
5185 - * set_baud - Baud rate setting code
5186 + * ioc3_set_baud - Baud rate setting code
5187 * @port: port to set
5188 * @baud: baud rate to use
5189 */
5190 -static int set_baud(struct ioc3_port *port, int baud)
5191 +static int ioc3_set_baud(struct ioc3_port *port, int baud)
5192 {
5193 + struct ioc3_uartregs __iomem *uart;
5194 int divisor;
5195 int actual_baud;
5196 int diff;
5197 int lcr, prediv;
5198 - struct ioc3_uartregs __iomem *uart;
5200 for (prediv = 6; prediv < 64; prediv++) {
5201 divisor = SER_DIVISOR(baud, SER_CLK_SPEED(prediv));
5202 @@ -346,10 +365,10 @@ static int set_baud(struct ioc3_port *port, int baud)
5203 }
5205 /**
5206 - * get_ioc3_port - given a uart port, return the control structure
5207 + * ioc3_get_ioc3port - given a uart port, return the control structure
5208 * @the_port: uart port to find
5209 */
5210 -static struct ioc3_port *get_ioc3_port(struct uart_port *the_port)
5211 +static struct ioc3_port *ioc3_get_ioc3port(struct uart_port *the_port)
5212 {
5213 struct ioc3_driver_data *idd = dev_get_drvdata(the_port->dev);
5214 struct ioc3_card *card_ptr = idd->data[Submodule_slot];
5215 @@ -370,17 +389,17 @@ static struct ioc3_port *get_ioc3_port(struct uart_port *the_port)
5216 }
5218 /**
5219 - * port_init - Initialize the sio and ioc3 hardware for a given port
5220 + * ioc3_port_init - Initialize the sio and ioc3 hardware for a given port
5221 * called per port from attach...
5222 * @port: port to initialize
5223 */
5224 -static inline int port_init(struct ioc3_port *port)
5225 +static inline int ioc3_port_init(struct ioc3_port *port)
5226 {
5227 - uint32_t sio_cr;
5228 struct port_hooks *hooks = port->ip_hooks;
5229 + struct ioc3_driver_data *idd = port->ip_idd;
5230 struct ioc3_uartregs __iomem *uart;
5231 int reset_loop_counter = 0xfffff;
5232 - struct ioc3_driver_data *idd = port->ip_idd;
5233 + uint32_t sio_cr;
5235 /* Idle the IOC3 serial interface */
5236 writel(SSCR_RESET, &port->ip_serial_regs->sscr);
5237 @@ -417,7 +436,7 @@ static inline int port_init(struct ioc3_port *port)
5238 writeb(0, &uart->iu_ier);
5240 /* Set the default baud */
5241 - set_baud(port, port->ip_baud);
5242 + ioc3_set_baud(port, port->ip_baud);
5244 /* Set line control to 8 bits no parity */
5245 writeb(UART_LCR_WLEN8 | 0, &uart->iu_lcr);
5246 @@ -442,7 +461,8 @@ static inline int port_init(struct ioc3_port *port)
5248 sbbr_l = &idd->vma->sbbr_l;
5249 sbbr_h = &idd->vma->sbbr_h;
5250 - ring_pci_addr = (unsigned long __iomem)port->ip_dma_ringbuf;
5251 + /* XXX: Below line needs work to function on MIPS. */
5252 + ring_pci_addr = ioc3_map(&port->ip_dma_ringbuf, PCI64_ATTR_BAR);
5253 DPRINT_CONFIG(("%s: ring_pci_addr 0x%p\n",
5254 __func__, (void *)ring_pci_addr));
5256 @@ -474,11 +494,11 @@ static inline int port_init(struct ioc3_port *port)
5257 }
5259 /**
5260 - * enable_intrs - enable interrupts
5261 + * ioc3_uart_enable_intrs - enable interrupts
5262 * @port: port to enable
5263 * @mask: mask to use
5264 */
5265 -static void enable_intrs(struct ioc3_port *port, uint32_t mask)
5266 +static void ioc3_uart_enable_intrs(struct ioc3_port *port, uint32_t mask)
5267 {
5268 if ((port->ip_card->ic_enable & mask) != mask) {
5269 port->ip_card->ic_enable |= mask;
5270 @@ -487,10 +507,10 @@ static void enable_intrs(struct ioc3_port *port, uint32_t mask)
5271 }
5273 /**
5274 - * local_open - local open a port
5275 + * ioc3_local_open - local open a port
5276 * @port: port to open
5277 */
5278 -static inline int local_open(struct ioc3_port *port)
5279 +static int ioc3_local_open(struct ioc3_port *port)
5280 {
5281 int spiniter = 0;
5283 @@ -536,11 +556,11 @@ static inline int local_open(struct ioc3_port *port)
5284 }
5286 /**
5287 - * set_rx_timeout - Set rx timeout and threshold values.
5288 + * ioc3_set_rx_timeout - Set rx timeout and threshold values.
5289 * @port: port to use
5290 * @timeout: timeout value in ticks
5291 */
5292 -static inline int set_rx_timeout(struct ioc3_port *port, int timeout)
5293 +static int ioc3_set_rx_timeout(struct ioc3_port *port, int timeout)
5294 {
5295 int threshold;
5297 @@ -575,7 +595,7 @@ static inline int set_rx_timeout(struct ioc3_port *port, int timeout)
5298 }
5300 /**
5301 - * config_port - config the hardware
5302 + * ioc3_config_port - config the hardware
5303 * @port: port to config
5304 * @baud: baud rate for the port
5305 * @byte_size: data size
5306 @@ -583,19 +603,18 @@ static inline int set_rx_timeout(struct ioc3_port *port, int timeout)
5307 * @parenb: parity enable ?
5308 * @parodd: odd parity ?
5309 */
5310 -static inline int
5311 -config_port(struct ioc3_port *port,
5312 - int baud, int byte_size, int stop_bits, int parenb, int parodd)
5313 +static int ioc3_config_port(struct ioc3_port *port, int baud, int byte_size,
5314 + int stop_bits, int parenb, int parodd)
5315 {
5316 - char lcr, sizebits;
5317 int spiniter = 0;
5318 + char lcr, sizebits;
5320 DPRINT_CONFIG(("%s: line %d baud %d byte_size %d stop %d parenb %d "
5321 "parodd %d\n",
5322 __func__, ((struct uart_port *)port->ip_port)->line,
5323 baud, byte_size, stop_bits, parenb, parodd));
5325 - if (set_baud(port, baud))
5326 + if (ioc3_set_baud(port, baud))
5327 return 1;
5329 switch (byte_size) {
5330 @@ -662,23 +681,23 @@ config_port(struct ioc3_port *port,
5331 if (port->ip_tx_lowat == 0)
5332 port->ip_tx_lowat = 1;
5334 - set_rx_timeout(port, 2);
5335 + ioc3_set_rx_timeout(port, 2);
5336 return 0;
5337 }
5339 /**
5340 - * do_write - Write bytes to the port. Returns the number of bytes
5341 - * actually written. Called from transmit_chars
5342 + * ioc3_do_write - Write bytes to the port. Returns the number of bytes
5343 + * actually written. Called from ioc3_transmit_chars
5344 * @port: port to use
5345 * @buf: the stuff to write
5346 * @len: how many bytes in 'buf'
5347 */
5348 -static inline int do_write(struct ioc3_port *port, char *buf, int len)
5349 +static int ioc3_do_write(struct ioc3_port *port, char *buf, int len)
5350 {
5351 - int prod_ptr, cons_ptr, total = 0;
5352 - struct ring *outring;
5353 struct ring_entry *entry;
5354 struct port_hooks *hooks = port->ip_hooks;
5355 + struct ring *outring;
5356 + int prod_ptr, cons_ptr, total = 0;
5358 BUG_ON(!(len >= 0));
5360 @@ -744,7 +763,7 @@ static inline int do_write(struct ioc3_port *port, char *buf, int len)
5361 * can disable DMA if necessary when the tx finishes.
5362 */
5363 if (total > 0)
5364 - enable_intrs(port, hooks->intr_tx_mt);
5365 + ioc3_uart_enable_intrs(port, hooks->intr_tx_mt);
5366 }
5367 port->ip_tx_prod = prod_ptr;
5369 @@ -752,11 +771,11 @@ static inline int do_write(struct ioc3_port *port, char *buf, int len)
5370 }
5372 /**
5373 - * disable_intrs - disable interrupts
5374 + * ioc3_uart_disable_intrs - disable interrupts
5375 * @port: port to enable
5376 * @mask: mask to use
5377 */
5378 -static inline void disable_intrs(struct ioc3_port *port, uint32_t mask)
5379 +static void ioc3_uart_disable_intrs(struct ioc3_port *port, uint32_t mask)
5380 {
5381 if (port->ip_card->ic_enable & mask) {
5382 ioc3_disable(port->ip_is, port->ip_idd, mask);
5383 @@ -765,12 +784,12 @@ static inline void disable_intrs(struct ioc3_port *port, uint32_t mask)
5384 }
5386 /**
5387 - * set_notification - Modify event notification
5388 + * ioc3_set_notification - Modify event notification
5389 * @port: port to use
5390 * @mask: events mask
5391 * @set_on: set ?
5392 */
5393 -static int set_notification(struct ioc3_port *port, int mask, int set_on)
5394 +static int ioc3_set_notification(struct ioc3_port *port, int mask, int set_on)
5395 {
5396 struct port_hooks *hooks = port->ip_hooks;
5397 uint32_t intrbits, sscrbits;
5398 @@ -791,11 +810,11 @@ static int set_notification(struct ioc3_port *port, int mask, int set_on)
5399 intrbits |= hooks->intr_delta_cts;
5401 if (set_on) {
5402 - enable_intrs(port, intrbits);
5403 + ioc3_uart_enable_intrs(port, intrbits);
5404 port->ip_notify |= mask;
5405 port->ip_sscr |= sscrbits;
5406 } else {
5407 - disable_intrs(port, intrbits);
5408 + ioc3_uart_disable_intrs(port, intrbits);
5409 port->ip_notify &= ~mask;
5410 port->ip_sscr &= ~sscrbits;
5411 }
5412 @@ -814,15 +833,14 @@ static int set_notification(struct ioc3_port *port, int mask, int set_on)
5413 }
5415 /**
5416 - * set_mcr - set the master control reg
5417 + * ioc3_set_mcr - set the master control reg
5418 * @the_port: port to use
5419 * @mask1: mcr mask
5420 * @mask2: shadow mask
5421 */
5422 -static inline int set_mcr(struct uart_port *the_port,
5423 - int mask1, int mask2)
5424 +static int ioc3_set_mcr(struct uart_port *the_port, int mask1, int mask2)
5425 {
5426 - struct ioc3_port *port = get_ioc3_port(the_port);
5427 + struct ioc3_port *port = ioc3_get_ioc3port(the_port);
5428 uint32_t shadow;
5429 int spiniter = 0;
5430 char mcr;
5431 @@ -886,17 +904,17 @@ static int ioc3_set_proto(struct ioc3_port *port, int proto)
5432 }
5434 /**
5435 - * transmit_chars - upper level write, called with the_port->lock
5436 + * ioc3_transmit_chars - upper level write, called with the_port->lock
5437 * @the_port: port to write
5438 */
5439 -static void transmit_chars(struct uart_port *the_port)
5440 +static void ioc3_transmit_chars(struct uart_port *the_port)
5441 {
5442 + struct ioc3_port *port = ioc3_get_ioc3port(the_port);
5443 + struct uart_state *state;
5444 + struct tty_struct *tty;
5445 + char *start;
5446 int xmit_count, tail, head;
5447 int result;
5448 - char *start;
5449 - struct tty_struct *tty;
5450 - struct ioc3_port *port = get_ioc3_port(the_port);
5451 - struct uart_state *state;
5453 if (!the_port)
5454 return;
5455 @@ -908,7 +926,7 @@ static void transmit_chars(struct uart_port *the_port)
5457 if (uart_circ_empty(&state->xmit) || uart_tx_stopped(the_port)) {
5458 /* Nothing to do or hw stopped */
5459 - set_notification(port, N_ALL_OUTPUT, 0);
5460 + ioc3_set_notification(port, N_ALL_OUTPUT, 0);
5461 return;
5462 }
5464 @@ -919,7 +937,7 @@ static void transmit_chars(struct uart_port *the_port)
5465 /* write out all the data or until the end of the buffer */
5466 xmit_count = (head < tail) ? (UART_XMIT_SIZE - tail) : (head - tail);
5467 if (xmit_count > 0) {
5468 - result = do_write(port, start, xmit_count);
5469 + result = ioc3_do_write(port, start, xmit_count);
5470 if (result > 0) {
5471 /* booking */
5472 xmit_count -= result;
5473 @@ -934,11 +952,10 @@ static void transmit_chars(struct uart_port *the_port)
5474 if (uart_circ_chars_pending(&state->xmit) < WAKEUP_CHARS)
5475 uart_write_wakeup(the_port);
5477 - if (uart_circ_empty(&state->xmit)) {
5478 - set_notification(port, N_OUTPUT_LOWAT, 0);
5479 - } else {
5480 - set_notification(port, N_OUTPUT_LOWAT, 1);
5481 - }
5482 + if (uart_circ_empty(&state->xmit))
5483 + ioc3_set_notification(port, N_OUTPUT_LOWAT, 0);
5484 + else
5485 + ioc3_set_notification(port, N_OUTPUT_LOWAT, 1);
5486 }
5488 /**
5489 @@ -947,15 +964,14 @@ static void transmit_chars(struct uart_port *the_port)
5490 * @new_termios: new termios settings
5491 * @old_termios: old termios settings
5492 */
5493 -static void
5494 -ioc3_change_speed(struct uart_port *the_port,
5495 - struct ktermios *new_termios, struct ktermios *old_termios)
5496 +static void ioc3_change_speed(struct uart_port *the_port,
5497 + struct ktermios *new_termios, struct ktermios *old_termios)
5498 {
5499 - struct ioc3_port *port = get_ioc3_port(the_port);
5500 + struct ioc3_port *port = ioc3_get_ioc3port(the_port);
5501 + struct uart_state *state = the_port->state;
5502 + int new_parity = 0, new_parity_enable = 0, new_stop = 0, new_data = 8;
5503 unsigned int cflag, iflag;
5504 int baud;
5505 - int new_parity = 0, new_parity_enable = 0, new_stop = 0, new_data = 8;
5506 - struct uart_state *state = the_port->state;
5508 cflag = new_termios->c_cflag;
5509 iflag = new_termios->c_iflag;
5510 @@ -1024,26 +1040,26 @@ ioc3_change_speed(struct uart_port *the_port,
5512 /* Set the configuration and proper notification call */
5513 DPRINT_CONFIG(("%s : port 0x%p line %d cflag 0%o "
5514 - "config_port(baud %d data %d stop %d penable %d "
5515 + "ioc3_config_port(baud %d data %d stop %d penable %d "
5516 " parity %d), notification 0x%x\n",
5517 __func__, (void *)port, the_port->line, cflag, baud,
5518 new_data, new_stop, new_parity_enable, new_parity,
5519 the_port->ignore_status_mask));
5521 - if ((config_port(port, baud, /* baud */
5522 + if ((ioc3_config_port(port, baud, /* baud */
5523 new_data, /* byte size */
5524 new_stop, /* stop bits */
5525 new_parity_enable, /* set parity */
5526 new_parity)) >= 0) { /* parity 1==odd */
5527 - set_notification(port, the_port->ignore_status_mask, 1);
5528 + ioc3_set_notification(port, the_port->ignore_status_mask, 1);
5529 }
5530 }
5532 /**
5533 - * ic3_startup_local - Start up the serial port - returns >= 0 if no errors
5534 + * ioc3_startup_local - Start up the serial port - returns >= 0 if no errors
5535 * @the_port: Port to operate on
5536 */
5537 -static inline int ic3_startup_local(struct uart_port *the_port)
5538 +static int ioc3_startup_local(struct uart_port *the_port)
5539 {
5540 struct ioc3_port *port;
5542 @@ -1052,13 +1068,13 @@ static inline int ic3_startup_local(struct uart_port *the_port)
5543 return -1;
5544 }
5546 - port = get_ioc3_port(the_port);
5547 + port = ioc3_get_ioc3port(the_port);
5548 if (!port) {
5549 NOT_PROGRESS();
5550 return -1;
5551 }
5553 - local_open(port);
5554 + ioc3_local_open(port);
5556 /* set the protocol */
5557 ioc3_set_proto(port, IS_RS232(the_port->line) ? PROTO_RS232 :
5558 @@ -1072,13 +1088,11 @@ static inline int ic3_startup_local(struct uart_port *the_port)
5559 */
5560 static void ioc3_cb_output_lowat(struct ioc3_port *port)
5561 {
5562 - unsigned long pflags;
5563 -
5564 /* the_port->lock is set on the call here */
5565 if (port->ip_port) {
5566 - spin_lock_irqsave(&port->ip_port->lock, pflags);
5567 - transmit_chars(port->ip_port);
5568 - spin_unlock_irqrestore(&port->ip_port->lock, pflags);
5569 + spin_lock(&port->ip_port->lock);
5570 + ioc3_transmit_chars(port->ip_port);
5571 + spin_unlock(&port->ip_port->lock);
5572 }
5573 }
5575 @@ -1104,17 +1118,17 @@ static void ioc3_cb_post_ncs(struct uart_port *the_port, int ncs)
5576 }
5578 /**
5579 - * do_read - Read in bytes from the port. Return the number of bytes
5580 + * ioc3_do_read - Read in bytes from the port. Return the number of bytes
5581 * actually read.
5582 * @the_port: port to use
5583 * @buf: place to put the stuff we read
5584 * @len: how big 'buf' is
5585 */
5587 -static inline int do_read(struct uart_port *the_port, char *buf, int len)
5588 +static int ioc3_do_read(struct uart_port *the_port, char *buf, int len)
5589 {
5590 int prod_ptr, cons_ptr, total;
5591 - struct ioc3_port *port = get_ioc3_port(the_port);
5592 + struct ioc3_port *port = ioc3_get_ioc3port(the_port);
5593 struct ring *inring;
5594 struct ring_entry *entry;
5595 struct port_hooks *hooks;
5596 @@ -1379,21 +1393,21 @@ static inline int do_read(struct uart_port *the_port, char *buf, int len)
5597 SSCR_RX_THRESHOLD)
5598 << PROD_CONS_PTR_OFF))) {
5599 port->ip_flags &= ~INPUT_HIGH;
5600 - enable_intrs(port, hooks->intr_rx_high);
5601 + ioc3_uart_enable_intrs(port, hooks->intr_rx_high);
5602 }
5603 return total;
5604 }
5606 /**
5607 - * receive_chars - upper level read.
5608 + * ioc3_receive_chars - upper level read.
5609 * @the_port: port to read from
5610 */
5611 -static int receive_chars(struct uart_port *the_port)
5612 +static int ioc3_receive_chars(struct uart_port *the_port)
5613 {
5614 + struct ioc3_port *port = ioc3_get_ioc3port(the_port);
5615 + struct uart_state *state = the_port->state;
5616 unsigned char ch[MAX_CHARS];
5617 int read_count = 0, read_room, flip = 0;
5618 - struct uart_state *state = the_port->state;
5619 - struct ioc3_port *port = get_ioc3_port(the_port);
5620 unsigned long pflags;
5622 /* Make sure all the pointers are "good" ones */
5623 @@ -1405,7 +1419,7 @@ static int receive_chars(struct uart_port *the_port)
5625 spin_lock_irqsave(&the_port->lock, pflags);
5627 - read_count = do_read(the_port, ch, MAX_CHARS);
5628 + read_count = ioc3_do_read(the_port, ch, MAX_CHARS);
5629 if (read_count > 0) {
5630 flip = 1;
5631 read_room = tty_insert_flip_string(&state->port, ch,
5632 @@ -1421,26 +1435,23 @@ static int receive_chars(struct uart_port *the_port)
5633 }
5635 /**
5636 - * ioc3uart_intr_one - lowest level (per port) interrupt handler.
5637 + * ioc3_uart_intr_one - lowest level (per port) interrupt handler.
5638 * @is : submodule
5639 * @idd: driver data
5640 * @pending: interrupts to handle
5641 */
5643 static inline int
5644 -ioc3uart_intr_one(struct ioc3_submodule *is,
5645 - struct ioc3_driver_data *idd,
5646 - unsigned int pending)
5647 +ioc3_uart_intr_one(struct ioc3_submodule *is, struct ioc3_driver_data *idd,
5648 + unsigned int pending)
5649 {
5650 - int port_num = GET_PORT_FROM_SIO_IR(pending);
5651 + struct ioc3_card *card_ptr;
5652 + struct ioc3_port *port;
5653 struct port_hooks *hooks;
5654 - unsigned int rx_high_rd_aborted = 0;
5655 - unsigned long flags;
5656 struct uart_port *the_port;
5657 - struct ioc3_port *port;
5658 + unsigned int sio_ir, rx_high_rd_aborted = 0;
5659 + int port_num = GET_PORT_FROM_SIO_IR(pending);
5660 int loop_counter;
5661 - struct ioc3_card *card_ptr;
5662 - unsigned int sio_ir;
5664 card_ptr = idd->data[is->id];
5665 port = card_ptr->ic_port[port_num].icp_port;
5666 @@ -1462,14 +1473,14 @@ ioc3uart_intr_one(struct ioc3_submodule *is,
5667 */
5669 sio_ir = pending & ~(hooks->intr_tx_mt);
5670 - spin_lock_irqsave(&port->ip_lock, flags);
5671 + spin_lock(&port->ip_lock);
5673 loop_counter = MAXITER; /* to avoid hangs */
5675 do {
5676 uint32_t shadow;
5678 - if (loop_counter-- <= 0) {
5679 + if (unlikely(loop_counter-- <= 0)) {
5680 printk(KERN_WARNING "IOC3 serial: "
5681 "possible hang condition/"
5682 "port stuck on interrupt (line %d).\n",
5683 @@ -1477,7 +1488,7 @@ ioc3uart_intr_one(struct ioc3_submodule *is,
5684 break;
5685 }
5686 /* Handle a DCD change */
5687 - if (sio_ir & hooks->intr_delta_dcd) {
5688 + if (unlikely(sio_ir & hooks->intr_delta_dcd)) {
5689 ioc3_ack(is, idd, hooks->intr_delta_dcd);
5690 shadow = readl(&port->ip_serial_regs->shadow);
5692 @@ -1499,7 +1510,7 @@ ioc3uart_intr_one(struct ioc3_submodule *is,
5693 }
5695 /* Handle a CTS change */
5696 - if (sio_ir & hooks->intr_delta_cts) {
5697 + if (unlikely(sio_ir & hooks->intr_delta_cts)) {
5698 ioc3_ack(is, idd, hooks->intr_delta_cts);
5699 shadow = readl(&port->ip_serial_regs->shadow);
5701 @@ -1516,24 +1527,24 @@ ioc3uart_intr_one(struct ioc3_submodule *is,
5702 * before the check for rx_high since servicing this condition
5703 * may cause that condition to clear.
5704 */
5705 - if (sio_ir & hooks->intr_rx_timer) {
5706 + if (unlikely(sio_ir & hooks->intr_rx_timer)) {
5707 ioc3_ack(is, idd, hooks->intr_rx_timer);
5708 if ((port->ip_notify & N_DATA_READY)
5709 && (port->ip_port)) {
5710 - receive_chars(port->ip_port);
5711 + ioc3_receive_chars(port->ip_port);
5712 }
5713 }
5715 /* rx high interrupt. Must be after rx_timer. */
5716 - else if (sio_ir & hooks->intr_rx_high) {
5717 + else if (unlikely(sio_ir & hooks->intr_rx_high)) {
5718 /* Data available, notify upper layer */
5719 if ((port->ip_notify & N_DATA_READY) && port->ip_port) {
5720 - receive_chars(port->ip_port);
5721 + ioc3_receive_chars(port->ip_port);
5722 }
5724 - /* We can't ACK this interrupt. If receive_chars didn't
5725 - * cause the condition to clear, we'll have to disable
5726 - * the interrupt until the data is drained.
5727 + /* We can't ACK this interrupt. If ioc3_receive_chars
5728 + * didn't cause the condition to clear, we'll have to
5729 + * disable the interrupt until the data is drained.
5730 * If the read was aborted, don't disable the interrupt
5731 * as this may cause us to hang indefinitely. An
5732 * aborted read generally means that this interrupt
5733 @@ -1556,7 +1567,7 @@ ioc3uart_intr_one(struct ioc3_submodule *is,
5734 * send more data. Must come before tx_mt since servicing
5735 * this condition may cause that condition to clear.
5736 */
5737 - if (sio_ir & hooks->intr_tx_explicit) {
5738 + if (unlikely(sio_ir & hooks->intr_tx_explicit)) {
5739 port->ip_flags &= ~LOWAT_WRITTEN;
5740 ioc3_ack(is, idd, hooks->intr_tx_explicit);
5741 if (port->ip_notify & N_OUTPUT_LOWAT)
5742 @@ -1564,7 +1575,7 @@ ioc3uart_intr_one(struct ioc3_submodule *is,
5743 }
5745 /* Handle tx_mt. Must come after tx_explicit. */
5746 - else if (sio_ir & hooks->intr_tx_mt) {
5747 + else if (unlikely(sio_ir & hooks->intr_tx_mt)) {
5748 /* If we are expecting a lowat notification
5749 * and we get to this point it probably means that for
5750 * some reason the tx_explicit didn't work as expected
5751 @@ -1614,20 +1625,20 @@ ioc3uart_intr_one(struct ioc3_submodule *is,
5752 }
5753 } while (sio_ir & hooks->intr_all);
5755 - spin_unlock_irqrestore(&port->ip_lock, flags);
5756 + spin_unlock(&port->ip_lock);
5757 ioc3_enable(is, idd, card_ptr->ic_enable);
5758 return 0;
5759 }
5761 /**
5762 - * ioc3uart_intr - field all serial interrupts
5763 + * ioc3_uart_intr - field all serial interrupts
5764 * @is : submodule
5765 * @idd: driver data
5766 * @pending: interrupts to handle
5767 *
5768 */
5770 -static int ioc3uart_intr(struct ioc3_submodule *is,
5771 +static int ioc3_uart_intr(struct ioc3_submodule *is,
5772 struct ioc3_driver_data *idd,
5773 unsigned int pending)
5774 {
5775 @@ -1639,19 +1650,19 @@ static int ioc3uart_intr(struct ioc3_submodule *is,
5776 */
5778 if (pending & SIO_IR_SA)
5779 - ret |= ioc3uart_intr_one(is, idd, pending & SIO_IR_SA);
5780 + ret |= ioc3_uart_intr_one(is, idd, pending & SIO_IR_SA);
5781 if (pending & SIO_IR_SB)
5782 - ret |= ioc3uart_intr_one(is, idd, pending & SIO_IR_SB);
5783 + ret |= ioc3_uart_intr_one(is, idd, pending & SIO_IR_SB);
5785 return ret;
5786 }
5788 /**
5789 - * ic3_type
5790 + * ioc3_type
5791 * @port: Port to operate with (we ignore since we only have one port)
5792 *
5793 */
5794 -static const char *ic3_type(struct uart_port *the_port)
5795 +static const char *ioc3_type(struct uart_port *the_port)
5796 {
5797 if (IS_RS232(the_port->line))
5798 return "SGI IOC3 Serial [rs232]";
5799 @@ -1660,14 +1671,14 @@ static const char *ic3_type(struct uart_port *the_port)
5800 }
5802 /**
5803 - * ic3_tx_empty - Is the transmitter empty?
5804 + * ioc3_tx_empty - Is the transmitter empty?
5805 * @port: Port to operate on
5806 *
5807 */
5808 -static unsigned int ic3_tx_empty(struct uart_port *the_port)
5809 +static unsigned int ioc3_tx_empty(struct uart_port *the_port)
5810 {
5811 + struct ioc3_port *port = ioc3_get_ioc3port(the_port);
5812 unsigned int ret = 0;
5813 - struct ioc3_port *port = get_ioc3_port(the_port);
5815 if (readl(&port->ip_serial_regs->shadow) & SHADOW_TEMT)
5816 ret = TIOCSER_TEMT;
5817 @@ -1675,52 +1686,52 @@ static unsigned int ic3_tx_empty(struct uart_port *the_port)
5818 }
5820 /**
5821 - * ic3_stop_tx - stop the transmitter
5822 + * ioc3_stop_tx - stop the transmitter
5823 * @port: Port to operate on
5824 *
5825 */
5826 -static void ic3_stop_tx(struct uart_port *the_port)
5827 +static void ioc3_stop_tx(struct uart_port *the_port)
5828 {
5829 - struct ioc3_port *port = get_ioc3_port(the_port);
5830 + struct ioc3_port *port = ioc3_get_ioc3port(the_port);
5832 if (port)
5833 - set_notification(port, N_OUTPUT_LOWAT, 0);
5834 + ioc3_set_notification(port, N_OUTPUT_LOWAT, 0);
5835 }
5837 /**
5838 - * ic3_stop_rx - stop the receiver
5839 + * ioc3_stop_rx - stop the receiver
5840 * @port: Port to operate on
5841 *
5842 */
5843 -static void ic3_stop_rx(struct uart_port *the_port)
5844 +static void ioc3_stop_rx(struct uart_port *the_port)
5845 {
5846 - struct ioc3_port *port = get_ioc3_port(the_port);
5847 + struct ioc3_port *port = ioc3_get_ioc3port(the_port);
5849 if (port)
5850 port->ip_flags &= ~INPUT_ENABLE;
5851 }
5853 /**
5854 - * null_void_function
5855 + * ioc3_null_void_function
5856 * @port: Port to operate on
5857 *
5858 */
5859 -static void null_void_function(struct uart_port *the_port)
5860 +static void ioc3_null_void_function(struct uart_port *the_port)
5861 {
5862 }
5864 /**
5865 - * ic3_shutdown - shut down the port - free irq and disable
5866 + * ioc3_shutdown - shut down the port - free irq and disable
5867 * @port: port to shut down
5868 *
5869 */
5870 -static void ic3_shutdown(struct uart_port *the_port)
5871 +static void ioc3_shutdown(struct uart_port *the_port)
5872 {
5873 - unsigned long port_flags;
5874 struct ioc3_port *port;
5875 struct uart_state *state;
5876 + unsigned long port_flags;
5878 - port = get_ioc3_port(the_port);
5879 + port = ioc3_get_ioc3port(the_port);
5880 if (!port)
5881 return;
5883 @@ -1728,17 +1739,17 @@ static void ic3_shutdown(struct uart_port *the_port)
5884 wake_up_interruptible(&state->port.delta_msr_wait);
5886 spin_lock_irqsave(&the_port->lock, port_flags);
5887 - set_notification(port, N_ALL, 0);
5888 + ioc3_set_notification(port, N_ALL, 0);
5889 spin_unlock_irqrestore(&the_port->lock, port_flags);
5890 }
5892 /**
5893 - * ic3_set_mctrl - set control lines (dtr, rts, etc)
5894 + * ioc3_set_mctrl - set control lines (dtr, rts, etc)
5895 * @port: Port to operate on
5896 * @mctrl: Lines to set/unset
5897 *
5898 */
5899 -static void ic3_set_mctrl(struct uart_port *the_port, unsigned int mctrl)
5900 +static void ioc3_set_mctrl(struct uart_port *the_port, unsigned int mctrl)
5901 {
5902 unsigned char mcr = 0;
5904 @@ -1753,17 +1764,17 @@ static void ic3_set_mctrl(struct uart_port *the_port, unsigned int mctrl)
5905 if (mctrl & TIOCM_LOOP)
5906 mcr |= UART_MCR_LOOP;
5908 - set_mcr(the_port, mcr, SHADOW_DTR);
5909 + ioc3_set_mcr(the_port, mcr, SHADOW_DTR);
5910 }
5912 /**
5913 - * ic3_get_mctrl - get control line info
5914 + * ioc3_get_mctrl - get control line info
5915 * @port: port to operate on
5916 *
5917 */
5918 -static unsigned int ic3_get_mctrl(struct uart_port *the_port)
5919 +static unsigned int ioc3_get_mctrl(struct uart_port *the_port)
5920 {
5921 - struct ioc3_port *port = get_ioc3_port(the_port);
5922 + struct ioc3_port *port = ioc3_get_ioc3port(the_port);
5923 uint32_t shadow;
5924 unsigned int ret = 0;
5926 @@ -1781,47 +1792,47 @@ static unsigned int ic3_get_mctrl(struct uart_port *the_port)
5927 }
5929 /**
5930 - * ic3_start_tx - Start transmitter. Called with the_port->lock
5931 + * ioc3_start_tx - Start transmitter. Called with the_port->lock
5932 * @port: Port to operate on
5933 *
5934 */
5935 -static void ic3_start_tx(struct uart_port *the_port)
5936 +static void ioc3_start_tx(struct uart_port *the_port)
5937 {
5938 - struct ioc3_port *port = get_ioc3_port(the_port);
5939 + struct ioc3_port *port = ioc3_get_ioc3port(the_port);
5941 if (port) {
5942 - set_notification(port, N_OUTPUT_LOWAT, 1);
5943 - enable_intrs(port, port->ip_hooks->intr_tx_mt);
5944 + ioc3_set_notification(port, N_OUTPUT_LOWAT, 1);
5945 + ioc3_uart_enable_intrs(port, port->ip_hooks->intr_tx_mt);
5946 }
5947 }
5949 /**
5950 - * ic3_break_ctl - handle breaks
5951 + * ioc3_break_ctl - handle breaks
5952 * @port: Port to operate on
5953 * @break_state: Break state
5954 *
5955 */
5956 -static void ic3_break_ctl(struct uart_port *the_port, int break_state)
5957 +static void ioc3_break_ctl(struct uart_port *the_port, int break_state)
5958 {
5959 }
5961 /**
5962 - * ic3_startup - Start up the serial port - always return 0 (We're always on)
5963 + * ioc3_startup - Start up the serial port - always return 0 (We're always on)
5964 * @port: Port to operate on
5965 *
5966 */
5967 -static int ic3_startup(struct uart_port *the_port)
5968 +static int ioc3_startup(struct uart_port *the_port)
5969 {
5970 - int retval;
5971 struct ioc3_port *port;
5972 struct ioc3_card *card_ptr;
5973 unsigned long port_flags;
5974 + int retval;
5976 if (!the_port) {
5977 NOT_PROGRESS();
5978 return -ENODEV;
5979 }
5980 - port = get_ioc3_port(the_port);
5981 + port = ioc3_get_ioc3port(the_port);
5982 if (!port) {
5983 NOT_PROGRESS();
5984 return -ENODEV;
5985 @@ -1836,21 +1847,21 @@ static int ic3_startup(struct uart_port *the_port)
5987 /* Start up the serial port */
5988 spin_lock_irqsave(&the_port->lock, port_flags);
5989 - retval = ic3_startup_local(the_port);
5990 + retval = ioc3_startup_local(the_port);
5991 spin_unlock_irqrestore(&the_port->lock, port_flags);
5992 return retval;
5993 }
5995 /**
5996 - * ic3_set_termios - set termios stuff
5997 + * ioc3_set_termios - set termios stuff
5998 * @port: port to operate on
5999 * @termios: New settings
6000 * @termios: Old
6001 *
6002 */
6003 -static void
6004 -ic3_set_termios(struct uart_port *the_port,
6005 - struct ktermios *termios, struct ktermios *old_termios)
6006 +static void ioc3_set_termios(struct uart_port *the_port,
6007 + struct ktermios *termios,
6008 + struct ktermios *old_termios)
6009 {
6010 unsigned long port_flags;
6012 @@ -1860,30 +1871,30 @@ ic3_set_termios(struct uart_port *the_port,
6013 }
6015 /**
6016 - * ic3_request_port - allocate resources for port - no op....
6017 + * ioc3_request_port - allocate resources for port - no op....
6018 * @port: port to operate on
6019 *
6020 */
6021 -static int ic3_request_port(struct uart_port *port)
6022 +static int ioc3_request_port(struct uart_port *port)
6023 {
6024 return 0;
6025 }
6027 /* Associate the uart functions above - given to serial core */
6028 static const struct uart_ops ioc3_ops = {
6029 - .tx_empty = ic3_tx_empty,
6030 - .set_mctrl = ic3_set_mctrl,
6031 - .get_mctrl = ic3_get_mctrl,
6032 - .stop_tx = ic3_stop_tx,
6033 - .start_tx = ic3_start_tx,
6034 - .stop_rx = ic3_stop_rx,
6035 - .break_ctl = ic3_break_ctl,
6036 - .startup = ic3_startup,
6037 - .shutdown = ic3_shutdown,
6038 - .set_termios = ic3_set_termios,
6039 - .type = ic3_type,
6040 - .release_port = null_void_function,
6041 - .request_port = ic3_request_port,
6042 + .tx_empty = ioc3_tx_empty,
6043 + .set_mctrl = ioc3_set_mctrl,
6044 + .get_mctrl = ioc3_get_mctrl,
6045 + .stop_tx = ioc3_stop_tx,
6046 + .start_tx = ioc3_start_tx,
6047 + .stop_rx = ioc3_stop_rx,
6048 + .break_ctl = ioc3_break_ctl,
6049 + .startup = ioc3_startup,
6050 + .shutdown = ioc3_shutdown,
6051 + .set_termios = ioc3_set_termios,
6052 + .type = ioc3_type,
6053 + .release_port = ioc3_null_void_function,
6054 + .request_port = ioc3_request_port,
6055 };
6057 /*
6058 @@ -1901,18 +1912,18 @@ static struct uart_driver ioc3_uart = {
6060 /**
6061 * ioc3_serial_core_attach - register with serial core
6062 - * This is done during pci probing
6063 + * This is done during pci probing
6064 * @is: submodule struct for this
6065 * @idd: handle for this card
6066 */
6067 -static inline int ioc3_serial_core_attach( struct ioc3_submodule *is,
6068 - struct ioc3_driver_data *idd)
6069 +static int ioc3_serial_core_attach(struct ioc3_submodule *is,
6070 + struct ioc3_driver_data *idd)
6071 {
6072 - struct ioc3_port *port;
6073 struct uart_port *the_port;
6074 + struct ioc3_port *port;
6075 struct ioc3_card *card_ptr = idd->data[is->id];
6076 - int ii, phys_port;
6077 struct pci_dev *pdev = idd->pdev;
6078 + int ii, phys_port;
6080 DPRINT_CONFIG(("%s: attach pdev 0x%p - card_ptr 0x%p\n",
6081 __func__, pdev, (void *)card_ptr));
6082 @@ -1960,13 +1971,13 @@ static inline int ioc3_serial_core_attach( struct ioc3_submodule *is,
6083 }
6085 /**
6086 - * ioc3uart_remove - register detach function
6087 + * ioc3_uart_remove - register detach function
6088 * @is: submodule struct for this submodule
6089 * @idd: ioc3 driver data for this submodule
6090 */
6092 -static int ioc3uart_remove(struct ioc3_submodule *is,
6093 - struct ioc3_driver_data *idd)
6094 +static int ioc3_uart_remove(struct ioc3_submodule *is,
6095 + struct ioc3_driver_data *idd)
6096 {
6097 struct ioc3_card *card_ptr = idd->data[is->id];
6098 struct uart_port *the_port;
6099 @@ -1998,21 +2009,21 @@ static int ioc3uart_remove(struct ioc3_submodule *is,
6100 }
6102 /**
6103 - * ioc3uart_probe - card probe function called from shim driver
6104 + * ioc3_uart_probe - card probe function called from shim driver
6105 * @is: submodule struct for this submodule
6106 * @idd: ioc3 driver data for this card
6107 */
6109 -static int
6110 -ioc3uart_probe(struct ioc3_submodule *is, struct ioc3_driver_data *idd)
6111 +static int ioc3_uart_probe(struct ioc3_submodule *is,
6112 + struct ioc3_driver_data *idd)
6113 {
6114 struct pci_dev *pdev = idd->pdev;
6115 - struct ioc3_card *card_ptr;
6116 - int ret = 0;
6117 - struct ioc3_port *port;
6118 struct ioc3_port *ports[PORTS_PER_CARD];
6119 + struct ioc3_port *port;
6120 + struct ioc3_card *card_ptr;
6121 int phys_port;
6122 int cnt;
6123 + int ret = 0;
6125 DPRINT_CONFIG(("%s (0x%p, 0x%p)\n", __func__, is, idd));
6127 @@ -2029,8 +2040,6 @@ ioc3uart_probe(struct ioc3_submodule *is, struct ioc3_driver_data *idd)
6128 ((UARTB_BASE >> 3) << SIO_CR_SER_B_BASE_SHIFT) |
6129 (0xf << SIO_CR_CMD_PULSE_SHIFT), &idd->vma->sio_cr);
6131 - pci_write_config_dword(pdev, PCI_LAT, 0xff00);
6132 -
6133 /* Enable serial port mode select generic PIO pins as outputs */
6134 ioc3_gpcr_set(idd, GPCR_UARTA_MODESEL | GPCR_UARTB_MODESEL);
6136 @@ -2121,7 +2130,7 @@ ioc3uart_probe(struct ioc3_submodule *is, struct ioc3_driver_data *idd)
6137 (void *)port->ip_uart_regs));
6139 /* Initialize the hardware for IOC3 */
6140 - port_init(port);
6141 + ioc3_port_init(port);
6143 DPRINT_CONFIG(("%s: phys_port %d port 0x%p inring 0x%p "
6144 "outring 0x%p\n",
6145 @@ -2151,20 +2160,20 @@ ioc3uart_probe(struct ioc3_submodule *is, struct ioc3_driver_data *idd)
6146 return ret;
6147 }
6149 -static struct ioc3_submodule ioc3uart_ops = {
6150 +static struct ioc3_submodule ioc3_uart_ops = {
6151 .name = "IOC3uart",
6152 - .probe = ioc3uart_probe,
6153 - .remove = ioc3uart_remove,
6154 + .probe = ioc3_uart_probe,
6155 + .remove = ioc3_uart_remove,
6156 /* call .intr for both ports initially */
6157 .irq_mask = SIO_IR_SA | SIO_IR_SB,
6158 - .intr = ioc3uart_intr,
6159 + .intr = ioc3_uart_intr,
6160 .owner = THIS_MODULE,
6161 };
6163 /**
6164 * ioc3_detect - module init called,
6165 */
6166 -static int __init ioc3uart_init(void)
6167 +static int __init ioc3_uart_init(void)
6168 {
6169 int ret;
6171 @@ -2175,20 +2184,20 @@ static int __init ioc3uart_init(void)
6172 __func__);
6173 return ret;
6174 }
6175 - ret = ioc3_register_submodule(&ioc3uart_ops);
6176 + ret = ioc3_register_submodule(&ioc3_uart_ops);
6177 if (ret)
6178 uart_unregister_driver(&ioc3_uart);
6179 return ret;
6180 }
6182 -static void __exit ioc3uart_exit(void)
6183 +static void __exit ioc3_uart_exit(void)
6184 {
6185 - ioc3_unregister_submodule(&ioc3uart_ops);
6186 + ioc3_unregister_submodule(&ioc3_uart_ops);
6187 uart_unregister_driver(&ioc3_uart);
6188 }
6190 -module_init(ioc3uart_init);
6191 -module_exit(ioc3uart_exit);
6192 +module_init(ioc3_uart_init);
6193 +module_exit(ioc3_uart_exit);
6195 MODULE_AUTHOR("Pat Gefre - Silicon Graphics Inc. (SGI) <pfg@sgi.com>");
6196 MODULE_DESCRIPTION("Serial PCI driver module for SGI IOC3 card");
6197 diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c
6198 index 9c14a453f73c..e5e01c9465ac 100644
6199 --- a/drivers/tty/serial/serial_core.c
6200 +++ b/drivers/tty/serial/serial_core.c
6201 @@ -2234,6 +2234,10 @@ uart_report_port(struct uart_driver *drv, struct uart_port *port)
6202 snprintf(address, sizeof(address),
6203 "MMIO 0x%llx", (unsigned long long)port->mapbase);
6204 break;
6205 + case UPIO_IOC3:
6206 + snprintf(address, sizeof(address), "IOC3 0x%llx",
6207 + (unsigned long long)port->mapbase);
6208 + break;
6209 default:
6210 strlcpy(address, "*unknown*", sizeof(address));
6211 break;
6212 @@ -2895,6 +2899,7 @@ int uart_match_port(struct uart_port *port1, struct uart_port *port2)
6213 case UPIO_MEM32BE:
6214 case UPIO_AU:
6215 case UPIO_TSI:
6216 + case UPIO_IOC3:
6217 return (port1->mapbase == port2->mapbase);
6218 }
6219 return 0;
6220 diff --git a/include/linux/ioc3.h b/include/linux/ioc3.h
6221 index 38b286e9a46c..09cb070ef0eb 100644
6222 --- a/include/linux/ioc3.h
6223 +++ b/include/linux/ioc3.h
6224 @@ -3,15 +3,20 @@
6225 * License. See the file "COPYING" in the main directory of this archive
6226 * for more details.
6227 *
6228 - * Copyright (c) 2005 Stanislaw Skowronek <skylark@linux-mips.org>
6229 + * Copyright (c) 2005 Stanislaw Skowronek <skylark@unaligned.org>
6230 */
6232 #ifndef _LINUX_IOC3_H
6233 #define _LINUX_IOC3_H
6235 +#include <linux/device.h>
6236 +#if defined(CONFIG_MIPS)
6237 +#include <asm/sgi/ioc3.h>
6238 +#elif defined(CONFIG_IA64)
6239 #include <asm/sn/ioc3.h>
6240 +#endif
6242 -#define IOC3_MAX_SUBMODULES 32
6243 +#define IOC3_MAX_SUBMODULES 8
6245 #define IOC3_CLASS_NONE 0
6246 #define IOC3_CLASS_BASE_IP27 1
6247 @@ -25,22 +30,22 @@
6248 struct ioc3_driver_data {
6249 struct list_head list;
6250 int id; /* IOC3 sequence number */
6251 + int class; /* IOC3 type */
6252 +
6253 /* PCI mapping */
6254 - unsigned long pma; /* physical address */
6255 struct ioc3 __iomem *vma; /* pointer to registers */
6256 struct pci_dev *pdev; /* PCI device */
6257 /* IRQ stuff */
6258 int dual_irq; /* set if separate IRQs are used */
6259 int irq_io, irq_eth; /* IRQ numbers */
6260 /* GPIO magic */
6261 - spinlock_t gpio_lock;
6262 unsigned int gpdr_shadow;
6263 + spinlock_t gpio_lock;
6264 /* NIC identifiers */
6265 char nic_part[32];
6266 char nic_serial[16];
6267 char nic_mac[6];
6268 /* submodule set */
6269 - int class;
6270 void *data[IOC3_MAX_SUBMODULES]; /* for submodule use */
6271 int active[IOC3_MAX_SUBMODULES]; /* set if probe succeeds */
6272 /* is_ir_lock must be held while
6273 @@ -56,10 +61,10 @@ struct ioc3_driver_data {
6274 struct ioc3_submodule {
6275 char *name; /* descriptive submodule name */
6276 struct module *owner; /* owning kernel module */
6277 - int ethernet; /* set for ethernet drivers */
6278 int (*probe) (struct ioc3_submodule *, struct ioc3_driver_data *);
6279 int (*remove) (struct ioc3_submodule *, struct ioc3_driver_data *);
6280 int id; /* assigned by IOC3, index for the "data" array */
6281 + int ethernet; /* set for ethernet drivers */
6282 /* IRQ stuff */
6283 unsigned int irq_mask; /* IOC3 IRQ mask, leave clear for Ethernet */
6284 int reset_mask; /* non-zero if you want the ioc3.c module to reset interrupts */
6285 @@ -89,5 +94,17 @@ extern void ioc3_disable(struct ioc3_submodule *, struct ioc3_driver_data *, uns
6286 extern void ioc3_gpcr_set(struct ioc3_driver_data *, unsigned int);
6287 /* general ireg writer */
6288 extern void ioc3_write_ireg(struct ioc3_driver_data *idd, uint32_t value, int reg);
6289 +/* atomically sets/clears GPIO bits */
6290 +extern void ioc3_gpio(struct ioc3_driver_data *idd, u32 mask, u32 val);
6291 +
6292 +/*
6293 + * ioc3_submodule_driver() - Helper macro for ioc3 submodules that don't do
6294 + * anything special in module init/exit. This eliminates a bit of
6295 + * boilerplate. Each submodule may only use this macro once, and calling it
6296 + * replaces ioc3_register_submodule() and ioc3_unregister_submodule()
6297 + */
6298 +#define ioc3_submodule_driver(__ioc3_submodule) \
6299 + module_driver(__ioc3_submodule, ioc3_register_submodule, \
6300 + ioc3_unregister_submodule)
6302 #endif
6303 diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
6304 index 06ea4eeb09ab..378f0b191037 100644
6305 --- a/include/linux/serial_core.h
6306 +++ b/include/linux/serial_core.h
6307 @@ -154,6 +154,7 @@ struct uart_port {
6308 #define UPIO_TSI (SERIAL_IO_TSI) /* Tsi108/109 type IO */
6309 #define UPIO_MEM32BE (SERIAL_IO_MEM32BE) /* 32b big endian */
6310 #define UPIO_MEM16 (SERIAL_IO_MEM16) /* 16b little endian */
6311 +#define UPIO_IOC3 (SERIAL_IO_IOC3) /* SGI IOC3 IO */
6313 /* quirks must be updated while holding port mutex */
6314 #define UPQ_NO_TXEN_TEST BIT(0)
6315 diff --git a/include/uapi/linux/serial.h b/include/uapi/linux/serial.h
6316 index 3fdd0dee8b41..9c3b971cd1e3 100644
6317 --- a/include/uapi/linux/serial.h
6318 +++ b/include/uapi/linux/serial.h
6319 @@ -71,6 +71,7 @@ struct serial_struct {
6320 #define SERIAL_IO_TSI 5
6321 #define SERIAL_IO_MEM32BE 6
6322 #define SERIAL_IO_MEM16 7
6323 +#define SERIAL_IO_IOC3 8
6325 #define UART_CLEAR_FIFO 0x01
6326 #define UART_USE_FIFO 0x02