| blob | a9cc4e96fa2af20dc3b827250b05993b05bf206f |
1 diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
2 index 29502238e510..a84dc2c07d48 100644
3 --- a/include/linux/pci_ids.h
4 +++ b/include/linux/pci_ids.h
5 @@ -1063,6 +1063,7 @@
6 #define PCI_VENDOR_ID_SGI 0x10a9
7 #define PCI_DEVICE_ID_SGI_IOC3 0x0003
8 #define PCI_DEVICE_ID_SGI_LITHIUM 0x1002
9 +#define PCI_DEVICE_ID_SGI_RAD1 0x0005
10 #define PCI_DEVICE_ID_SGI_IOC4 0x100a
12 #define PCI_VENDOR_ID_WINBOND 0x10ad
13 diff --git a/sound/pci/Kconfig b/sound/pci/Kconfig
14 index 4105d9f653d9..f2ddbdb2d4dc 100644
15 --- a/sound/pci/Kconfig
16 +++ b/sound/pci/Kconfig
17 @@ -907,6 +907,12 @@ config SND_YMFPCI
18 To compile this driver as a module, choose M here: the module
19 will be called snd-ymfpci.
21 +config SND_RAD1
22 + tristate "SGI RAD1"
23 + depends on SND && SGI_IP30
24 + help
25 + Say 'Y' or 'M' to include support for SGI RAD1 Pro Audio in Octane.
26 +
27 endif # SND_PCI
29 source "sound/pci/hda/Kconfig"
30 diff --git a/arch/mips/pci/pci-bridge.c b/arch/mips/pci/pci-bridge.c
31 index 28b0eb5b844e..9df13ce313b5 100644
32 --- a/arch/mips/pci/pci-bridge.c
33 +++ b/arch/mips/pci/pci-bridge.c
34 @@ -368,6 +368,9 @@ bridge_disable_swapping_dma(struct pci_dev *dev)
35 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
36 bridge_disable_swapping_dma);
38 +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_RAD1,
39 + bridge_disable_swapping_dma);
40 +
41 static int __init
42 bridge_init(struct platform_device *pdev)
43 {
44 diff --git a/sound/pci/Makefile b/sound/pci/Makefile
45 index 04cac7469139..9186ff609192 100644
46 --- a/sound/pci/Makefile
47 +++ b/sound/pci/Makefile
48 @@ -22,6 +22,7 @@ snd-fm801-objs := fm801.o
49 snd-intel8x0-objs := intel8x0.o
50 snd-intel8x0m-objs := intel8x0m.o
51 snd-maestro3-objs := maestro3.o
52 +snd-rad1-objs := rad1.o
53 snd-rme32-objs := rme32.o
54 snd-rme96-objs := rme96.o
55 snd-sis7019-objs := sis7019.o
56 @@ -48,6 +49,7 @@ obj-$(CONFIG_SND_FM801) += snd-fm801.o
57 obj-$(CONFIG_SND_INTEL8X0) += snd-intel8x0.o
58 obj-$(CONFIG_SND_INTEL8X0M) += snd-intel8x0m.o
59 obj-$(CONFIG_SND_MAESTRO3) += snd-maestro3.o
60 +obj-$(CONFIG_SND_RAD1) += snd-rad1.o
61 obj-$(CONFIG_SND_RME32) += snd-rme32.o
62 obj-$(CONFIG_SND_RME96) += snd-rme96.o
63 obj-$(CONFIG_SND_SIS7019) += snd-sis7019.o
64 diff --git a/include/sound/rad1.h b/include/sound/rad1.h
65 new file mode 100644
66 index 000000000000..3acbb6cd36f2
67 --- /dev/null
68 +++ b/include/sound/rad1.h
69 @@ -0,0 +1,120 @@
70 +/*
71 + * This file is subject to the terms and conditions of the GNU General Public
72 + * License. See the file "COPYING" in the main directory of this archive
73 + * for more details.
74 + *
75 + * Copyright (C) 2004-2007 Stanislaw Skowronek <skylark@unaligned.org>
76 + * Copyright (C) 2018 René Rebe <rene@exactcode.de>
77 + */
78 +
79 +#ifndef _SOUND_RAD1_H
80 +#define _SOUND_RAD1_H
81 +
82 +#include <linux/types.h>
83 +
84 +#define RAD1_ADATRX 0
85 +#define RAD1_AESRX 1
86 +#define RAD1_ADC 2
87 +#define RAD1_ADATSUBRX 3
88 +#define RAD1_AESSUBRX 4
89 +#define RAD1_ADATTX 5
90 +#define RAD1_AESTX 6
91 +#define RAD1_DAC 7
92 +#define RAD1_STATUS 8
93 +
94 +struct rad1regs {
95 + u32 pci_status; /* 0x00000000 */
96 + u32 adat_rx_msc_ust; /* 0x00000004 */
97 + u32 adat_rx_msc0_submsc; /* 0x00000008 */
98 + u32 aes_rx_msc_ust; /* 0x0000000c */
99 + u32 aes_rx_msc0_submsc; /* 0x00000010 */
100 + u32 adc_msc_ust; /* 0x00000014 */
101 + u32 adc_msc0_submsc; /* 0x00000018 */
102 + u32 adat_tx_msc_ust; /* 0x0000001c */
103 + u32 adat_tx_msc0_submsc; /* 0x00000020 */
104 + u32 aes_tx_msc_ust; /* 0x00000024 */
105 + u32 aes_tx_msc0_submsc; /* 0x00000028 */
106 + u32 dac_msc_ust; /* 0x0000002c */
107 + u32 ust_register; /* 0x00000030 */
108 + u32 gpio_status; /* 0x00000034 */
109 + u32 chip_status1; /* 0x00000038 */
110 + u32 chip_status0; /* 0x0000003c */
111 +
112 + u32 ust_clock_control; /* 0x00000040 */
113 + u32 adat_rx_control; /* 0x00000044 */
114 + u32 aes_rx_control; /* 0x00000048 */
115 + u32 adc_control; /* 0x0000004c */
116 + u32 adat_tx_control; /* 0x00000050 */
117 + u32 aes_tx_control; /* 0x00000054 */
118 + u32 dac_control; /* 0x00000058 */
119 + u32 status_timer; /* 0x0000005c */
120 +
121 + u32 _pad70[4];
122 +
123 + u32 misc_control; /* 0x00000070 */
124 + u32 pci_holdoff; /* 0x00000074 */
125 + u32 pci_arb_control; /* 0x00000078 */
126 +
127 + u32 volume_control; /* 0x0000007c */
128 +
129 + u32 reset; /* 0x00000080 */
130 +
131 + u32 gpio0; /* 0x00000084 */
132 + u32 gpio1; /* 0x00000088 */
133 + u32 gpio2; /* 0x0000008c */
134 + u32 gpio3; /* 0x00000090 */
135 +
136 + u32 _pada0[3];
137 +
138 + u32 clockgen_ictl; /* 0x000000a0 */
139 + u32 clockgen_rem; /* 0x000000a4 */
140 + u32 freq_synth_mux_sel[4]; /* 0x000000a8 */
141 + u32 mpll0_lock_control; /* 0x000000b8 */
142 + u32 mpll1_lock_control; /* 0x000000bc */
143 +
144 + u32 _pad400[208];
145 +
146 + /* descriptor RAM */
147 + struct {
148 + u32 loadr; /* 0x00000400 + 12*idx */
149 + u32 hiadr; /* 0x00000404 + 12*idx */
150 + u32 control; /* 0x00000408 + 12*idx */
151 + } pci_descr[16];
152 +
153 + /* running descriptors */
154 + struct {
155 + u32 loadr;
156 + u32 control;
157 + } pci_lc[9];
158 + u32 pci_hiadr[9];
159 +
160 + u32 _pad1000[693];
161 +
162 + u32 adat_subcode_txa_u[24]; /* 0x00001000 */
163 + u32 adat_subcode_txa_unused; /* 0x00001060 */
164 +
165 + u32 _pad1080[7];
166 +
167 + u32 adat_subcode_txb_u[24]; /* 0x00001080 */
168 + u32 adat_subcode_txb_unused; /* 0x000010e0 */
169 +
170 + u32 _pad1100[7];
171 +
172 + u32 aes_subcode_txa_lu[6]; /* 0x00001100 */
173 + u32 aes_subcode_txa_lc[6]; /* 0x00001118 */
174 + u32 aes_subcode_txa_lv[6]; /* 0x00001130 */
175 + u32 aes_subcode_txa_ru[6]; /* 0x00001148 */
176 + u32 aes_subcode_txa_rc[6]; /* 0x00001160 */
177 + u32 aes_subcode_txa_rv0[2]; /* 0x00001178 */
178 + u32 aes_subcode_txb_lu[6]; /* 0x00001180 */
179 + u32 aes_subcode_txb_lc[6]; /* 0x00001198 */
180 + u32 aes_subcode_txb_lv[6]; /* 0x000011b0 */
181 + u32 aes_subcode_txb_ru[6]; /* 0x000011c8 */
182 + u32 aes_subcode_txb_rc[6]; /* 0x000011e0 */
183 + u32 aes_subcode_txb_rv0[2]; /* 0x000011f8 */
184 + u32 aes_subcode_txa_rv2[4]; /* 0x00001200 */
185 + u32 aes_subcode_txb_rv2[4]; /* 0x00001210 */
186 + u32 aes_subcode_tx_unused; /* 0x00001220 */
187 +};
188 +
189 +#endif /* _SOUND_RAD1_H */
190 diff --git a/sound/pci/rad1.c b/sound/pci/rad1.c
191 new file mode 100644
192 index 000000000000..24318b1c9187
193 --- /dev/null
194 +++ b/sound/pci/rad1.c
195 @@ -0,0 +1,1527 @@
196 +/*
197 + * rad1.c - ALSA driver for SGI RAD1 (as found in Octane and Octane2)
198 + * Copyright (C) 2004-2007 by Stanislaw Skowronek <skylark@unaligned.org>
199 + * Copyright (C) 2018 René Rebe <rene@exactcode.de>
200 + *
201 + * This program is free software; you can redistribute it and/or modify
202 + * it under the terms of the GNU General Public License as published by
203 + * the Free Software Foundation; either version 2 of the License, or
204 + * (at your option) any later version.
205 + *
206 + * This program is distributed in the hope that it will be useful,
207 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
208 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
209 + * GNU General Public License for more details.
210 + *
211 + * You should have received a copy of the GNU General Public License
212 + * along with this program; if not, write to the Free Software
213 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA02111-1307 USA
214 + */
215 +
216 +#include <linux/delay.h>
217 +#include <linux/init.h>
218 +#include <linux/pci.h>
219 +#include <linux/slab.h>
220 +#include <linux/timer.h>
221 +#include <linux/spinlock.h>
222 +#include <linux/module.h>
223 +
224 +#include <sound/core.h>
225 +#include <sound/initval.h>
226 +#include <sound/pcm.h>
227 +#include <sound/control.h>
228 +
229 +#include <sound/rad1.h>
230 +
231 +struct snd_rad1_pipe {
232 + unsigned long pma; /* physical addr of the ring */
233 + int *vma; /* virtual addr of the ring */
234 + struct snd_pcm_substream *subs; /* ALSA substream */
235 + struct snd_pcm *pcm;
236 + unsigned int pnum; /* number of periods */
237 + unsigned int plen; /* length of period (in bytes) */
238 + unsigned int hptr; /* hardware pointer */
239 + int adma; /* DMA active flag */
240 + unsigned int qptr; /* queue pointer */
241 +};
242 +
243 +struct snd_rad1 {
244 + spinlock_t lock;
245 + struct snd_card *card;
246 + struct pci_dev *pci;
247 + unsigned long mmio_phys;
248 + volatile struct rad1regs *mmio;
249 + int timer_active;
250 + struct timer_list timer;
251 + struct snd_rad1_pipe pipes[9];
252 +
253 + /* random stuff */
254 + int last_aesrx_rate;
255 +
256 + /* card controls */
257 + unsigned int attctrl; /* Attenuation control */
258 + unsigned int rt_adc; /* ADC routing */
259 + unsigned int rt_aesr; /* AES Rx routing */
260 + unsigned int rt_adat; /* ADAT Rx routing */
261 + unsigned int rt_opto; /* Optical Out routing */
262 +};
263 +
264 +/* ----------------------------------------------------------------------- */
265 +
266 +
267 +/* ----------------------------------------------------------------------- */
268 +/* Hardware initialization, DMa, Pipe setup */
269 +static void
270 +snd_rad1_hw_init(struct snd_rad1 *chip)
271 +{
272 + /* The hex values listed here are, for the most part, unknown values
273 + * determined by running portions of the IRIX kernel inside of Linux
274 + * as a userland application and then extracting the run-time info.
275 + *
276 + * We could define them via macros if we wanted, but the macro names
277 + * would be no more intelligible as RAD1_ANCIENT_MU_* than they are
278 + * simple hex numbers, so until the purpose of each value is known,
279 + * they shall remain as simple hex numbers.
280 + *
281 + * The same applies for pretty much any other hex number found in
282 + * driver that isn't a bit mask or some sort. One day, we may figure
283 + * it all out, and create an appropriate header file to define them
284 + * all as intelligible macros.
285 + */
286 + volatile struct rad1regs *mmio = chip->mmio;
287 +
288 + mmio->reset = 0xffffffff;
289 + udelay(1000);
290 + mmio->reset = 0xffe3cffe;
291 + mmio->pci_holdoff = 0x08000010;
292 + mmio->pci_arb_control = 0x00fac688;
293 +
294 + /* I/O routing */
295 + /* Mike 03000000; LineIn 05000000 */
296 + mmio->adc_control = 0x03000000;
297 + chip->rt_adc = 0x03000000;
298 +
299 + /* Default */
300 + mmio->dac_control = 0x20000000;
301 +
302 + /* Optical In 00000018; AES In 00000010 */
303 + mmio->aes_rx_control = 0x00000018;
304 + chip->rt_aesr = 0x00000018;
305 +
306 + /* Default */
307 + mmio->aes_tx_control = 0x40000000;
308 +
309 + /* Disabled a0000000; Optical In a0000018 */
310 + mmio->adat_rx_control = 0xa0000000;
311 + chip->rt_adat = 0xa0000000;
312 +
313 + /* Default */
314 + mmio->adat_tx_control = 0x20000000;
315 + mmio->gpio3 = 0x00000002;
316 + mmio->misc_control = 0x00001500;
317 + mmio->mpll0_lock_control = 0x9fffffff;
318 + mmio->mpll1_lock_control = 0x9fffffff;
319 + mmio->reset = 0xffe3c0fe;
320 + udelay(1000);
321 + mmio->clockgen_ictl = 0x02000001;
322 + mmio->reset = 0xffe24070;
323 + udelay(1000);
324 + mmio->reset = 0xffe20000;
325 + mmio->gpio2 = 0x00000002;
326 + mmio->volume_control = 0xd6d6d6d6;
327 + chip->attctrl = 0xd6d6d6d6;
328 + udelay(1000);
329 +
330 + /* AES-Optical Out 00001040; AES-AES Out 00001440 */
331 + mmio->misc_control = 0x00001040;
332 + chip->rt_opto = 0x00001040;
333 + mmio->reset = 0xffe20100;
334 + mmio->freq_synth_mux_sel[3] = 0x00000001;
335 + mmio->clockgen_rem = 0x0000ffff;
336 + mmio->clockgen_ictl = 0x10000603;
337 + mmio->reset = 0xffe20000;
338 + mmio->reset = 0xffe20200;
339 + mmio->freq_synth_mux_sel[2] = 0x00000001;
340 + mmio->clockgen_rem = 0x0000ffff;
341 + mmio->clockgen_ictl = 0x20000603;
342 + mmio->reset = 0xffe20000;
343 + mmio->reset = 0xffe20400;
344 + mmio->freq_synth_mux_sel[1] = 0x00000001;
345 + mmio->clockgen_rem = 0x0000ffff;
346 + mmio->clockgen_ictl = 0x40000603;
347 + mmio->reset = 0xffe20000;
348 + mmio->reset = 0xffe20800;
349 + mmio->freq_synth_mux_sel[0] = 0x00000001;
350 + mmio->clockgen_rem = 0x0000ffff;
351 + mmio->clockgen_ictl = 0x80000603;
352 + mmio->reset = 0xffe20000;
353 + mmio->gpio1 = 0x00000003;
354 + udelay(10000);
355 +}
356 +
357 +static void
358 +snd_rad1_setup_dma_pipe(struct snd_rad1 *chip, int pidx)
359 +{
360 + struct snd_rad1_pipe *pipe = (chip->pipes + pidx);
361 + volatile struct rad1regs *mmio = chip->mmio;
362 +
363 + if ((-pipe->pnum * pipe->plen) & 0x7f)
364 + printk(KERN_WARNING "rad1: pipe %d has unaligned size %d\n",
365 + pidx, (pipe->pnum * pipe->plen));
366 +
367 + mmio->pci_descr[pidx].hiadr = (pipe->pma >> 32);
368 + mmio->pci_descr[pidx].loadr = (pipe->pma & 0xffffffff);
369 + mmio->pci_descr[pidx].control = (((-pipe->pnum * pipe->plen) &
370 + 0xffffff80) | (pidx << 3));
371 +
372 + mmio->pci_hiadr[pidx] = (pipe->pma >> 32);
373 + mmio->pci_lc[pidx].loadr = (pipe->pma & 0xffffffff);
374 + mmio->pci_lc[pidx].control = (((-pipe->pnum * pipe->plen) &
375 + 0xffffff80) | (pidx << 3));
376 +}
377 +
378 +static void
379 +snd_rad1_activate_timer(struct snd_rad1 *chip)
380 +{
381 + if (!chip->timer_active) {
382 + chip->timer.expires = (jiffies + 1);
383 + add_timer(&chip->timer);
384 + chip->timer_active = 1;
385 + }
386 +}
387 +
388 +static void
389 +snd_rad1_run_pipe(struct snd_rad1 *chip, int pidx, int adma)
390 +{
391 + struct snd_rad1_pipe *pipe = (chip->pipes + pidx);
392 + volatile struct rad1regs *mmio = chip->mmio;
393 +
394 + if (pipe->adma != adma) {
395 + pipe->adma = adma;
396 +
397 + switch (pidx) {
398 + case RAD1_ADC:
399 + mmio->adc_control = (chip->rt_adc | adma);
400 + break;
401 + case RAD1_DAC:
402 + mmio->dac_control = (0x20000000 | adma);
403 + break;
404 + case RAD1_AESRX:
405 + mmio->aes_rx_control = (chip->rt_aesr | adma);
406 + break;
407 + case RAD1_AESTX:
408 + mmio->aes_tx_control = (0x40000000 | adma);
409 + break;
410 + }
411 + }
412 +
413 + if (adma)
414 + snd_rad1_activate_timer(chip);
415 +}
416 +
417 +static void
418 +snd_rad1_poll_pipe(struct snd_rad1 *chip, int pidx, int is_tx)
419 +{
420 + struct snd_rad1_pipe *pipe = (chip->pipes + pidx);
421 + unsigned long flags;
422 + unsigned int hptr = (pipe->pnum * pipe->plen) +
423 + (chip->mmio->pci_lc[pidx].control & 0xffffff80);
424 +
425 + spin_lock_irqsave(&chip->lock, flags);
426 + if (pipe->adma && pipe->subs) {
427 + /* use hardware pointer to detect period crossing */
428 + if ((hptr / pipe->plen) != (pipe->hptr / pipe->plen)) {
429 + if (is_tx)
430 + pipe->qptr = (hptr / 8);
431 + else
432 + pipe->qptr = (pipe->hptr / 8);
433 + spin_unlock_irqrestore(&chip->lock, flags);
434 + snd_pcm_period_elapsed(pipe->subs);
435 + spin_lock_irqsave(&chip->lock, flags);
436 + }
437 + pipe->hptr = hptr;
438 + }
439 + spin_unlock_irqrestore(&chip->lock, flags);
440 +}
441 +
442 +static void
443 +snd_rad1_poll_timer(struct timer_list *chip_virt)
444 +{
445 + struct snd_rad1 *chip = from_timer(chip, chip_virt, timer);
446 + int adma = 0;
447 +
448 + if (chip->pipes[RAD1_ADC].adma) {
449 + snd_rad1_poll_pipe(chip, RAD1_ADC, 0);
450 + adma = 1;
451 + }
452 +
453 + if (chip->pipes[RAD1_DAC].adma) {
454 + snd_rad1_poll_pipe(chip, RAD1_DAC, 1);
455 + adma = 1;
456 + }
457 +
458 + if (chip->pipes[RAD1_AESRX].adma) {
459 + snd_rad1_poll_pipe(chip, RAD1_AESRX, 0);
460 + adma = 1;
461 + }
462 +
463 + if (chip->pipes[RAD1_AESTX].adma) {
464 + snd_rad1_poll_pipe(chip, RAD1_AESTX, 1);
465 + adma = 1;
466 + }
467 +
468 + if (adma) {
469 + chip->timer.expires = (jiffies + 1);
470 + add_timer(&chip->timer);
471 + } else
472 + chip->timer_active = 0;
473 +}
474 +
475 +static int
476 +snd_rad1_free_pipe(struct snd_pcm_substream *substream, int pidx)
477 +{
478 + struct snd_rad1 *chip = snd_pcm_substream_chip(substream);
479 + struct snd_rad1_pipe *pipe = (chip->pipes + pidx);
480 + unsigned long flags;
481 +
482 + spin_lock_irqsave(&chip->lock, flags);
483 + snd_rad1_run_pipe(chip, pidx, 0);
484 + pipe->subs = NULL;
485 + spin_unlock_irqrestore(&chip->lock, flags);
486 +
487 + return snd_pcm_lib_free_pages(substream);
488 +}
489 +
490 +static inline long
491 +snd_rad1_gcd(long x, long y)
492 +{
493 + long t;
494 +
495 + if (x < y) {
496 + t = x;
497 + x = y;
498 + y = t;
499 + }
500 +
501 + while (y) {
502 + y = x % (t = y);
503 + x = t;
504 + }
505 +
506 + return x;
507 +}
508 +
509 +static void
510 +snd_rad1_red_frac(long *n, long *d, long max)
511 +{
512 + long gcd = snd_rad1_gcd(*n, *d);
513 +
514 + if (unlikely(!gcd))
515 + return;
516 +
517 + *n /= gcd;
518 + *d /= gcd;
519 +
520 + /* XXX: Lose precision [sic] */
521 + while ((*n > max) || (*d > max)) {
522 + *n >>= 1;
523 + *d >>= 1;
524 + }
525 +}
526 +
527 +static void
528 +snd_rad1_set_aestx_subcode(struct snd_rad1 *chip, unsigned char *sub_lc,
529 + unsigned char *sub_rc)
530 +{
531 + volatile struct rad1regs *mmio = chip->mmio;
532 + unsigned int i, j, lc[6], rc[6];
533 +
534 + for (i = 0; i < 6; i++) {
535 + lc[i] = 0;
536 + rc[i] = 0;
537 + for (j = 0; j < 4; j++) {
538 + lc[i] |= (sub_lc[i * 4 + j] << (j << 3));
539 + rc[i] |= (sub_rc[i * 4 + j] << (j << 3));
540 + }
541 + }
542 +
543 + for (i = 0; i < 6; i++) {
544 + mmio->aes_subcode_txa_lu[i] = 0x00000000;
545 + mmio->aes_subcode_txa_lc[i] = lc[i];
546 + mmio->aes_subcode_txa_lv[i] = 0x00000000;
547 + mmio->aes_subcode_txa_ru[i] = 0x00000000;
548 + mmio->aes_subcode_txa_rc[i] = rc[i];
549 + mmio->aes_subcode_txb_lu[i] = 0x00000000;
550 + mmio->aes_subcode_txb_lc[i] = lc[i];
551 + mmio->aes_subcode_txb_lv[i] = 0x00000000;
552 + mmio->aes_subcode_txb_ru[i] = 0x00000000;
553 + mmio->aes_subcode_txb_rc[i] = rc[i];
554 + }
555 +
556 + for (i = 0; i < 2; i++) {
557 + mmio->aes_subcode_txa_rv0[i] = 0x00000000;
558 + mmio->aes_subcode_txb_rv0[i] = 0x00000000;
559 + }
560 +
561 + for (i = 0; i < 4; i++) {
562 + mmio->aes_subcode_txa_rv2[i] = 0x00000000;
563 + mmio->aes_subcode_txb_rv2[i] = 0x00000000;
564 + }
565 +}
566 +
567 +static void
568 +snd_rad1_genset_aestx_subcode(struct snd_rad1 *chip, int rate)
569 +{
570 + int i;
571 + unsigned char lc[24], rc[24];
572 +
573 + for (i = 0; i < 24; i++) {
574 + lc[i] = 0x00;
575 + rc[i] = 0x00;
576 + }
577 +
578 + lc[0] = 0x04; /* PRO=0, !AUDIO=0, COPY=1, PRE=000, MODE=00 */
579 + rc[0] = 0x04;
580 + lc[1] = 0x01; /* Laser Optical, CD IEC-908 */
581 + rc[1] = 0x01;
582 + lc[2] = 0x10; /* SOURCE=0000, CHANNEL=0001 */
583 + rc[2] = 0x20; /* SOURCE=0000, CHANNEL=0010 */
584 +
585 + /*
586 + * RAD1 systems have generally decent clock sources,
587 + * so we mark them as Level I
588 + */
589 + switch (rate) {
590 + case 32000:
591 + lc[3] = 0x0c; /* Level I, 32 kHz */
592 + rc[3] = 0x0c;
593 + break;
594 + case 44100:
595 + lc[3] = 0x00; /* Level I, 44.1 kHz */
596 + rc[3] = 0x00;
597 + break;
598 + case 48000:
599 + lc[3] = 0x04; /* Level I, 48 kHz */
600 + rc[3] = 0x04;
601 + break;
602 + default:
603 + /* Not a valid IEC-958 sample rate */
604 + lc[3] = 0x10; /* Level III, 44.1 kHz */
605 + rc[3] = 0x10;
606 + }
607 + snd_rad1_set_aestx_subcode(chip, lc, rc);
608 +}
609 +
610 +static void
611 +snd_rad1_set_cg(struct snd_rad1 *chip, int cg, long rate,
612 + long base, unsigned muxsel)
613 +{
614 + volatile struct rad1regs *mmio = chip->mmio;
615 + long div, rem;
616 + unsigned flags;
617 +
618 + snd_rad1_red_frac(&base, &rate, 0xffff);
619 + div = (base / rate);
620 + rem = (base % rate);
621 + snd_rad1_red_frac(&rem, &rate, 0xffff);
622 + flags = (((rem * 2) < rate) ? 0x600 : 0x200);
623 +
624 + mmio->reset = 0xffe20000 | (0x100 << cg);
625 + mmio->freq_synth_mux_sel[3 - cg] = muxsel;
626 + mmio->clockgen_rem = (rem << 16) | (0x10000 - rate);
627 + mmio->clockgen_ictl = (flags | (0x10000000 << cg) | (div - 1));
628 + mmio->reset = 0xffe20000;
629 +}
630 +
631 +/* Select best master clock source for low jitter */
632 +static inline void
633 +snd_rad1_set_cgms(struct snd_rad1 *chip, int cg, long rate)
634 +{
635 + if (!(176400 % rate))
636 + snd_rad1_set_cg(chip, cg, rate, 176400, 0);
637 + else
638 + snd_rad1_set_cg(chip, cg, rate, 192000, 1);
639 +}
640 +
641 +static inline void
642 +snd_rad1_setrate_pipe(struct snd_rad1 *chip, int pidx, int rate)
643 +{
644 + if (pidx == RAD1_ADC)
645 + snd_rad1_set_cgms(chip, 0, rate);
646 +
647 + if (pidx == RAD1_DAC)
648 + snd_rad1_set_cgms(chip, 1, rate);
649 +
650 + if (pidx == RAD1_AESTX) {
651 + snd_rad1_set_cgms(chip, 2, rate);
652 + snd_rad1_genset_aestx_subcode(chip, rate);
653 + }
654 +}
655 +
656 +static int
657 +snd_rad1_prepare_pipe(struct snd_pcm_substream *substream, int pidx)
658 +{
659 + struct snd_rad1 *chip = snd_pcm_substream_chip(substream);
660 + struct snd_pcm_runtime *runtime = substream->runtime;
661 + struct snd_rad1_pipe *pipe = (chip->pipes + pidx);
662 + unsigned long flags;
663 +
664 + spin_lock_irqsave(&chip->lock, flags);
665 + snd_rad1_run_pipe(chip, pidx, 0);
666 + spin_unlock_irqrestore(&chip->lock, flags);
667 +
668 + pipe->subs = substream;
669 + pipe->vma = (int *)runtime->dma_area;
670 + pipe->pma = runtime->dma_addr;
671 + pipe->pnum = runtime->periods;
672 + pipe->plen = frames_to_bytes(runtime, runtime->period_size);
673 +
674 + snd_rad1_setrate_pipe(chip, pidx, runtime->rate);
675 +
676 + pipe->hptr = 0;
677 + pipe->qptr = 0;
678 + snd_rad1_setup_dma_pipe(chip, pidx);
679 +
680 + return 0;
681 +}
682 +
683 +static void
684 +snd_rad1_detect_aesrx_rate(struct snd_rad1 *chip, struct snd_pcm_hardware *hw)
685 +{
686 + int rate;
687 + unsigned sc = (((chip->mmio->chip_status0) >> 24) & 7);
688 + static int rates[8] = {0, 48000, 44100, 32000, 48000,
689 + 44100, 44056, 32000};
690 +
691 + if (!rates[sc]) {
692 + printk(KERN_INFO "rad1: Warning: Recording from an unlocked "
693 + "IEC958 source. Assuming sample rate: %d.\n",
694 + chip->last_aesrx_rate);
695 + rate = chip->last_aesrx_rate;
696 + } else
697 + rate = rates[sc];
698 +
699 + chip->last_aesrx_rate = rate;
700 + hw->rate_min = rate;
701 + hw->rate_max = rate;
702 +
703 + switch (rate) {
704 + case 32000:
705 + hw->rates = SNDRV_PCM_RATE_32000;
706 + break;
707 + case 44056:
708 + hw->rates = SNDRV_PCM_RATE_CONTINUOUS;
709 + break;
710 + case 48000:
711 + hw->rates = SNDRV_PCM_RATE_48000;
712 + case 44100:
713 + default:
714 + hw->rates = SNDRV_PCM_RATE_44100;
715 + break;
716 + }
717 +}
718 +
719 +static int
720 +snd_rad1_trigger_pipe(struct snd_pcm_substream *substream, int pidx, int cmd)
721 +{
722 + struct snd_rad1 *chip = snd_pcm_substream_chip(substream);
723 + int result = 0;
724 +
725 + switch (cmd) {
726 + case SNDRV_PCM_TRIGGER_START:
727 + case SNDRV_PCM_TRIGGER_RESUME:
728 + snd_rad1_run_pipe(chip, pidx, 1);
729 + break;
730 + case SNDRV_PCM_TRIGGER_STOP:
731 + case SNDRV_PCM_TRIGGER_SUSPEND:
732 + snd_rad1_run_pipe(chip, pidx, 0);
733 + break;
734 + default:
735 + result = -EINVAL;
736 + }
737 +
738 + return result;
739 +}
740 +
741 +static snd_pcm_uframes_t
742 +snd_rad1_ptr_pipe(struct snd_pcm_substream *substream, int pidx)
743 +{
744 + struct snd_rad1 *chip = snd_pcm_substream_chip(substream);
745 +
746 + return chip->pipes[pidx].qptr;
747 +}
748 +
749 +/* ----------------------------------------------------------------------- */
750 +
751 +
752 +/* ----------------------------------------------------------------------- */
753 +/* ADC pipe */
754 +static struct snd_pcm_hardware
755 +snd_rad1_adc_hw = {
756 + .info = (SNDRV_PCM_INFO_INTERLEAVED |
757 + SNDRV_PCM_INFO_MMAP |
758 + SNDRV_PCM_INFO_MMAP_VALID |
759 + SNDRV_PCM_INFO_BLOCK_TRANSFER),
760 + .rates = (SNDRV_PCM_RATE_CONTINUOUS |
761 + SNDRV_PCM_RATE_32000 |
762 + SNDRV_PCM_RATE_44100 |
763 + SNDRV_PCM_RATE_48000),
764 + .formats = SNDRV_PCM_FMTBIT_S24_BE,
765 + .rate_min = 32000,
766 + .rate_max = 48000,
767 + .channels_min = 2,
768 + .channels_max = 2,
769 + .buffer_bytes_max = 1048576,
770 + .period_bytes_min = 4096,
771 + .period_bytes_max = 4096,
772 + .periods_min = 4,
773 + .periods_max = 256,
774 +};
775 +
776 +static int
777 +snd_rad1_adc_open(struct snd_pcm_substream *substream)
778 +{
779 + struct snd_pcm_runtime *runtime = substream->runtime;
780 +
781 + runtime->hw = snd_rad1_adc_hw;
782 +
783 + return 0;
784 +}
785 +
786 +static int
787 +snd_rad1_adc_close(struct snd_pcm_substream *substream)
788 +{
789 + struct snd_rad1 *chip = snd_pcm_substream_chip(substream);
790 +
791 + snd_rad1_run_pipe(chip, RAD1_ADC, 0);
792 +
793 + return 0;
794 +}
795 +
796 +static int
797 +snd_rad1_adc_params(struct snd_pcm_substream *substream,
798 + struct snd_pcm_hw_params *hw_params)
799 +{
800 + return snd_pcm_lib_malloc_pages(substream,
801 + params_buffer_bytes(hw_params));
802 +}
803 +
804 +static int
805 +snd_rad1_adc_free(struct snd_pcm_substream *substream)
806 +{
807 + return snd_rad1_free_pipe(substream, RAD1_ADC);
808 +}
809 +
810 +static int
811 +snd_rad1_adc_prepare(struct snd_pcm_substream *substream)
812 +{
813 + return snd_rad1_prepare_pipe(substream, RAD1_ADC);
814 +}
815 +
816 +static int
817 +snd_rad1_adc_trigger(struct snd_pcm_substream *substream, int cmd)
818 +{
819 + return snd_rad1_trigger_pipe(substream, RAD1_ADC, cmd);
820 +}
821 +
822 +static snd_pcm_uframes_t
823 +snd_rad1_adc_ptr(struct snd_pcm_substream *substream)
824 +{
825 + return snd_rad1_ptr_pipe(substream, RAD1_ADC);
826 +}
827 +
828 +static struct snd_pcm_ops
829 +snd_rad1_adc_ops = {
830 + .open = snd_rad1_adc_open,
831 + .close = snd_rad1_adc_close,
832 + .hw_params = snd_rad1_adc_params,
833 + .hw_free = snd_rad1_adc_free,
834 + .prepare = snd_rad1_adc_prepare,
835 + .trigger = snd_rad1_adc_trigger,
836 + .pointer = snd_rad1_adc_ptr,
837 + .ioctl = snd_pcm_lib_ioctl,
838 +};
839 +
840 +static void
841 +snd_rad1_adc_pcm_free(struct snd_pcm *pcm)
842 +{
843 + snd_pcm_lib_preallocate_free_for_all(pcm);
844 +}
845 +
846 +static int
847 +snd_rad1_new_adc(struct snd_rad1 *chip, int dev)
848 +{
849 + struct snd_pcm *pcm;
850 + int err;
851 +
852 + err = snd_pcm_new(chip->card, "RAD1 ADC", dev, 0, 1, &pcm);
853 + if (unlikely(err < 0))
854 + return err;
855 +
856 + pcm->private_data = chip;
857 + pcm->private_free = snd_rad1_adc_pcm_free;
858 + strlcpy(pcm->name, "RAD1 ADC", sizeof(pcm->name));
859 + chip->pipes[RAD1_ADC].pcm = pcm;
860 + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rad1_adc_ops);
861 + snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
862 + snd_dma_pci_data(chip->pci),
863 + 65536, 65536);
864 +
865 + return 0;
866 +}
867 +
868 +/* ----------------------------------------------------------------------- */
869 +
870 +
871 +/* ----------------------------------------------------------------------- */
872 +/* DAC pipe */
873 +static struct
874 +snd_pcm_hardware snd_rad1_dac_hw = {
875 + .info = (SNDRV_PCM_INFO_INTERLEAVED |
876 + SNDRV_PCM_INFO_MMAP |
877 + SNDRV_PCM_INFO_MMAP_VALID |
878 + SNDRV_PCM_INFO_BLOCK_TRANSFER),
879 + .rates = (SNDRV_PCM_RATE_CONTINUOUS |
880 + SNDRV_PCM_RATE_32000 |
881 + SNDRV_PCM_RATE_44100 |
882 + SNDRV_PCM_RATE_48000),
883 + .formats = SNDRV_PCM_FMTBIT_S24_BE,
884 + .rate_min = 32000,
885 + .rate_max = 48000,
886 + .channels_min = 2,
887 + .channels_max = 2,
888 + .buffer_bytes_max = 1048576,
889 + .period_bytes_min = 4096,
890 + .period_bytes_max = 4096,
891 + .periods_min = 4,
892 + .periods_max = 256,
893 +};
894 +
895 +static int
896 +snd_rad1_dac_open(struct snd_pcm_substream *substream)
897 +{
898 + struct snd_pcm_runtime *runtime = substream->runtime;
899 +
900 + runtime->hw = snd_rad1_dac_hw;
901 +
902 + return 0;
903 +}
904 +
905 +static int
906 +snd_rad1_dac_close(struct snd_pcm_substream *substream)
907 +{
908 + struct snd_rad1 *chip = snd_pcm_substream_chip(substream);
909 +
910 + snd_rad1_run_pipe(chip, RAD1_DAC, 0);
911 +
912 + return 0;
913 +}
914 +
915 +static int
916 +snd_rad1_dac_params(struct snd_pcm_substream *substream,
917 + struct snd_pcm_hw_params *hw_params)
918 +{
919 + return snd_pcm_lib_malloc_pages(substream,
920 + params_buffer_bytes(hw_params));
921 +}
922 +
923 +static int
924 +snd_rad1_dac_free(struct snd_pcm_substream *substream)
925 +{
926 + return snd_rad1_free_pipe(substream, RAD1_DAC);
927 +}
928 +
929 +static int
930 +snd_rad1_dac_prepare(struct snd_pcm_substream *substream)
931 +{
932 + return snd_rad1_prepare_pipe(substream, RAD1_DAC);
933 +}
934 +
935 +static int
936 +snd_rad1_dac_trigger(struct snd_pcm_substream *substream, int cmd)
937 +{
938 + return snd_rad1_trigger_pipe(substream, RAD1_DAC, cmd);
939 +}
940 +
941 +static snd_pcm_uframes_t
942 +snd_rad1_dac_ptr(struct snd_pcm_substream *substream)
943 +{
944 + return snd_rad1_ptr_pipe(substream, RAD1_DAC);
945 +}
946 +
947 +static struct snd_pcm_ops
948 +snd_rad1_dac_ops = {
949 + .open = snd_rad1_dac_open,
950 + .close = snd_rad1_dac_close,
951 + .hw_params = snd_rad1_dac_params,
952 + .hw_free = snd_rad1_dac_free,
953 + .prepare = snd_rad1_dac_prepare,
954 + .trigger = snd_rad1_dac_trigger,
955 + .pointer = snd_rad1_dac_ptr,
956 + .ioctl = snd_pcm_lib_ioctl,
957 +};
958 +
959 +static void
960 +snd_rad1_dac_pcm_free(struct snd_pcm *pcm)
961 +{
962 + snd_pcm_lib_preallocate_free_for_all(pcm);
963 +}
964 +
965 +static int
966 +snd_rad1_new_dac(struct snd_rad1 *chip, int dev)
967 +{
968 + struct snd_pcm *pcm;
969 + int err;
970 +
971 + err = snd_pcm_new(chip->card, "RAD1 DAC", dev, 1, 0, &pcm);
972 + if (unlikely(err < 0))
973 + return err;
974 +
975 + pcm->private_data = chip;
976 + pcm->private_free = snd_rad1_dac_pcm_free;
977 + strlcpy(pcm->name, "RAD1 DAC", sizeof(pcm->name));
978 + chip->pipes[RAD1_DAC].pcm = pcm;
979 + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rad1_dac_ops);
980 + snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
981 + snd_dma_pci_data(chip->pci),
982 + 65536, 65536);
983 +
984 + return 0;
985 +}
986 +
987 +/* ----------------------------------------------------------------------- */
988 +
989 +
990 +/* ----------------------------------------------------------------------- */
991 +/* AESRX pipe */
992 +static struct snd_pcm_hardware
993 +snd_rad1_aesrx_hw = {
994 + .info = (SNDRV_PCM_INFO_INTERLEAVED |
995 + SNDRV_PCM_INFO_MMAP |
996 + SNDRV_PCM_INFO_MMAP_VALID |
997 + SNDRV_PCM_INFO_BLOCK_TRANSFER),
998 + .rates = (SNDRV_PCM_RATE_32000 |
999 + SNDRV_PCM_RATE_44100 |
1000 + SNDRV_PCM_RATE_48000),
1001 + .formats = SNDRV_PCM_FMTBIT_S24_BE,
1002 + .rate_min = 32000,
1003 + .rate_max = 48000,
1004 + .channels_min = 2,
1005 + .channels_max = 2,
1006 + .buffer_bytes_max = 1048576,
1007 + .period_bytes_min = 4096,
1008 + .period_bytes_max = 4096,
1009 + .periods_min = 4,
1010 + .periods_max = 256,
1011 +};
1012 +
1013 +static int
1014 +snd_rad1_aesrx_open(struct snd_pcm_substream *substream)
1015 +{
1016 + struct snd_pcm_runtime *runtime = substream->runtime;
1017 + struct snd_rad1 *chip = snd_pcm_substream_chip(substream);
1018 +
1019 + runtime->hw = snd_rad1_aesrx_hw;
1020 + snd_rad1_detect_aesrx_rate(chip, &runtime->hw);
1021 +
1022 + return 0;
1023 +}
1024 +
1025 +static int
1026 +snd_rad1_aesrx_close(struct snd_pcm_substream *substream)
1027 +{
1028 + struct snd_rad1 *chip = snd_pcm_substream_chip(substream);
1029 +
1030 + snd_rad1_run_pipe(chip, RAD1_AESRX, 0);
1031 +
1032 + return 0;
1033 +}
1034 +
1035 +static int
1036 +snd_rad1_aesrx_params(struct snd_pcm_substream *substream,
1037 + struct snd_pcm_hw_params *hw_params)
1038 +{
1039 + return snd_pcm_lib_malloc_pages(substream,
1040 + params_buffer_bytes(hw_params));
1041 +}
1042 +
1043 +static int
1044 +snd_rad1_aesrx_free(struct snd_pcm_substream *substream)
1045 +{
1046 + return snd_rad1_free_pipe(substream, RAD1_AESRX);
1047 +}
1048 +
1049 +static int
1050 +snd_rad1_aesrx_prepare(struct snd_pcm_substream *substream)
1051 +{
1052 + return snd_rad1_prepare_pipe(substream, RAD1_AESRX);
1053 +}
1054 +
1055 +static int
1056 +snd_rad1_aesrx_trigger(struct snd_pcm_substream *substream, int cmd)
1057 +{
1058 + return snd_rad1_trigger_pipe(substream, RAD1_AESRX, cmd);
1059 +}
1060 +
1061 +static snd_pcm_uframes_t
1062 +snd_rad1_aesrx_ptr(struct snd_pcm_substream *substream)
1063 +{
1064 + return snd_rad1_ptr_pipe(substream, RAD1_AESRX);
1065 +}
1066 +
1067 +static struct snd_pcm_ops
1068 +snd_rad1_aesrx_ops = {
1069 + .open = snd_rad1_aesrx_open,
1070 + .close = snd_rad1_aesrx_close,
1071 + .hw_params = snd_rad1_aesrx_params,
1072 + .hw_free = snd_rad1_aesrx_free,
1073 + .prepare = snd_rad1_aesrx_prepare,
1074 + .trigger = snd_rad1_aesrx_trigger,
1075 + .pointer = snd_rad1_aesrx_ptr,
1076 + .ioctl = snd_pcm_lib_ioctl,
1077 +};
1078 +
1079 +static void
1080 +snd_rad1_aesrx_pcm_free(struct snd_pcm *pcm)
1081 +{
1082 + snd_pcm_lib_preallocate_free_for_all(pcm);
1083 +}
1084 +
1085 +static int
1086 +snd_rad1_new_aesrx(struct snd_rad1 *chip, int dev)
1087 +{
1088 + struct snd_pcm *pcm;
1089 + int err;
1090 +
1091 + err = snd_pcm_new(chip->card, "RAD1 AES Rx", dev, 0, 1, &pcm);
1092 + if (unlikely(err < 0))
1093 + return err;
1094 +
1095 + pcm->private_data = chip;
1096 + pcm->private_free = snd_rad1_aesrx_pcm_free;
1097 + strlcpy(pcm->name, "RAD1 AES Rx", sizeof(pcm->name));
1098 + chip->pipes[RAD1_AESRX].pcm = pcm;
1099 + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rad1_aesrx_ops);
1100 + snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1101 + snd_dma_pci_data(chip->pci),
1102 + 65536, 65536);
1103 + chip->last_aesrx_rate = 44100;
1104 +
1105 + return 0;
1106 +}
1107 +
1108 +/* ----------------------------------------------------------------------- */
1109 +
1110 +
1111 +/* ----------------------------------------------------------------------- */
1112 +/* AESTX pipe */
1113 +static struct snd_pcm_hardware
1114 +snd_rad1_aestx_hw = {
1115 + .info = (SNDRV_PCM_INFO_INTERLEAVED |
1116 + SNDRV_PCM_INFO_MMAP |
1117 + SNDRV_PCM_INFO_MMAP_VALID |
1118 + SNDRV_PCM_INFO_BLOCK_TRANSFER),
1119 + .rates = (SNDRV_PCM_RATE_32000 |
1120 + SNDRV_PCM_RATE_44100 |
1121 + SNDRV_PCM_RATE_48000),
1122 + .formats = SNDRV_PCM_FMTBIT_S24_BE,
1123 + .rate_min = 32000,
1124 + .rate_max = 48000,
1125 + .channels_min = 2,
1126 + .channels_max = 2,
1127 + .buffer_bytes_max = 1048576,
1128 + .period_bytes_min = 4096,
1129 + .period_bytes_max = 4096,
1130 + .periods_min = 4,
1131 + .periods_max = 256,
1132 +};
1133 +
1134 +static int
1135 +snd_rad1_aestx_open(struct snd_pcm_substream *substream)
1136 +{
1137 + struct snd_pcm_runtime *runtime = substream->runtime;
1138 +
1139 + runtime->hw = snd_rad1_aestx_hw;
1140 +
1141 + return 0;
1142 +}
1143 +
1144 +static int
1145 +snd_rad1_aestx_close(struct snd_pcm_substream *substream)
1146 +{
1147 + struct snd_rad1 *chip = snd_pcm_substream_chip(substream);
1148 +
1149 + snd_rad1_run_pipe(chip, RAD1_AESTX, 0);
1150 +
1151 + return 0;
1152 +}
1153 +
1154 +static int
1155 +snd_rad1_aestx_params(struct snd_pcm_substream *substream,
1156 + struct snd_pcm_hw_params *hw_params)
1157 +{
1158 + return snd_pcm_lib_malloc_pages(substream,
1159 + params_buffer_bytes(hw_params));
1160 +}
1161 +
1162 +static int
1163 +snd_rad1_aestx_free(struct snd_pcm_substream *substream)
1164 +{
1165 + return snd_rad1_free_pipe(substream, RAD1_AESTX);
1166 +}
1167 +
1168 +static int
1169 +snd_rad1_aestx_prepare(struct snd_pcm_substream *substream)
1170 +{
1171 + return snd_rad1_prepare_pipe(substream, RAD1_AESTX);
1172 +}
1173 +
1174 +static int
1175 +snd_rad1_aestx_trigger(struct snd_pcm_substream *substream, int cmd)
1176 +{
1177 + return snd_rad1_trigger_pipe(substream, RAD1_AESTX, cmd);
1178 +}
1179 +
1180 +static snd_pcm_uframes_t
1181 +snd_rad1_aestx_ptr(struct snd_pcm_substream *substream)
1182 +{
1183 + return snd_rad1_ptr_pipe(substream, RAD1_AESTX);
1184 +}
1185 +
1186 +static struct snd_pcm_ops
1187 +snd_rad1_aestx_ops = {
1188 + .open = snd_rad1_aestx_open,
1189 + .close = snd_rad1_aestx_close,
1190 + .hw_params = snd_rad1_aestx_params,
1191 + .hw_free = snd_rad1_aestx_free,
1192 + .prepare = snd_rad1_aestx_prepare,
1193 + .trigger = snd_rad1_aestx_trigger,
1194 + .pointer = snd_rad1_aestx_ptr,
1195 + .ioctl = snd_pcm_lib_ioctl,
1196 +};
1197 +
1198 +static void
1199 +snd_rad1_aestx_pcm_free(struct snd_pcm *pcm)
1200 +{
1201 + snd_pcm_lib_preallocate_free_for_all(pcm);
1202 +}
1203 +
1204 +static int
1205 +snd_rad1_new_aestx(struct snd_rad1 *chip, int dev)
1206 +{
1207 + struct snd_pcm *pcm;
1208 + int err;
1209 +
1210 + err = snd_pcm_new(chip->card, "RAD1 AES Tx", dev, 1, 0, &pcm);
1211 + if (unlikely(err < 0))
1212 + return err;
1213 +
1214 + pcm->private_data = chip;
1215 + pcm->private_free = snd_rad1_aestx_pcm_free;
1216 + strlcpy(pcm->name, "RAD1 AES Tx", sizeof(pcm->name));
1217 + chip->pipes[RAD1_AESTX].pcm = pcm;
1218 + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rad1_aestx_ops);
1219 + snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1220 + snd_dma_pci_data(chip->pci),
1221 + 65536, 65536);
1222 +
1223 + return 0;
1224 +}
1225 +
1226 +/* ----------------------------------------------------------------------- */
1227 +
1228 +
1229 +/* ----------------------------------------------------------------------- */
1230 +/* Volume control */
1231 +static int
1232 +snd_rad1_control_pv_info(struct snd_kcontrol *kcontrol,
1233 + struct snd_ctl_elem_info *uinfo)
1234 +{
1235 + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1236 + uinfo->count = 2;
1237 + uinfo->value.integer.min = 0;
1238 + uinfo->value.integer.max = 255;
1239 +
1240 + return 0;
1241 +}
1242 +
1243 +static int
1244 +snd_rad1_control_pv_get(struct snd_kcontrol *kcontrol,
1245 + struct snd_ctl_elem_value *u)
1246 +{
1247 + int shift = (kcontrol->private_value * 16);
1248 + unsigned long flags;
1249 + struct snd_rad1 *chip = snd_kcontrol_chip(kcontrol);
1250 +
1251 + spin_lock_irqsave(&chip->lock, flags);
1252 + u->value.integer.value[0] = ((chip->attctrl >> shift) & 0xff);
1253 + u->value.integer.value[1] = ((chip->attctrl >> (8 + shift)) & 0xff);
1254 + spin_unlock_irqrestore(&chip->lock, flags);
1255 +
1256 + return 0;
1257 +}
1258 +
1259 +static int
1260 +snd_rad1_control_pv_put(struct snd_kcontrol *kcontrol,
1261 + struct snd_ctl_elem_value *u)
1262 +{
1263 + int change = 0;
1264 + int shift = (kcontrol->private_value * 16);
1265 + unsigned long flags;
1266 + struct snd_rad1 *chip = snd_kcontrol_chip(kcontrol);
1267 +
1268 + spin_lock_irqsave(&chip->lock, flags);
1269 + if (u->value.integer.value[0] != ((chip->attctrl >> shift) & 0xff))
1270 + change = 1;
1271 +
1272 + if (u->value.integer.value[1] != ((chip->attctrl >> (8 + shift)) & 0xff))
1273 + change = 1;
1274 +
1275 + if (change) {
1276 + chip->attctrl &= (0xffff << (16 - shift));
1277 + chip->attctrl |= (u->value.integer.value[0] << shift);
1278 + chip->attctrl |= (u->value.integer.value[1] << (8 + shift));
1279 + chip->mmio->volume_control = chip->attctrl;
1280 + }
1281 + spin_unlock_irqrestore(&chip->lock, flags);
1282 +
1283 + return change;
1284 +}
1285 +
1286 +/* ----------------------------------------------------------------------- */
1287 +
1288 +
1289 +/* ----------------------------------------------------------------------- */
1290 +/* AES Tx route control */
1291 +static int
1292 +snd_rad1_control_tr_info(struct snd_kcontrol *kcontrol,
1293 + struct snd_ctl_elem_info *uinfo)
1294 +{
1295 + static char *rts[2] = {"Optical", "Coaxial"};
1296 +
1297 + uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1298 + uinfo->count = 1;
1299 + uinfo->value.enumerated.items = 2;
1300 +
1301 + if (uinfo->value.enumerated.item > 1)
1302 + uinfo->value.enumerated.item = 1;
1303 +
1304 + strlcpy(uinfo->value.enumerated.name,
1305 + rts[uinfo->value.enumerated.item],
1306 + sizeof(uinfo->value.enumerated.name));
1307 +
1308 + return 0;
1309 +}
1310 +
1311 +static int
1312 +snd_rad1_control_tr_get(struct snd_kcontrol *kcontrol,
1313 + struct snd_ctl_elem_value *u)
1314 +{
1315 + unsigned long flags;
1316 + struct snd_rad1 *chip = snd_kcontrol_chip(kcontrol);
1317 +
1318 + spin_lock_irqsave(&chip->lock, flags);
1319 + if (chip->rt_opto == 0x00001440)
1320 + u->value.enumerated.item[0] = 1;
1321 + else
1322 + u->value.enumerated.item[0] = 0;
1323 + spin_unlock_irqrestore(&chip->lock, flags);
1324 +
1325 + return 0;
1326 +}
1327 +
1328 +static int
1329 +snd_rad1_control_tr_put(struct snd_kcontrol *kcontrol,
1330 + struct snd_ctl_elem_value *u)
1331 +{
1332 + int change = 0;
1333 + unsigned long flags;
1334 + struct snd_rad1 *chip = snd_kcontrol_chip(kcontrol);
1335 +
1336 + spin_lock_irqsave(&chip->lock, flags);
1337 + if (u->value.enumerated.item[0] && (chip->rt_opto != 0x00001440))
1338 + change = 1;
1339 +
1340 + if (!u->value.enumerated.item[0] && (chip->rt_opto == 0x00001440))
1341 + change = 1;
1342 +
1343 + if (change) {
1344 + if (u->value.enumerated.item[0])
1345 + chip->rt_opto = 0x00001440;
1346 + else
1347 + chip->rt_opto = 0x00001040;
1348 + chip->mmio->misc_control = chip->rt_opto;
1349 + }
1350 + spin_unlock_irqrestore(&chip->lock, flags);
1351 +
1352 + return change;
1353 +}
1354 +
1355 +/* ----------------------------------------------------------------------- */
1356 +
1357 +
1358 +/* ----------------------------------------------------------------------- */
1359 +/* AES Rx route control */
1360 +static int
1361 +snd_rad1_control_rr_get(struct snd_kcontrol *kcontrol,
1362 + struct snd_ctl_elem_value *u)
1363 +{
1364 + struct snd_rad1 *chip = snd_kcontrol_chip(kcontrol);
1365 + unsigned long flags;
1366 +
1367 + spin_lock_irqsave(&chip->lock, flags);
1368 + if (chip->rt_aesr == 0x00000010)
1369 + u->value.enumerated.item[0] = 1;
1370 + else
1371 + u->value.enumerated.item[0] = 0;
1372 + spin_unlock_irqrestore(&chip->lock, flags);
1373 +
1374 + return 0;
1375 +}
1376 +
1377 +static int
1378 +snd_rad1_control_rr_put(struct snd_kcontrol *kcontrol,
1379 + struct snd_ctl_elem_value *u)
1380 +{
1381 + struct snd_rad1 *chip = snd_kcontrol_chip(kcontrol);
1382 + unsigned long flags;
1383 + int change = 0;
1384 +
1385 + spin_lock_irqsave(&chip->lock, flags);
1386 + if (u->value.enumerated.item[0] && (chip->rt_aesr != 0x00000010))
1387 + change = 1;
1388 +
1389 + if (!u->value.enumerated.item[0] && (chip->rt_aesr == 0x00000010))
1390 + change = 1;
1391 +
1392 + if (change) {
1393 + if (u->value.enumerated.item[0]) {
1394 + chip->rt_aesr = 0x00000010;
1395 + chip->rt_adat = 0xa0000018;
1396 + } else {
1397 + chip->rt_aesr = 0x00000018;
1398 + chip->rt_adat = 0xa0000000;
1399 + }
1400 + chip->mmio->aes_rx_control = (chip->rt_aesr |
1401 + chip->pipes[RAD1_AESRX].adma);
1402 + chip->mmio->adat_rx_control = (chip->rt_adat |
1403 + chip->pipes[RAD1_ADATRX].adma);
1404 + }
1405 + spin_unlock_irqrestore(&chip->lock, flags);
1406 +
1407 + return change;
1408 +}
1409 +
1410 +
1411 +/* ----------------------------------------------------------------------- */
1412 +
1413 +
1414 +/* ----------------------------------------------------------------------- */
1415 +/* ADC route control */
1416 +static int
1417 +snd_rad1_control_ar_info(struct snd_kcontrol *kcontrol,
1418 + struct snd_ctl_elem_info *uinfo)
1419 +{
1420 + static char *rts[2] = {"Mic", "Line"};
1421 +
1422 + uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1423 + uinfo->count = 1;
1424 + uinfo->value.enumerated.items = 2;
1425 +
1426 + if (uinfo->value.enumerated.item > 1)
1427 + uinfo->value.enumerated.item = 1;
1428 +
1429 + strlcpy(uinfo->value.enumerated.name,
1430 + rts[uinfo->value.enumerated.item],
1431 + sizeof(uinfo->value.enumerated.name));
1432 +
1433 + return 0;
1434 +}
1435 +
1436 +static int
1437 +snd_rad1_control_ar_get(struct snd_kcontrol *kcontrol,
1438 + struct snd_ctl_elem_value *u)
1439 +{
1440 + struct snd_rad1 *chip = snd_kcontrol_chip(kcontrol);
1441 + unsigned long flags;
1442 +
1443 + spin_lock_irqsave(&chip->lock, flags);
1444 + if (chip->rt_adc == 0x05000000)
1445 + u->value.enumerated.item[0] = 1;
1446 + else
1447 + u->value.enumerated.item[0] = 0;
1448 + spin_unlock_irqrestore(&chip->lock, flags);
1449 +
1450 + return 0;
1451 +}
1452 +
1453 +static int
1454 +snd_rad1_control_ar_put(struct snd_kcontrol *kcontrol,
1455 + struct snd_ctl_elem_value *u)
1456 +{
1457 + struct snd_rad1 *chip = snd_kcontrol_chip(kcontrol);
1458 + unsigned long flags;
1459 + int change = 0;
1460 +
1461 + spin_lock_irqsave(&chip->lock, flags);
1462 + if (u->value.enumerated.item[0] && (chip->rt_adc != 0x05000000))
1463 + change = 1;
1464 +
1465 + if (!u->value.enumerated.item[0] && (chip->rt_adc == 0x05000000))
1466 + change = 1;
1467 +
1468 + if (change) {
1469 + if (u->value.enumerated.item[0])
1470 + chip->rt_adc = 0x05000000;
1471 + else
1472 + chip->rt_adc = 0x03000000;
1473 + chip->mmio->adc_control = (chip->rt_adc |
1474 + chip->pipes[RAD1_ADC].adma);
1475 + }
1476 + spin_unlock_irqrestore(&chip->lock, flags);
1477 +
1478 + return change;
1479 +}
1480 +
1481 +/* ----------------------------------------------------------------------- */
1482 +
1483 +
1484 +/* ----------------------------------------------------------------------- */
1485 +/* Controls */
1486 +static struct snd_kcontrol_new
1487 +snd_rad1_controls[] = {
1488 + {
1489 + .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1490 + .name = "Master Playback Volume",
1491 + .info = snd_rad1_control_pv_info,
1492 + .get = snd_rad1_control_pv_get,
1493 + .put = snd_rad1_control_pv_put,
1494 + .private_value = 1
1495 + },
1496 + {
1497 + .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1498 + .name = "Line Capture Volume",
1499 + .info = snd_rad1_control_pv_info,
1500 + .get = snd_rad1_control_pv_get,
1501 + .put = snd_rad1_control_pv_put,
1502 + .private_value = 0
1503 + },
1504 + {
1505 + .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1506 + .name = "IEC958 Playback Routing",
1507 + .info = snd_rad1_control_tr_info,
1508 + .get = snd_rad1_control_tr_get,
1509 + .put = snd_rad1_control_tr_put
1510 + },
1511 + {
1512 + .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1513 + .name = "IEC958 Capture Routing",
1514 + .info = snd_rad1_control_tr_info, /* clone */
1515 + .get = snd_rad1_control_rr_get,
1516 + .put = snd_rad1_control_rr_put
1517 + },
1518 + {
1519 + .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1520 + .name = "Line Capture Routing",
1521 + .info = snd_rad1_control_ar_info,
1522 + .get = snd_rad1_control_ar_get,
1523 + .put = snd_rad1_control_ar_put
1524 + },
1525 +};
1526 +
1527 +static int
1528 +snd_rad1_add_controls(struct snd_rad1 *chip)
1529 +{
1530 + int idx, err;
1531 +
1532 + for (idx = 0; idx < 5; idx++) {
1533 + err = snd_ctl_add(chip->card,
1534 + snd_ctl_new1(&snd_rad1_controls[idx], chip));
1535 + if (unlikely(err < 0))
1536 + return err;
1537 + }
1538 +
1539 + return 0;
1540 +}
1541 +
1542 +/* ----------------------------------------------------------------------- */
1543 +
1544 +
1545 +/* ----------------------------------------------------------------------- */
1546 +/* Create/Probe/Free/Module */
1547 +
1548 +static int
1549 +snd_rad1_free(struct snd_rad1 *chip)
1550 +{
1551 + if (chip->mmio) {
1552 + iounmap((void *)(chip->mmio));
1553 + chip->mmio = NULL;
1554 + }
1555 + kfree(chip);
1556 +
1557 + return 0;
1558 +}
1559 +
1560 +static int
1561 +snd_rad1_dev_free(struct snd_device *device)
1562 +{
1563 + struct snd_rad1 *chip = device->device_data;
1564 +
1565 + return snd_rad1_free(chip);
1566 +}
1567 +
1568 +static int
1569 +snd_rad1_create(struct snd_card *card, struct pci_dev *pci,
1570 + struct snd_rad1 **rchip)
1571 +{
1572 + int error = -ENODEV;
1573 + struct snd_rad1 *chip;
1574 + static struct snd_device_ops ops = {
1575 + .dev_free = snd_rad1_dev_free,
1576 + };
1577 +
1578 + *rchip = NULL;
1579 +
1580 + if (unlikely(pci_enable_device(pci)))
1581 + goto out;
1582 +
1583 + if (unlikely(pci_request_regions(pci, "rad1")))
1584 + goto out_disable_dev;
1585 +
1586 + pci_write_config_byte(pci, PCI_LATENCY_TIMER, 64);
1587 + pci_set_master(pci);
1588 +
1589 + chip = kzalloc(sizeof(struct snd_rad1), GFP_KERNEL);
1590 + if (unlikely(!chip)) {
1591 + error = -ENOMEM;
1592 + goto out_rel_region;
1593 + }
1594 +
1595 + timer_setup(&chip->timer, snd_rad1_poll_timer, 0);
1596 +
1597 + chip->card = card;
1598 + chip->pci = pci;
1599 +
1600 + spin_lock_init(&chip->lock);
1601 +
1602 + chip->mmio_phys = pci_resource_start(pci, 0);
1603 + chip->mmio = ioremap_nocache(chip->mmio_phys,
1604 + pci_resource_len(pci, 0));
1605 +
1606 + snd_rad1_hw_init(chip);
1607 +
1608 + if (snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops))
1609 + goto out_rad1_free;
1610 +
1611 + snd_card_set_dev(card, &pci->dev);
1612 + *rchip = chip;
1613 +
1614 + return 0;
1615 +
1616 +out_rad1_free:
1617 + snd_rad1_free(chip);
1618 +out_rel_region:
1619 + pci_release_regions(pci);
1620 +out_disable_dev:
1621 + pci_disable_device(pci);
1622 +out:
1623 + return error;
1624 +}
1625 +
1626 +static struct pci_device_id
1627 +snd_rad1_ids[] = {
1628 + { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_RAD1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
1629 + { 0, },
1630 +};
1631 +
1632 +static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
1633 +static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
1634 +static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
1635 +static int ndev;
1636 +
1637 +static int
1638 +snd_rad1_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1639 +{
1640 + struct snd_card *card;
1641 + struct snd_rad1 *chip;
1642 + int err;
1643 +
1644 + if (unlikely(ndev >= SNDRV_CARDS))
1645 + return -ENODEV;
1646 +
1647 + if (unlikely(!enable[ndev])) {
1648 + ndev++;
1649 + return -ENOENT;
1650 + }
1651 +
1652 + err = snd_card_new(&pci->dev, index[ndev], id[ndev], THIS_MODULE, 0, &card);
1653 + if (unlikely(err < 0))
1654 + return err;
1655 +
1656 + err = snd_rad1_create(card, pci, &chip);
1657 + if (unlikely(err < 0)) {
1658 + snd_card_free(card);
1659 + return err;
1660 + }
1661 +
1662 + strlcpy(card->driver, "RAD1", sizeof(card->driver));
1663 + strlcpy(card->shortname, "RADAudio", sizeof(card->shortname));
1664 + snprintf(card->longname, sizeof(card->longname),
1665 + "SGI RAD Audio at 0x%lx", chip->mmio_phys);
1666 +
1667 + /* create pipes */
1668 + snd_rad1_new_dac(chip, 0);
1669 + snd_rad1_new_adc(chip, 1);
1670 + snd_rad1_new_aestx(chip, 2);
1671 + snd_rad1_new_aesrx(chip, 3);
1672 + snd_rad1_add_controls(chip);
1673 +
1674 + err = snd_card_register(card);
1675 + if (unlikely(err < 0)) {
1676 + snd_card_free(card);
1677 + return err;
1678 + }
1679 +
1680 + pci_set_drvdata(pci, card);
1681 + ndev++;
1682 +
1683 + return 0;
1684 +}
1685 +
1686 +static void
1687 +snd_rad1_remove(struct pci_dev *pci)
1688 +{
1689 + snd_card_free(pci_get_drvdata(pci));
1690 + pci_set_drvdata(pci, NULL);
1691 +}
1692 +
1693 +MODULE_DEVICE_TABLE(pci, snd_rad1_ids);
1694 +
1695 +static struct pci_driver
1696 +rad1_driver = {
1697 + .name = "rad1",
1698 + .id_table = snd_rad1_ids,
1699 + .probe = snd_rad1_probe,
1700 + .remove = snd_rad1_remove,
1701 +};
1702 +
1703 +static int __init
1704 +alsa_card_rad1_init(void)
1705 +{
1706 + return pci_register_driver(&rad1_driver);
1707 +}
1708 +
1709 +static void __exit
1710 +alsa_card_rad1_exit(void)
1711 +{
1712 + pci_unregister_driver(&rad1_driver);
1713 +}
1714 +
1715 +MODULE_AUTHOR("Stanislaw Skowronek <skylark@unaligned.org>");
1716 +MODULE_AUTHOR("René Rebe <rene@exactcode.de");
1717 +MODULE_DESCRIPTION("SGI Octane (IP30) RAD1 ALSA driver");
1718 +MODULE_LICENSE("GPL");
1719 +MODULE_VERSION("0.42.3");
1720 +
1721 +module_init(alsa_card_rad1_init)
1722 +module_exit(alsa_card_rad1_exit)