| blob | b3492845be48f0a326cc4e0c22d512d0e3a024bd |
1 # --- T2-COPYRIGHT-NOTE-BEGIN ---
2 # T2 SDE: package/*/strace/riscv32.patch
3 # Copyright (C) 2021 - 2022 The T2 SDE Project
4 #
5 # This Copyright note is generated by scripts/Create-CopyPatch,
6 # more information can be found in the files COPYING and README.
7 #
8 # This patch file is dual-licensed. It is available under the license the
9 # patched project is licensed under, as long as it is an OpenSource license
10 # as defined at http://www.opensource.org/ (e.g. BSD, X11) or under the terms
11 # of the GNU General Public License version 2 as used by the T2 SDE.
12 # --- T2-COPYRIGHT-NOTE-END ---
14 Signed-off-by: Alistair Francis <alistair.francis at wdc.com>
15 ---
16 Makefile.am | 20 ++++++++--------
17 configure.ac | 6 ++++-
18 dist/INSTALL | 2 +-
19 src/linux/{riscv64 => riscv}/arch_defs_.h | 16 +++++++++++++
20 src/linux/{riscv64 => riscv}/arch_regs.c | 0
21 src/linux/riscv/asm_stat.h | 26 +++++++++++++++++++++
22 src/linux/{riscv64 => riscv}/get_error.c | 0
23 src/linux/{riscv64 => riscv}/get_scno.c | 0
24 src/linux/{riscv64 => riscv}/get_syscall_args.c | 0
25 src/linux/{riscv64 => riscv}/ioctls_arch0.h | 0
26 src/linux/riscv/ioctls_inc0.h | 7 ++++++
27 src/linux/{riscv64 => riscv}/raw_syscall.h | 0
28 src/linux/{riscv64 => riscv}/set_error.c | 0
29 src/linux/{riscv64 => riscv}/set_scno.c | 0
30 src/linux/{riscv64 => riscv}/syscallent.h | 8 ++++++-
31 src/linux/riscv64/ioctls_inc0.h | 1 -
32 src/riscv.c | 4 ++--
33 17 files changed, 74 insertions(+), 16 deletions(-)
34 create mode 100644 src/linux/riscv/arch_defs_.h
35 rename src/linux/{riscv64 => src/riscv}/arch_regs.c (100%)
36 create mode 100644 src/linux/riscv/asm_stat.h
37 rename src/linux/{riscv64 => src/riscv}/get_error.c (100%)
38 rename src/linux/{riscv64 => src/riscv}/get_scno.c (100%)
39 rename src/linux/{riscv64 => src/riscv}/get_syscall_args.c (100%)
40 rename src/linux/{riscv64 => src/riscv}/ioctls_arch0.h (100%)
41 create mode 100644 src/linux/riscv/ioctls_inc0.h
42 rename src/linux/{riscv64 => src/riscv}/raw_syscall.h (100%)
43 rename src/linux/{riscv64 => src/riscv}/set_error.c (100%)
44 rename src/linux/{riscv64 => src/riscv}/set_scno.c (100%)
45 rename src/linux/{riscv64 => src/riscv}/syscallent.h (64%)
46 delete mode 100644 src/linux/riscv64/ioctls_inc0.h
48 diff --git a/Makefile.am b/Makefile.am
49 index 9c62218f..4955654b 100644
50 --- a/src/Makefile.am
51 +++ b/src/Makefile.am
52 @@ -802,19 +802,19 @@ extrA_DIST =
53 linux/powerpc64le/set_scno.c \
54 linux/powerpc64le/syscallent.h \
55 linux/powerpc64le/userent.h \
56 - linux/riscv64/arch_defs_.h \
57 - linux/riscv64/arch_prstatus_regset.c \
58 - linux/riscv64/arch_prstatus_regset.h \
59 - linux/riscv64/arch_regs.c \
60 - linux/riscv64/get_error.c \
61 - linux/riscv64/get_scno.c \
62 - linux/riscv64/get_syscall_args.c \
63 - linux/riscv64/ioctls_arch0.h \
64 - linux/riscv64/ioctls_inc0.h \
65 - linux/riscv64/raw_syscall.h \
66 - linux/riscv64/set_error.c \
67 - linux/riscv64/set_scno.c \
68 - linux/riscv64/syscallent.h \
69 + linux/riscv/arch_defs_.h \
70 + linux/riscv/arch_prstatus_regset.c \
71 + linux/riscv/arch_prstatus_regset.h \
72 + linux/riscv/arch_regs.c \
73 + linux/riscv/get_error.c \
74 + linux/riscv/get_scno.c \
75 + linux/riscv/get_syscall_args.c \
76 + linux/riscv/ioctls_arch0.h \
77 + linux/riscv/ioctls_inc0.h \
78 + linux/riscv/raw_syscall.h \
79 + linux/riscv/set_error.c \
80 + linux/riscv/set_scno.c \
81 + linux/riscv/syscallent.h \
82 linux/s390/arch_defs_.h \
83 linux/s390/arch_prstatus_regset.c \
84 linux/s390/arch_prstatus_regset.h \
85 diff --git a/configure.ac b/configure.ac
86 index dd4f13f4..4a53681c 100644
87 --- a/configure.ac
88 +++ b/configure.ac
89 @@ -157,9 +157,12 @@
90 esac
91 fi
92 ;;
93 +riscv32*)
94 + arch=riscv
95 + AC_DEFINE([RISCV32], 1, [Define for the RISC-V 32-bit architecture])
96 + ;;
97 riscv64*)
98 - arch=riscv64
99 - karch=riscv
100 + arch=riscv
101 AC_DEFINE([RISCV64], 1, [Define for the RISC-V 64-bit architecture])
102 ;;
103 s390)
104 diff --git a/dist/INSTALL b/dist/INSTALL
105 index 0d22512b..19e059cf 100644
106 --- a/INSTALL
107 +++ b/INSTALL
108 @@ -63,7 +63,7 @@ Taking the aforementioned into account, there are the following requirements:
110 - gawk (at least version 3)
111 - Ability to compile for m32 personality (on architectures where it is supported)
112 - - On x86_64, x32, powerpc64, sparc64, riscv64, tile64: gcc -m32
113 + - On x86_64, x32, powerpc64, sparc64, riscv32, riscv64, tile64: gcc -m32
114 - s390x: gcc -m31
115 - AArch64: a separate compiler for armv7 EABI
116 - See information about configuration in "1.3.2. AArch64: AArch32 support"
117 diff --git a/src/linux/riscv64/arch_defs_.h b/src/linux/riscv/arch_defs_.h
118 similarity index 20%
119 rename from src/linux/riscv64/arch_defs_.h
120 rename to src/linux/riscv/arch_defs_.h
121 index 0d22512b..19e059cf 100644
122 --- a/src/linux/riscv64/arch_defs_.h
123 +++ b/src/linux/riscv/arch_defs_.h
124 @@ -1 +1,8 @@
125 -#define PERSONALITY0_AUDIT_ARCH { AUDIT_ARCH_RISCV64, 0 }
126 +#if defined(RISCV32)
127 +# define ARCH_TIMESIZE 64
128 +# define HAVE_ARCH_TIME32_SYSCALLS 0
129 +# define HAVE_ARCH_OLD_TIME64_SYSCALLS 0
130 +# define PERSONALITY0_AUDIT_ARCH { AUDIT_ARCH_RISCV32, 0 }
131 +#else
132 +# define PERSONALITY0_AUDIT_ARCH { AUDIT_ARCH_RISCV64, 0 }
133 +#endif
134 diff --git a/src/linux/riscv64/arch_regs.c b/src/linux/riscv/arch_regs.c
135 similarity index 100%
136 rename from src/linux/riscv64/arch_regs.c
137 rename to src/linux/riscv/arch_regs.c
138 diff --git a/src/linux/riscv/asm_stat.h b/src/linux/riscv/asm_stat.h
139 new file mode 100644
140 index 00000000..73341454
141 --- /dev/null
142 +++ b/src/linux/riscv/asm_stat.h
143 @@ -0,0 +1,26 @@
144 +/*
145 + * Copyright (c) 2020 The strace developers.
146 + * All rights reserved.
147 + *
148 + * SPDX-License-Identifier: LGPL-2.1-or-later
149 + */
150 +
151 +#ifndef STRACE_RISCV_ASM_STAT_H
152 +# define STRACE_RISCV_ASM_STAT_H
153 +
154 +# include "linux/generic/asm_stat.h"
155 +
156 +# if defined(RISCV32)
157 +# undef dev_t
158 +# undef ino_t
159 +# undef off64_t
160 +# undef off_t
161 +# undef time_t
162 +
163 +# define dev_t __kernel_loff_t
164 +# define ino_t __kernel_loff_t
165 +# define off64_t __kernel_off64_t
166 +# define off_t __kernel_off64_t
167 +# define time_t __kernel_time64_t
168 +# endif /* defined(RISCV32) */
169 +#endif /* !STRACE_RISCV_ASM_STAT_H */
170 diff --git a/src/linux/riscv64/arch_prstatus_regset.h b/src/linux/riscv/arch_prstatus_regset.h
171 similarity index 100%
172 rename from src/linux/riscv64/arch_prstatus_regset.h
173 rename to src/linux/riscv/arch_prstatus_regset.h
174 diff --git a/src/linux/riscv64/arch_prstatus_regset.c b/src/linux/riscv/arch_prstatus_regset.c
175 similarity index 100%
176 rename from src/linux/riscv64/arch_prstatus_regset.c
177 rename to src/linux/riscv/arch_prstatus_regset.c
178 diff --git a/src/linux/riscv64/get_error.c b/src/linux/riscv/get_error.c
179 similarity index 100%
180 rename from src/linux/riscv64/get_error.c
181 rename to src/linux/riscv/get_error.c
182 diff --git a/src/linux/riscv64/get_scno.c b/src/linux/riscv/get_scno.c
183 similarity index 100%
184 rename from src/linux/riscv64/get_scno.c
185 rename to src/linux/riscv/get_scno.c
186 diff --git a/src/linux/riscv64/get_syscall_args.c b/src/linux/riscv/get_syscall_args.c
187 similarity index 100%
188 rename from src/linux/riscv64/get_syscall_args.c
189 rename to src/linux/riscv/get_syscall_args.c
190 diff --git a/src/linux/riscv64/ioctls_arch0.h b/src/linux/riscv/ioctls_arch0.h
191 similarity index 100%
192 rename from src/linux/riscv64/ioctls_arch0.h
193 rename to src/linux/riscv/ioctls_arch0.h
194 diff --git a/src/linux/riscv/ioctls_inc0.h b/src/linux/riscv/ioctls_inc0.h
195 new file mode 100644
196 index 00000000..cc39332f
197 --- /dev/null
198 +++ b/src/linux/riscv/ioctls_inc0.h
199 @@ -0,0 +1,7 @@
200 +#if defined(RISCV64)
201 +# include "../64/ioctls_inc.h"
202 +#elif defined(RISCV32)
203 +# include "../32/ioctls_inc.h"
204 +#else
205 +# error "Unsupported RISC-V xlen"
206 +#endif
207 diff --git a/src/linux/riscv64/raw_syscall.h b/src/linux/riscv/raw_syscall.h
208 similarity index 100%
209 rename from src/linux/riscv64/raw_syscall.h
210 rename to src/linux/riscv/raw_syscall.h
211 diff --git a/src/linux/riscv64/set_error.c b/src/linux/riscv/set_error.c
212 similarity index 100%
213 rename from src/linux/riscv64/set_error.c
214 rename to src/linux/riscv/set_error.c
215 diff --git a/src/linux/riscv64/set_scno.c b/src/linux/riscv/set_scno.c
216 similarity index 100%
217 rename from src/linux/riscv64/set_scno.c
218 rename to src/linux/riscv/set_scno.c
219 diff --git a/src/linux/riscv64/syscallent.h b/src/linux/riscv/syscallent.h
220 similarity index 64%
221 rename from src/linux/riscv64/syscallent.h
222 rename to src/linux/riscv/syscallent.h
223 index 60c6ce58..c8fb3b8f 100644
224 --- a/src/linux/riscv64/syscallent.h
225 +++ b/src/linux/riscv/syscallent.h
226 @@ -5,7 +5,13 @@
227 * SPDX-License-Identifier: LGPL-2.1-or-later
228 */
230 -#include "../64/syscallent.h"
231 +#if defined(RISCV64)
232 +# include "../64/syscallent.h"
233 +#elif defined(RISCV32)
234 +# include "../32/syscallent.h"
235 +#else
236 +# error "Unsupported RISC-V xlen"
237 +#endif
239 /* #define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15) */
240 [259] = { 3, TM, SEN(riscv_flush_icache), "riscv_flush_icache" },
241 diff --git a/src/linux/riscv64/ioctls_inc0.h b/src/linux/riscv64/ioctls_inc0.h
242 deleted file mode 100644
243 index f9939faa..00000000
244 --- a/src/linux/riscv64/ioctls_inc0.h
245 +++ /dev/null
246 @@ -1 +0,0 @@
247 -#include "../64/ioctls_inc.h"
248 diff --git a/riscv.c b/riscv.c
249 index 825eb293..20094ba5 100644
250 --- a/src/riscv.c
251 +++ b/src/riscv.c
252 @@ -9,7 +9,7 @@
254 #include "defs.h"
256 -#ifdef RISCV64
257 +#if defined(RISCV64) || defined(RISCV32)
259 # include "xlat/riscv_flush_icache_flags.h"
261 @@ -30,4 +30,4 @@ SYS_FUNC(riscv_flush_icache)
262 return RVAL_DECODED;
263 }
265 -#endif /* RISCV64 */
266 +#endif /* defined(RISCV64) || defined(RISCV32) */
267 --
268 2.25.0
270 --- strace-5.10/src/config.h.in.vanilla 2021-02-13 16:11:28.950662094 +0100
271 +++ strace-5.10/src/config.h.in 2021-02-13 16:12:01.681663752 +0100
272 @@ -3776,6 +3779,9 @@
273 /* Define for the little endian PowerPC64 architecture. */
274 #undef POWERPC64LE
276 +/* Define for the RISC-V 32-bit architecture */
277 +#undef RISCV32
278 +
279 /* Define for the RISC-V 64-bit architecture */
280 #undef RISCV64