| blob | 9202a831048c436fd48df42f65c2d7967eed93b0 |
1 From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
2 From: Arjan van de Ven <arjan@linux.intel.com>
3 Date: Sat, 19 Mar 2016 21:32:19 -0400
4 Subject: [PATCH] intel_idle: tweak cpuidle cstates
6 Increase target_residency in cpuidle cstate
8 Tune intel_idle to be a bit less agressive;
9 Clear linux is cleaner in hygiene (wakupes) than the average linux,
10 so we can afford changing these in a way that increases
11 performance while keeping power efficiency
12 ---
13 drivers/idle/intel_idle.c | 44 +++++++++++++++++++--------------------
14 1 file changed, 22 insertions(+), 22 deletions(-)
16 diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
17 index 3a1617a3e5bf..4f0ac8a9c6ab 100644
18 --- a/drivers/idle/intel_idle.c
19 +++ b/drivers/idle/intel_idle.c
20 @@ -498,7 +498,7 @@ static struct cpuidle_state hsw_cstates[] __initdata = {
21 .desc = "MWAIT 0x01",
22 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
23 .exit_latency = 10,
24 - .target_residency = 20,
25 + .target_residency = 120,
26 .enter = &intel_idle,
27 .enter_s2idle = intel_idle_s2idle, },
28 {
29 @@ -506,7 +506,7 @@ static struct cpuidle_state hsw_cstates[] __initdata = {
30 .desc = "MWAIT 0x10",
31 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
32 .exit_latency = 33,
33 - .target_residency = 100,
34 + .target_residency = 900,
35 .enter = &intel_idle,
36 .enter_s2idle = intel_idle_s2idle, },
37 {
38 @@ -514,7 +514,7 @@ static struct cpuidle_state hsw_cstates[] __initdata = {
39 .desc = "MWAIT 0x20",
40 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
41 .exit_latency = 133,
42 - .target_residency = 400,
43 + .target_residency = 1000,
44 .enter = &intel_idle,
45 .enter_s2idle = intel_idle_s2idle, },
46 {
47 @@ -522,7 +522,7 @@ static struct cpuidle_state hsw_cstates[] __initdata = {
48 .desc = "MWAIT 0x32",
49 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
50 .exit_latency = 166,
51 - .target_residency = 500,
52 + .target_residency = 1500,
53 .enter = &intel_idle,
54 .enter_s2idle = intel_idle_s2idle, },
55 {
56 @@ -530,7 +530,7 @@ static struct cpuidle_state hsw_cstates[] __initdata = {
57 .desc = "MWAIT 0x40",
58 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
59 .exit_latency = 300,
60 - .target_residency = 900,
61 + .target_residency = 2000,
62 .enter = &intel_idle,
63 .enter_s2idle = intel_idle_s2idle, },
64 {
65 @@ -538,7 +538,7 @@ static struct cpuidle_state hsw_cstates[] __initdata = {
66 .desc = "MWAIT 0x50",
67 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
68 .exit_latency = 600,
69 - .target_residency = 1800,
70 + .target_residency = 5000,
71 .enter = &intel_idle,
72 .enter_s2idle = intel_idle_s2idle, },
73 {
74 @@ -546,7 +546,7 @@ static struct cpuidle_state hsw_cstates[] __initdata = {
75 .desc = "MWAIT 0x60",
76 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
77 .exit_latency = 2600,
78 - .target_residency = 7700,
79 + .target_residency = 9000,
80 .enter = &intel_idle,
81 .enter_s2idle = intel_idle_s2idle, },
82 {
83 @@ -566,7 +566,7 @@ static struct cpuidle_state bdw_cstates[] __initdata = {
84 .desc = "MWAIT 0x01",
85 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
86 .exit_latency = 10,
87 - .target_residency = 20,
88 + .target_residency = 120,
89 .enter = &intel_idle,
90 .enter_s2idle = intel_idle_s2idle, },
91 {
92 @@ -574,7 +574,7 @@ static struct cpuidle_state bdw_cstates[] __initdata = {
93 .desc = "MWAIT 0x10",
94 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
95 .exit_latency = 40,
96 - .target_residency = 100,
97 + .target_residency = 1000,
98 .enter = &intel_idle,
99 .enter_s2idle = intel_idle_s2idle, },
100 {
101 @@ -582,7 +582,7 @@ static struct cpuidle_state bdw_cstates[] __initdata = {
102 .desc = "MWAIT 0x20",
103 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
104 .exit_latency = 133,
105 - .target_residency = 400,
106 + .target_residency = 1000,
107 .enter = &intel_idle,
108 .enter_s2idle = intel_idle_s2idle, },
109 {
110 @@ -590,7 +590,7 @@ static struct cpuidle_state bdw_cstates[] __initdata = {
111 .desc = "MWAIT 0x32",
112 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
113 .exit_latency = 166,
114 - .target_residency = 500,
115 + .target_residency = 2000,
116 .enter = &intel_idle,
117 .enter_s2idle = intel_idle_s2idle, },
118 {
119 @@ -598,7 +598,7 @@ static struct cpuidle_state bdw_cstates[] __initdata = {
120 .desc = "MWAIT 0x40",
121 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
122 .exit_latency = 300,
123 - .target_residency = 900,
124 + .target_residency = 4000,
125 .enter = &intel_idle,
126 .enter_s2idle = intel_idle_s2idle, },
127 {
128 @@ -606,7 +606,7 @@ static struct cpuidle_state bdw_cstates[] __initdata = {
129 .desc = "MWAIT 0x50",
130 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
131 .exit_latency = 600,
132 - .target_residency = 1800,
133 + .target_residency = 7000,
134 .enter = &intel_idle,
135 .enter_s2idle = intel_idle_s2idle, },
136 {
137 @@ -614,7 +614,7 @@ static struct cpuidle_state bdw_cstates[] __initdata = {
138 .desc = "MWAIT 0x60",
139 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
140 .exit_latency = 2600,
141 - .target_residency = 7700,
142 + .target_residency = 9000,
143 .enter = &intel_idle,
144 .enter_s2idle = intel_idle_s2idle, },
145 {
146 @@ -635,7 +635,7 @@ static struct cpuidle_state skl_cstates[] __initdata = {
147 .desc = "MWAIT 0x01",
148 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
149 .exit_latency = 10,
150 - .target_residency = 20,
151 + .target_residency = 120,
152 .enter = &intel_idle,
153 .enter_s2idle = intel_idle_s2idle, },
154 {
155 @@ -643,7 +643,7 @@ static struct cpuidle_state skl_cstates[] __initdata = {
156 .desc = "MWAIT 0x10",
157 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
158 .exit_latency = 70,
159 - .target_residency = 100,
160 + .target_residency = 1000,
161 .enter = &intel_idle,
162 .enter_s2idle = intel_idle_s2idle, },
163 {
164 @@ -651,7 +651,7 @@ static struct cpuidle_state skl_cstates[] __initdata = {
165 .desc = "MWAIT 0x20",
166 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
167 .exit_latency = 85,
168 - .target_residency = 200,
169 + .target_residency = 600,
170 .enter = &intel_idle,
171 .enter_s2idle = intel_idle_s2idle, },
172 {
173 @@ -659,7 +659,7 @@ static struct cpuidle_state skl_cstates[] __initdata = {
174 .desc = "MWAIT 0x33",
175 .flags = MWAIT2flg(0x33) | CPUIDLE_FLAG_TLB_FLUSHED,
176 .exit_latency = 124,
177 - .target_residency = 800,
178 + .target_residency = 3000,
179 .enter = &intel_idle,
180 .enter_s2idle = intel_idle_s2idle, },
181 {
182 @@ -667,7 +667,7 @@ static struct cpuidle_state skl_cstates[] __initdata = {
183 .desc = "MWAIT 0x40",
184 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
185 .exit_latency = 200,
186 - .target_residency = 800,
187 + .target_residency = 3200,
188 .enter = &intel_idle,
189 .enter_s2idle = intel_idle_s2idle, },
190 {
191 @@ -675,7 +675,7 @@ static struct cpuidle_state skl_cstates[] __initdata = {
192 .desc = "MWAIT 0x50",
193 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
194 .exit_latency = 480,
195 - .target_residency = 5000,
196 + .target_residency = 9000,
197 .enter = &intel_idle,
198 .enter_s2idle = intel_idle_s2idle, },
199 {
200 @@ -683,7 +683,7 @@ static struct cpuidle_state skl_cstates[] __initdata = {
201 .desc = "MWAIT 0x60",
202 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
203 .exit_latency = 890,
204 - .target_residency = 5000,
205 + .target_residency = 9000,
206 .enter = &intel_idle,
207 .enter_s2idle = intel_idle_s2idle, },
208 {
209 @@ -704,7 +704,7 @@ static struct cpuidle_state skx_cstates[] __initdata = {
210 .desc = "MWAIT 0x01",
211 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
212 .exit_latency = 10,
213 - .target_residency = 20,
214 + .target_residency = 300,
215 .enter = &intel_idle,
216 .enter_s2idle = intel_idle_s2idle, },
217 {
218 --
219 https://clearlinux.org