package/contrib/stressapptest/hotfix-i686.patch

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   2 # T2 SDE: package/*/stressapptest/hotfix-i686.patch
   3 # Copyright (C) 2024 The T2 SDE Project
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   9 # patched project is licensed under, as long as it is an OpenSource license
  10 # as defined at http://www.opensource.org/ (e.g. BSD, X11) or under the terms
  11 # of the GNU General Public License version 2 as used by the T2 SDE.
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  13
  14 include/emmintrin.h:1526:1: error: inlining failed in call to 'always_inline' '_mm_clflush(void const*)': target specific option mismatch
  15  1526 | _mm_clflush (void const *__A)
  16
  17 --- stressapptest-1.0.11/src/os.h.vanilla       2024-02-09 16:49:02.605879492 +0100
  18 +++ stressapptest-1.0.11/src/os.h       2024-02-09 16:55:04.521908407 +0100
  19 @@ -150,7 +150,7 @@
  20    inline static void FastFlush(void *vaddr) {
  21  #ifdef STRESSAPPTEST_CPU_PPC
  22      asm volatile("dcbf 0,%0; sync" : : "r" (vaddr));
  23 -#elif defined(STRESSAPPTEST_CPU_X86_64) || defined(STRESSAPPTEST_CPU_I686)
  24 +#elif defined(STRESSAPPTEST_CPU_X86_64) || (defined(STRESSAPPTEST_CPU_I686) && defined(__SSE2__))
  25      // Put mfence before and after clflush to make sure:
  26      // 1. The write before the clflush is committed to memory bus;
  27      // 2. The read after the clflush is hitting the memory bus.
  28 @@ -192,7 +192,7 @@
  29        asm volatile("dcbf 0,%0" : : "r" (*vaddrs++));
  30      }
  31      asm volatile("sync");
  32 -#elif defined(STRESSAPPTEST_CPU_X86_64) || defined(STRESSAPPTEST_CPU_I686)
  33 +#elif defined(STRESSAPPTEST_CPU_X86_64) || (defined(STRESSAPPTEST_CPU_I686) && defined(__SSE2__))
  34      // Put mfence before and after clflush to make sure:
  35      // 1. The write before the clflush is committed to memory bus;
  36      // 2. The read after the clflush is hitting the memory bus.
  37 @@ -226,7 +226,7 @@
  38    inline static void FastFlushHint(void *vaddr) {
  39  #ifdef STRESSAPPTEST_CPU_PPC
  40      asm volatile("dcbf 0,%0" : : "r" (vaddr));
  41 -#elif defined(STRESSAPPTEST_CPU_X86_64) || defined(STRESSAPPTEST_CPU_I686)
  42 +#elif defined(STRESSAPPTEST_CPU_X86_64) || (defined(STRESSAPPTEST_CPU_I686) && defined(__SSE2__))
  43      // From Intel manual:
  44      // CLFLUSH is only ordered by the MFENCE instruction. It is not guaranteed
  45      // to be ordered by any other fencing, serializing or other CLFLUSH
  46 @@ -248,7 +248,7 @@
  47    inline static void FastFlushSync() {
  48  #ifdef STRESSAPPTEST_CPU_PPC
  49      asm volatile("sync");
  50 -#elif defined(STRESSAPPTEST_CPU_X86_64) || defined(STRESSAPPTEST_CPU_I686)
  51 +#elif defined(STRESSAPPTEST_CPU_X86_64) || (defined(STRESSAPPTEST_CPU_I686) && defined(__SSE2__))
  52      // Put mfence before and after clflush to make sure:
  53      // 1. The write before the clflush is committed to memory bus;
  54      // 2. The read after the clflush is hitting the memory bus.