package/develop/vhd2vl/vhd2vl.desc

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   3 [COPY] Copyright (C) 2018 - 2024 The T2 SDE Project
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   6 [COPY] more information can be found in the files COPYING and README.
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   8 [COPY] This program is free software; you can redistribute it and/or modify
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  11
  12 [I] Translate synthesizable VHDL into Verilog
  13
  14 [T] Vhd2vl is designed to translate synthesizable VHDL into Verilog 1995 or 2001.
  15
  16 [U] https://github.com/ldoolitt/vhd2vl
  17
  18 [A] Vincenzo Liguori - Ocean Logic Pty Ltd
  19 [M] Rene Rebe <rene@t2-project.org>
  20
  21 [C] extra/development
  22 [F] CROSS
  23
  24 [L] GPL
  25 [S] Stable
  26 [V] bbe3198
  27 [P] X -----5---9 126.800
  28
  29 [O] var_append makeopt ' ' '-C src'
  30 [O] makeinstopt=
  31 [O] hook_add postmake 5 "install src/vhd2vl $root$bindir/"
  32
  33 [D] b8e1aad0a2ea5ddae726ef4750e494183c70a4946ec22d892edca59e vhd2vl-bbe3198.tar.zst git+https://github.com/ldoolitt/vhd2vl bbe3198