platform/win32/win32cpuid.cpp

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  39
  40
  41 #include <windows.h>
  42 #include <winbase.h>
  43
  44 // disable warnings about "Inline asm assigning to FS:0 handler not registered as safe handler"
  45 #pragma warning(disable:4733)
  46
  47 // Code from Intel that crashes a Cyrix CPU
  48 #define CPUID   _asm _emit 0x0F _asm _emit 0xA2
  49
  50 #define CPUID_SSE2_FLAG 0x04000000 //; Is IA SSE2 bit (Bit 26 of EDX) in feature flags set
  51 static BOOL gP4OsSupport = FALSE;
  52
  53 #ifndef _WIN64
  54 EXCEPTION_DISPOSITION __cdecl MyExceptionHandlerSSE2(struct _EXCEPTION_RECORD * /*ExceptionRecord*/,
  55                                                  void * /*EstablisherFrame*/,
  56                                                  struct _CONTEXT *ContextRecord,
  57                                                  void * /*DispatcherContext*/)
  58 {
  59     // Turn off the P4 OS support flag.
  60     gP4OsSupport = FALSE;
  61
  62     // The offending P4 instruction is 3 bytes long.  Skip it and continue.
  63     ContextRecord->Eip += 3;
  64     return ExceptionContinueExecution;
  65 }
  66 #endif
  67
  68 bool P4Available()
  69 {
  70 #ifdef _M_AMD64
  71     // we support all this stuff
  72     return true;
  73 #else
  74     long featureFlags = 0;
  75     //arun
  76     BOOL procType = 0;
  77
  78 // disable warnings about unreferenced _asm labels.
  79 #pragma warning(disable:4102)
  80
  81     _asm {
  82         push ecx
  83         push ebx
  84
  85 ;       i386 CPU check
  86 ;       The AC bit, bit #18, is a new bit introduced in the EFLAGS
  87 ;       register on the i486 DX CPU to generate alignment faults.
  88 ;       This bit can not be set on the i386 CPU.
  89 ;
  90 check_Intel386:
  91         pushfd
  92         pop             eax                     ; get original EFLAGS
  93         mov             ecx,eax                 ; save original EFLAGS
  94         xor             eax,40000h              ; flip AC bit in EFLAGS
  95         push    eax                     ; save for EFLAGS
  96         popfd                                   ; copy to EFLAGS
  97         pushfd                                  ; push EFLAGS
  98         pop             eax                     ; get new EFLAGS value
  99         xor             eax,ecx                 ; can't toggle AC bit, CPU=Intel386
 100         je              end_get_cpuid   ; CPU is i386,
 101
 102 ;       i486 DX CPU / i487 SX MCP and i486 SX CPU checking
 103 ;
 104 ;       Checking for ability to set/clear ID flag (Bit 21) in EFLAGS
 105 ;       which indicates the presence of a processor
 106 ;       with the ability to use the CPUID instruction.
 107 ;
 108 check_Intel486:
 109         pushfd                                  ; push original EFLAGS
 110         pop             eax                     ; get original EFLAGS in eax
 111         mov             ecx,eax                 ; save original EFLAGS in ecx
 112         xor             eax,200000h             ; flip ID bit in EFLAGS
 113         push    eax                     ; save for EFLAGS
 114         popfd                                   ; copy to EFLAGS
 115         pushfd                                  ; push EFLAGS
 116         pop             eax                     ; get new EFLAGS value
 117         xor     eax, ecx
 118         je              end_get_cpuid   ; CPU=486 without CPUID instruction functionality
 119
 120 ;       Execute CPUID instruction to determine vendor, family,
 121 ;       model and stepping.  The use of the CPUID instruction used
 122 ;       in this program can be used for B0 and later steppings
 123 ;       of the P5 processor.
 124
 125 cpuid_data:
 126         // At this point we know we can do our CPUID instruction
 127         // We need some special code here to handle Cyrix buggy processors
 128
 129         // Get our Vendors name out first
 130         mov         eax, 0
 131         CPUID
 132         //arun
 133         cmp ebx, 0x47656e75
 134         jz cyrix_version
 135         cmp edx, 0x696e6549
 136         jz cyrix_version
 137         cmp ecx, 0x6e74656c
 138         jz cyrix_version
 139         mov procType, 1
 140         jmp non_cyrix_version
 141
 142 cyrix_version:
 143         // EAX returns the highest value we can use as input into the
 144         // CPUID instruction.  If for some reason it returns 0, assume
 145         // no MMX support.  (Since we need to input 1 to query MMX)
 146         cmp eax, 0
 147         jz end_get_cpuid
 148
 149         cmp ebx, 0x69727943 // This is "iryC", "Cyri" in memory
 150         jne non_cyrix_version
 151
 152         // EAX now contains the stepping, model and family information
 153         and eax, 0x0FF0 // isolate model and family info
 154         cmp eax, 0x0520 // We're a 6x86, so there's no MMX
 155         je end_get_cpuid
 156
 157 non_cyrix_version:
 158         // Non Cyrix version
 159         mov         eax, 1 // Our input flag for our CPUID instruction
 160         CPUID
 161         mov featureFlags, edx ; save feature flags
 162
 163 end_get_cpuid:
 164         pop ecx
 165         pop ebx
 166     }
 167
 168     BOOL bOsSupport = FALSE;
 169     BOOL bHwSupport = (featureFlags & CPUID_SSE2_FLAG);
 170
 171     if(bHwSupport) {
 172         // Execute a KNI instruction and use Structured Exception Handling
 173         // to catch the exception if the OS does not support KNI.
 174
 175         DWORD handler = (DWORD)MyExceptionHandlerSSE2;
 176
 177         gP4OsSupport = TRUE;
 178
 179         __asm { // Build EXCEPTION_REGISTRATION record:
 180             push handler    // Address of handler function
 181             push FS:[0]     // Address of previous handler
 182             mov FS:[0],ESP  // Install new EXECEPTION_REGISTRATION
 183         }
 184
 185         // If so, test a KNI instruction and make sure you don't get
 186         // an exception (this tests OS support)
 187         __asm{
 188             pushad;
 189             //orpd xmm1,xmm1;   //Below are the op codes for this instruction
 190                                 //emits will compile w/ MSVC 5.0 compiler
 191                                 //You can comment these out and uncomment the
 192                                 //orpd when using the Intel Compiler
 193             __emit 0x66
 194             __emit 0x0f
 195             __emit 0x56
 196             __emit 0xc9
 197             popad;
 198         }
 199
 200         __asm {                 // Remove our EXECEPTION_REGISTRATION record
 201             mov eax,[ESP]       // Get pointer to previous record
 202             mov FS:[0], EAX     // Install previous record
 203             add esp, 8          // Clean our EXECEPTION_REGISTRATION off stack
 204         }
 205
 206         bOsSupport = gP4OsSupport;
 207     }
 208
 209     return bHwSupport && bOsSupport && procType;
 210 #endif
 211 }
 212