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Fixed binary search: no more infinite loops when vendor is unknown.
[tangerine.git] / workbench / devs / networks / e1000 / e1000_82540.c
blob9d678df8c77df7441b16425a0e226e5803a933e6
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /* e1000_82540
30 * e1000_82545
31 * e1000_82546
32 * e1000_82545_rev_3
33 * e1000_82546_rev_3
34 */
35
36 #include "e1000_api.h"
37
38 static s32 e1000_init_phy_params_82540(struct e1000_hw *hw);
39 static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw);
40 static s32 e1000_init_mac_params_82540(struct e1000_hw *hw);
41 static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw);
42 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw);
43 static s32 e1000_init_hw_82540(struct e1000_hw *hw);
44 static s32 e1000_reset_hw_82540(struct e1000_hw *hw);
45 static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw);
46 static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw);
47 static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw);
48 static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw);
49 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw);
50
51 /**
52 * e1000_init_phy_params_82540 - Init PHY func ptrs.
53 * @hw: pointer to the HW structure
54 *
55 * This is a function pointer entry point called by the api module.
56 **/
57 static s32 e1000_init_phy_params_82540(struct e1000_hw *hw)
58 {
59 struct e1000_phy_info *phy = &hw->phy;
60 s32 ret_val = E1000_SUCCESS;
61
62 phy->addr = 1;
63 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
64 phy->reset_delay_us = 10000;
65 phy->type = e1000_phy_m88;
66
67 /* Function Pointers */
68 phy->ops.check_polarity = e1000_check_polarity_m88;
69 phy->ops.commit = e1000_phy_sw_reset_generic;
70 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
71 phy->ops.get_cable_length = e1000_get_cable_length_m88;
72 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
73 phy->ops.read_reg = e1000_read_phy_reg_m88;
74 phy->ops.reset = e1000_phy_hw_reset_generic;
75 phy->ops.write_reg = e1000_write_phy_reg_m88;
76 phy->ops.get_info = e1000_get_phy_info_m88;
77 phy->ops.power_up = e1000_power_up_phy_copper;
78 phy->ops.power_down = e1000_power_down_phy_copper_82540;
79
80 ret_val = e1000_get_phy_id(hw);
81 if (ret_val)
82 goto out;
83
84 /* Verify phy id */
85 switch (hw->mac.type) {
86 case e1000_82540:
87 case e1000_82545:
88 case e1000_82545_rev_3:
89 case e1000_82546:
90 case e1000_82546_rev_3:
91 if (phy->id == M88E1011_I_PHY_ID)
92 break;
93 /* Fall Through */
94 default:
95 ret_val = -E1000_ERR_PHY;
96 goto out;
97 break;
98 }
99
100 out:
101 return ret_val;
102 }
103
104 /**
105 * e1000_init_nvm_params_82540 - Init NVM func ptrs.
106 * @hw: pointer to the HW structure
107 *
108 * This is a function pointer entry point called by the api module.
109 **/
110 static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw)
111 {
112 struct e1000_nvm_info *nvm = &hw->nvm;
113 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
114
115 DEBUGFUNC("e1000_init_nvm_params_82540");
116
117 nvm->type = e1000_nvm_eeprom_microwire;
118 nvm->delay_usec = 50;
119 nvm->opcode_bits = 3;
120 switch (nvm->override) {
121 case e1000_nvm_override_microwire_large:
122 nvm->address_bits = 8;
123 nvm->word_size = 256;
124 break;
125 case e1000_nvm_override_microwire_small:
126 nvm->address_bits = 6;
127 nvm->word_size = 64;
128 break;
129 default:
130 nvm->address_bits = eecd & E1000_EECD_SIZE ? 8 : 6;
131 nvm->word_size = eecd & E1000_EECD_SIZE ? 256 : 64;
132 break;
133 }
134
135 /* Function Pointers */
136 nvm->ops.acquire = e1000_acquire_nvm_generic;
137 nvm->ops.read = e1000_read_nvm_microwire;
138 nvm->ops.release = e1000_release_nvm_generic;
139 nvm->ops.update = e1000_update_nvm_checksum_generic;
140 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
141 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
142 nvm->ops.write = e1000_write_nvm_microwire;
143
144 return E1000_SUCCESS;
145 }
146
147 /**
148 * e1000_init_mac_params_82540 - Init MAC func ptrs.
149 * @hw: pointer to the HW structure
150 *
151 * This is a function pointer entry point called by the api module.
152 **/
153 static s32 e1000_init_mac_params_82540(struct e1000_hw *hw)
154 {
155 struct e1000_mac_info *mac = &hw->mac;
156 s32 ret_val = E1000_SUCCESS;
157
158 DEBUGFUNC("e1000_init_mac_params_82540");
159
160 /* Set media type */
161 switch (hw->device_id) {
162 case E1000_DEV_ID_82545EM_FIBER:
163 case E1000_DEV_ID_82545GM_FIBER:
164 case E1000_DEV_ID_82546EB_FIBER:
165 case E1000_DEV_ID_82546GB_FIBER:
166 hw->phy.media_type = e1000_media_type_fiber;
167 break;
168 case E1000_DEV_ID_82545GM_SERDES:
169 case E1000_DEV_ID_82546GB_SERDES:
170 hw->phy.media_type = e1000_media_type_internal_serdes;
171 break;
172 default:
173 hw->phy.media_type = e1000_media_type_copper;
174 break;
175 }
176
177 /* Set mta register count */
178 mac->mta_reg_count = 128;
179 /* Set rar entry count */
180 mac->rar_entry_count = E1000_RAR_ENTRIES;
181
182 /* Function pointers */
183
184 /* bus type/speed/width */
185 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
186 /* reset */
187 mac->ops.reset_hw = e1000_reset_hw_82540;
188 /* hw initialization */
189 mac->ops.init_hw = e1000_init_hw_82540;
190 /* link setup */
191 mac->ops.setup_link = e1000_setup_link_generic;
192 /* physical interface setup */
193 mac->ops.setup_physical_interface =
194 (hw->phy.media_type == e1000_media_type_copper)
195 ? e1000_setup_copper_link_82540
196 : e1000_setup_fiber_serdes_link_82540;
197 /* check for link */
198 switch (hw->phy.media_type) {
199 case e1000_media_type_copper:
200 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
201 break;
202 case e1000_media_type_fiber:
203 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
204 break;
205 case e1000_media_type_internal_serdes:
206 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
207 break;
208 default:
209 ret_val = -E1000_ERR_CONFIG;
210 goto out;
211 break;
212 }
213 /* link info */
214 mac->ops.get_link_up_info =
215 (hw->phy.media_type == e1000_media_type_copper)
216 ? e1000_get_speed_and_duplex_copper_generic
217 : e1000_get_speed_and_duplex_fiber_serdes_generic;
218 /* multicast address update */
219 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
220 /* writing VFTA */
221 mac->ops.write_vfta = e1000_write_vfta_generic;
222 /* clearing VFTA */
223 mac->ops.clear_vfta = e1000_clear_vfta_generic;
224 /* setting MTA */
225 mac->ops.mta_set = e1000_mta_set_generic;
226 /* setup LED */
227 mac->ops.setup_led = e1000_setup_led_generic;
228 /* cleanup LED */
229 mac->ops.cleanup_led = e1000_cleanup_led_generic;
230 /* turn on/off LED */
231 mac->ops.led_on = e1000_led_on_generic;
232 mac->ops.led_off = e1000_led_off_generic;
233 /* clear hardware counters */
234 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82540;
235
236 out:
237 return ret_val;
238 }
239
240 /**
241 * e1000_init_function_pointers_82540 - Init func ptrs.
242 * @hw: pointer to the HW structure
243 *
244 * The only function explicitly called by the api module to initialize
245 * all function pointers and parameters.
246 **/
247 void e1000_init_function_pointers_82540(struct e1000_hw *hw)
248 {
249 DEBUGFUNC("e1000_init_function_pointers_82540");
250
251 hw->mac.ops.init_params = e1000_init_mac_params_82540;
252 hw->nvm.ops.init_params = e1000_init_nvm_params_82540;
253 hw->phy.ops.init_params = e1000_init_phy_params_82540;
254 }
255
256 /**
257 * e1000_reset_hw_82540 - Reset hardware
258 * @hw: pointer to the HW structure
259 *
260 * This resets the hardware into a known state. This is a
261 * function pointer entry point called by the api module.
262 **/
263 static s32 e1000_reset_hw_82540(struct e1000_hw *hw)
264 {
265 u32 ctrl, icr, manc;
266 s32 ret_val = E1000_SUCCESS;
267
268 DEBUGFUNC("e1000_reset_hw_82540");
269
270 DEBUGOUT("Masking off all interrupts\n");
271 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
272
273 E1000_WRITE_REG(hw, E1000_RCTL, 0);
274 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
275 E1000_WRITE_FLUSH(hw);
276
277 /*
278 * Delay to allow any outstanding PCI transactions to complete
279 * before resetting the device.
280 */
281 msec_delay(10);
282
283 ctrl = E1000_READ_REG(hw, E1000_CTRL);
284
285 DEBUGOUT("Issuing a global reset to 82540/82545/82546 MAC\n");
286 switch (hw->mac.type) {
287 case e1000_82545_rev_3:
288 case e1000_82546_rev_3:
289 E1000_WRITE_REG(hw, E1000_CTRL_DUP, ctrl | E1000_CTRL_RST);
290 break;
291 default:
292 /*
293 * These controllers can't ack the 64-bit write when
294 * issuing the reset, so we use IO-mapping as a
295 * workaround to issue the reset.
296 */
297 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
298 break;
299 }
300
301 /* Wait for EEPROM reload */
302 msec_delay(5);
303
304 /* Disable HW ARPs on ASF enabled adapters */
305 manc = E1000_READ_REG(hw, E1000_MANC);
306 manc &= ~E1000_MANC_ARP_EN;
307 E1000_WRITE_REG(hw, E1000_MANC, manc);
308
309 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
310 icr = E1000_READ_REG(hw, E1000_ICR);
311
312 return ret_val;
313 }
314
315 /**
316 * e1000_init_hw_82540 - Initialize hardware
317 * @hw: pointer to the HW structure
318 *
319 * This inits the hardware readying it for operation. This is a
320 * function pointer entry point called by the api module.
321 **/
322 static s32 e1000_init_hw_82540(struct e1000_hw *hw)
323 {
324 struct e1000_mac_info *mac = &hw->mac;
325 u32 txdctl, ctrl_ext;
326 s32 ret_val = E1000_SUCCESS;
327 u16 i;
328
329 DEBUGFUNC("e1000_init_hw_82540");
330
331 /* Initialize identification LED */
332 ret_val = e1000_id_led_init_generic(hw);
333 if (ret_val) {
334 DEBUGOUT("Error initializing identification LED\n");
335 /* This is not fatal and we should not stop init due to this */
336 }
337
338 /* Disabling VLAN filtering */
339 DEBUGOUT("Initializing the IEEE VLAN\n");
340 if (mac->type < e1000_82545_rev_3)
341 E1000_WRITE_REG(hw, E1000_VET, 0);
342
343 mac->ops.clear_vfta(hw);
344
345 /* Setup the receive address. */
346 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
347
348 /* Zero out the Multicast HASH table */
349 DEBUGOUT("Zeroing the MTA\n");
350 for (i = 0; i < mac->mta_reg_count; i++) {
351 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
352 /*
353 * Avoid back to back register writes by adding the register
354 * read (flush). This is to protect against some strange
355 * bridge configurations that may issue Memory Write Block
356 * (MWB) to our register space. The *_rev_3 hardware at
357 * least doesn't respond correctly to every other dword in an
358 * MWB to our register space.
359 */
360 E1000_WRITE_FLUSH(hw);
361 }
362
363 if (mac->type < e1000_82545_rev_3)
364 e1000_pcix_mmrbc_workaround_generic(hw);
365
366 /* Setup link and flow control */
367 ret_val = mac->ops.setup_link(hw);
368
369 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
370 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
371 E1000_TXDCTL_FULL_TX_DESC_WB;
372 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
373
374 /*
375 * Clear all of the statistics registers (clear on read). It is
376 * important that we do this after we have tried to establish link
377 * because the symbol error count will increment wildly if there
378 * is no link.
379 */
380 e1000_clear_hw_cntrs_82540(hw);
381
382 if ((hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER) ||
383 (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3)) {
384 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
385 /*
386 * Relaxed ordering must be disabled to avoid a parity
387 * error crash in a PCI slot.
388 */
389 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
390 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
391 }
392
393 return ret_val;
394 }
395
396 /**
397 * e1000_setup_copper_link_82540 - Configure copper link settings
398 * @hw: pointer to the HW structure
399 *
400 * Calls the appropriate function to configure the link for auto-neg or forced
401 * speed and duplex. Then we check for link, once link is established calls
402 * to configure collision distance and flow control are called. If link is
403 * not established, we return -E1000_ERR_PHY (-2). This is a function
404 * pointer entry point called by the api module.
405 **/
406 static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw)
407 {
408 u32 ctrl;
409 s32 ret_val = E1000_SUCCESS;
410 u16 data;
411
412 DEBUGFUNC("e1000_setup_copper_link_82540");
413
414 ctrl = E1000_READ_REG(hw, E1000_CTRL);
415 ctrl |= E1000_CTRL_SLU;
416 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
417 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
418
419 ret_val = e1000_set_phy_mode_82540(hw);
420 if (ret_val)
421 goto out;
422
423 if (hw->mac.type == e1000_82545_rev_3 ||
424 hw->mac.type == e1000_82546_rev_3) {
425 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &data);
426 if (ret_val)
427 goto out;
428 data |= 0x00000008;
429 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, data);
430 if (ret_val)
431 goto out;
432 }
433
434 ret_val = e1000_copper_link_setup_m88(hw);
435 if (ret_val)
436 goto out;
437
438 ret_val = e1000_setup_copper_link_generic(hw);
439
440 out:
441 return ret_val;
442 }
443
444 /**
445 * e1000_setup_fiber_serdes_link_82540 - Setup link for fiber/serdes
446 * @hw: pointer to the HW structure
447 *
448 * Set the output amplitude to the value in the EEPROM and adjust the VCO
449 * speed to improve Bit Error Rate (BER) performance. Configures collision
450 * distance and flow control for fiber and serdes links. Upon successful
451 * setup, poll for link. This is a function pointer entry point called by
452 * the api module.
453 **/
454 static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw)
455 {
456 struct e1000_mac_info *mac = &hw->mac;
457 s32 ret_val = E1000_SUCCESS;
458
459 DEBUGFUNC("e1000_setup_fiber_serdes_link_82540");
460
461 switch (mac->type) {
462 case e1000_82545_rev_3:
463 case e1000_82546_rev_3:
464 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
465 /*
466 * If we're on serdes media, adjust the output
467 * amplitude to value set in the EEPROM.
468 */
469 ret_val = e1000_adjust_serdes_amplitude_82540(hw);
470 if (ret_val)
471 goto out;
472 }
473 /* Adjust VCO speed to improve BER performance */
474 ret_val = e1000_set_vco_speed_82540(hw);
475 if (ret_val)
476 goto out;
477 default:
478 break;
479 }
480
481 ret_val = e1000_setup_fiber_serdes_link_generic(hw);
482
483 out:
484 return ret_val;
485 }
486
487 /**
488 * e1000_adjust_serdes_amplitude_82540 - Adjust amplitude based on EEPROM
489 * @hw: pointer to the HW structure
490 *
491 * Adjust the SERDES output amplitude based on the EEPROM settings.
492 **/
493 static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw)
494 {
495 s32 ret_val = E1000_SUCCESS;
496 u16 nvm_data;
497
498 DEBUGFUNC("e1000_adjust_serdes_amplitude_82540");
499
500 ret_val = hw->nvm.ops.read(hw, NVM_SERDES_AMPLITUDE, 1, &nvm_data);
501 if (ret_val)
502 goto out;
503
504 if (nvm_data != NVM_RESERVED_WORD) {
505 /* Adjust serdes output amplitude only. */
506 nvm_data &= NVM_SERDES_AMPLITUDE_MASK;
507 ret_val = hw->phy.ops.write_reg(hw,
508 M88E1000_PHY_EXT_CTRL,
509 nvm_data);
510 if (ret_val)
511 goto out;
512 }
513
514 out:
515 return ret_val;
516 }
517
518 /**
519 * e1000_set_vco_speed_82540 - Set VCO speed for better performance
520 * @hw: pointer to the HW structure
521 *
522 * Set the VCO speed to improve Bit Error Rate (BER) performance.
523 **/
524 static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw)
525 {
526 s32 ret_val = E1000_SUCCESS;
527 u16 default_page = 0;
528 u16 phy_data;
529
530 DEBUGFUNC("e1000_set_vco_speed_82540");
531
532 /* Set PHY register 30, page 5, bit 8 to 0 */
533
534 ret_val = hw->phy.ops.read_reg(hw,
535 M88E1000_PHY_PAGE_SELECT,
536 &default_page);
537 if (ret_val)
538 goto out;
539
540 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
541 if (ret_val)
542 goto out;
543
544 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
545 if (ret_val)
546 goto out;
547
548 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
549 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
550 if (ret_val)
551 goto out;
552
553 /* Set PHY register 30, page 4, bit 11 to 1 */
554
555 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
556 if (ret_val)
557 goto out;
558
559 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
560 if (ret_val)
561 goto out;
562
563 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
564 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
565 if (ret_val)
566 goto out;
567
568 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
569 default_page);
570
571 out:
572 return ret_val;
573 }
574
575 /**
576 * e1000_set_phy_mode_82540 - Set PHY to class A mode
577 * @hw: pointer to the HW structure
578 *
579 * Sets the PHY to class A mode and assumes the following operations will
580 * follow to enable the new class mode:
581 * 1. Do a PHY soft reset.
582 * 2. Restart auto-negotiation or force link.
583 **/
584 static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw)
585 {
586 struct e1000_phy_info *phy = &hw->phy;
587 s32 ret_val = E1000_SUCCESS;
588 u16 nvm_data;
589
590 DEBUGFUNC("e1000_set_phy_mode_82540");
591
592 if (hw->mac.type != e1000_82545_rev_3)
593 goto out;
594
595 ret_val = hw->nvm.ops.read(hw, NVM_PHY_CLASS_WORD, 1, &nvm_data);
596 if (ret_val) {
597 ret_val = -E1000_ERR_PHY;
598 goto out;
599 }
600
601 if ((nvm_data != NVM_RESERVED_WORD) && (nvm_data & NVM_PHY_CLASS_A)) {
602 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
603 0x000B);
604 if (ret_val) {
605 ret_val = -E1000_ERR_PHY;
606 goto out;
607 }
608 ret_val = hw->phy.ops.write_reg(hw,
609 M88E1000_PHY_GEN_CONTROL,
610 0x8104);
611 if (ret_val) {
612 ret_val = -E1000_ERR_PHY;
613 goto out;
614 }
615
616 phy->reset_disable = FALSE;
617 }
618
619 out:
620 return ret_val;
621 }
622
623 /**
624 * e1000_power_down_phy_copper_82540 - Remove link in case of PHY power down
625 * @hw: pointer to the HW structure
626 *
627 * In the case of a PHY power down to save power, or to turn off link during a
628 * driver unload, or wake on lan is not enabled, remove the link.
629 **/
630 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw)
631 {
632 /* If the management interface is not enabled, then power down */
633 if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
634 e1000_power_down_phy_copper(hw);
635
636 return;
637 }
638
639 /**
640 * e1000_clear_hw_cntrs_82540 - Clear device specific hardware counters
641 * @hw: pointer to the HW structure
642 *
643 * Clears the hardware counters by reading the counter registers.
644 **/
645 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw)
646 {
647 volatile u32 temp;
648
649 DEBUGFUNC("e1000_clear_hw_cntrs_82540");
650
651 e1000_clear_hw_cntrs_base_generic(hw);
652
653 temp = E1000_READ_REG(hw, E1000_PRC64);
654 temp = E1000_READ_REG(hw, E1000_PRC127);
655 temp = E1000_READ_REG(hw, E1000_PRC255);
656 temp = E1000_READ_REG(hw, E1000_PRC511);
657 temp = E1000_READ_REG(hw, E1000_PRC1023);
658 temp = E1000_READ_REG(hw, E1000_PRC1522);
659 temp = E1000_READ_REG(hw, E1000_PTC64);
660 temp = E1000_READ_REG(hw, E1000_PTC127);
661 temp = E1000_READ_REG(hw, E1000_PTC255);
662 temp = E1000_READ_REG(hw, E1000_PTC511);
663 temp = E1000_READ_REG(hw, E1000_PTC1023);
664 temp = E1000_READ_REG(hw, E1000_PTC1522);
665
666 temp = E1000_READ_REG(hw, E1000_ALGNERRC);
667 temp = E1000_READ_REG(hw, E1000_RXERRC);
668 temp = E1000_READ_REG(hw, E1000_TNCRS);
669 temp = E1000_READ_REG(hw, E1000_CEXTERR);
670 temp = E1000_READ_REG(hw, E1000_TSCTC);
671 temp = E1000_READ_REG(hw, E1000_TSCTFC);
672
673 temp = E1000_READ_REG(hw, E1000_MGTPRC);
674 temp = E1000_READ_REG(hw, E1000_MGTPDC);
675 temp = E1000_READ_REG(hw, E1000_MGTPTC);
676 }
677
A totally sweet operating system