workbench/devs/networks/e1000/e1000_manage.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 #include "e1000_api.h"
  30 #include "e1000_manage.h"
  31
  32 static u8 e1000_calculate_checksum(u8 *buffer, u32 length);
  33
  34 /**
  35  *  e1000_calculate_checksum - Calculate checksum for buffer
  36  *  @buffer: pointer to EEPROM
  37  *  @length: size of EEPROM to calculate a checksum for
  38  *
  39  *  Calculates the checksum for some buffer on a specified length.  The
  40  *  checksum calculated is returned.
  41  **/
  42 static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
  43 {
  44         u32 i;
  45         u8  sum = 0;
  46
  47 //      DEBUGFUNC("e1000_calculate_checksum");
  48
  49         if (!buffer)
  50                 return 0;
  51
  52         for (i = 0; i < length; i++)
  53                 sum += buffer[i];
  54
  55         return (u8) (0 - sum);
  56 }
  57
  58 /**
  59  *  e1000_mng_enable_host_if_generic - Checks host interface is enabled
  60  *  @hw: pointer to the HW structure
  61  *
  62  *  Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
  63  *
  64  *  This function checks whether the HOST IF is enabled for command operation
  65  *  and also checks whether the previous command is completed.  It busy waits
  66  *  in case of previous command is not completed.
  67  **/
  68 s32 e1000_mng_enable_host_if_generic(struct e1000_hw * hw)
  69 {
  70         u32 hicr;
  71         s32 ret_val = E1000_SUCCESS;
  72         u8  i;
  73
  74         DEBUGFUNC("e1000_mng_enable_host_if_generic");
  75
  76         /* Check that the host interface is enabled. */
  77         hicr = E1000_READ_REG(hw, E1000_HICR);
  78         if ((hicr & E1000_HICR_EN) == 0) {
  79                 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
  80                 ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
  81                 goto out;
  82         }
  83         /* check the previous command is completed */
  84         for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
  85                 hicr = E1000_READ_REG(hw, E1000_HICR);
  86                 if (!(hicr & E1000_HICR_C))
  87                         break;
  88                 msec_delay_irq(1);
  89         }
  90
  91         if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
  92                 DEBUGOUT("Previous command timeout failed .\n");
  93                 ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
  94                 goto out;
  95         }
  96
  97 out:
  98         return ret_val;
  99 }
 100
 101 /**
 102  *  e1000_check_mng_mode_generic - Generic check management mode
 103  *  @hw: pointer to the HW structure
 104  *
 105  *  Reads the firmware semaphore register and returns true (>0) if
 106  *  manageability is enabled, else false (0).
 107  **/
 108 bool e1000_check_mng_mode_generic(struct e1000_hw *hw)
 109 {
 110         u32 fwsm;
 111
 112         DEBUGFUNC("e1000_check_mng_mode_generic");
 113
 114         fwsm = E1000_READ_REG(hw, E1000_FWSM);
 115
 116         return ((fwsm & E1000_FWSM_MODE_MASK) ==
 117                 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 118 }
 119
 120 /**
 121  *  e1000_enable_tx_pkt_filtering_generic - Enable packet filtering on TX
 122  *  @hw: pointer to the HW structure
 123  *
 124  *  Enables packet filtering on transmit packets if manageability is enabled
 125  *  and host interface is enabled.
 126  **/
 127 bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw)
 128 {
 129         struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
 130         u32 *buffer = (u32 *)&hw->mng_cookie;
 131         u32 offset;
 132         s32 ret_val, hdr_csum, csum;
 133         u8 i, len;
 134         bool tx_filter = TRUE;
 135
 136         DEBUGFUNC("e1000_enable_tx_pkt_filtering_generic");
 137
 138         /* No manageability, no filtering */
 139         if (!hw->mac.ops.check_mng_mode(hw)) {
 140                 tx_filter = FALSE;
 141                 goto out;
 142         }
 143
 144         /*
 145          * If we can't read from the host interface for whatever
 146          * reason, disable filtering.
 147          */
 148         ret_val = hw->mac.ops.mng_enable_host_if(hw);
 149         if (ret_val != E1000_SUCCESS) {
 150                 tx_filter = FALSE;
 151                 goto out;
 152         }
 153
 154         /* Read in the header.  Length and offset are in dwords. */
 155         len    = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
 156         offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
 157         for (i = 0; i < len; i++) {
 158                 *(buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw,
 159                                                            E1000_HOST_IF,
 160                                                            offset + i);
 161         }
 162         hdr_csum = hdr->checksum;
 163         hdr->checksum = 0;
 164         csum = e1000_calculate_checksum((u8 *)hdr,
 165                                         E1000_MNG_DHCP_COOKIE_LENGTH);
 166         /*
 167          * If either the checksums or signature don't match, then
 168          * the cookie area isn't considered valid, in which case we
 169          * take the safe route of assuming Tx filtering is enabled.
 170          */
 171         if (hdr_csum != csum)
 172                 goto out;
 173         if (hdr->signature != E1000_IAMT_SIGNATURE)
 174                 goto out;
 175
 176         /* Cookie area is valid, make the final check for filtering. */
 177         if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING))
 178                 tx_filter = FALSE;
 179
 180 out:
 181         hw->mac.tx_pkt_filtering = tx_filter;
 182         return tx_filter;
 183 }
 184
 185 /**
 186  *  e1000_mng_write_dhcp_info_generic - Writes DHCP info to host interface
 187  *  @hw: pointer to the HW structure
 188  *  @buffer: pointer to the host interface
 189  *  @length: size of the buffer
 190  *
 191  *  Writes the DHCP information to the host interface.
 192  **/
 193 s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw * hw, u8 *buffer,
 194                                       u16 length)
 195 {
 196         struct e1000_host_mng_command_header hdr;
 197         s32 ret_val;
 198         u32 hicr;
 199
 200         DEBUGFUNC("e1000_mng_write_dhcp_info_generic");
 201
 202         hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
 203         hdr.command_length = length;
 204         hdr.reserved1 = 0;
 205         hdr.reserved2 = 0;
 206         hdr.checksum = 0;
 207
 208         /* Enable the host interface */
 209         ret_val = hw->mac.ops.mng_enable_host_if(hw);
 210         if (ret_val)
 211                 goto out;
 212
 213         /* Populate the host interface with the contents of "buffer". */
 214         ret_val = hw->mac.ops.mng_host_if_write(hw, buffer, length,
 215                                           sizeof(hdr), &(hdr.checksum));
 216         if (ret_val)
 217                 goto out;
 218
 219         /* Write the manageability command header */
 220         ret_val = hw->mac.ops.mng_write_cmd_header(hw, &hdr);
 221         if (ret_val)
 222                 goto out;
 223
 224         /* Tell the ARC a new command is pending. */
 225         hicr = E1000_READ_REG(hw, E1000_HICR);
 226         E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
 227
 228 out:
 229         return ret_val;
 230 }
 231
 232 /**
 233  *  e1000_mng_write_cmd_header_generic - Writes manageability command header
 234  *  @hw: pointer to the HW structure
 235  *  @hdr: pointer to the host interface command header
 236  *
 237  *  Writes the command header after does the checksum calculation.
 238  **/
 239 s32 e1000_mng_write_cmd_header_generic(struct e1000_hw * hw,
 240                                     struct e1000_host_mng_command_header * hdr)
 241 {
 242         u16 i, length = sizeof(struct e1000_host_mng_command_header);
 243
 244         DEBUGFUNC("e1000_mng_write_cmd_header_generic");
 245
 246         /* Write the whole command header structure with new checksum. */
 247
 248         hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
 249
 250         length >>= 2;
 251         /* Write the relevant command block into the ram area. */
 252         for (i = 0; i < length; i++) {
 253                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
 254                                             *((u32 *) hdr + i));
 255                 E1000_WRITE_FLUSH(hw);
 256         }
 257
 258         return E1000_SUCCESS;
 259 }
 260
 261 /**
 262  *  e1000_mng_host_if_write_generic - Write to the manageability host interface
 263  *  @hw: pointer to the HW structure
 264  *  @buffer: pointer to the host interface buffer
 265  *  @length: size of the buffer
 266  *  @offset: location in the buffer to write to
 267  *  @sum: sum of the data (not checksum)
 268  *
 269  *  This function writes the buffer content at the offset given on the host if.
 270  *  It also does alignment considerations to do the writes in most efficient
 271  *  way.  Also fills up the sum of the buffer in *buffer parameter.
 272  **/
 273 s32 e1000_mng_host_if_write_generic(struct e1000_hw * hw, u8 *buffer,
 274                                     u16 length, u16 offset, u8 *sum)
 275 {
 276         u8 *tmp;
 277         u8 *bufptr = buffer;
 278         u32 data = 0;
 279         s32 ret_val = E1000_SUCCESS;
 280         u16 remaining, i, j, prev_bytes;
 281
 282         DEBUGFUNC("e1000_mng_host_if_write_generic");
 283
 284         /* sum = only sum of the data and it is not checksum */
 285
 286         if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
 287                 ret_val = -E1000_ERR_PARAM;
 288                 goto out;
 289         }
 290
 291         tmp = (u8 *)&data;
 292         prev_bytes = offset & 0x3;
 293         offset >>= 2;
 294
 295         if (prev_bytes) {
 296                 data = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset);
 297                 for (j = prev_bytes; j < sizeof(u32); j++) {
 298                         *(tmp + j) = *bufptr++;
 299                         *sum += *(tmp + j);
 300                 }
 301                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset, data);
 302                 length -= j - prev_bytes;
 303                 offset++;
 304         }
 305
 306         remaining = length & 0x3;
 307         length -= remaining;
 308
 309         /* Calculate length in DWORDs */
 310         length >>= 2;
 311
 312         /*
 313          * The device driver writes the relevant command block into the
 314          * ram area.
 315          */
 316         for (i = 0; i < length; i++) {
 317                 for (j = 0; j < sizeof(u32); j++) {
 318                         *(tmp + j) = *bufptr++;
 319                         *sum += *(tmp + j);
 320                 }
 321
 322                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i, data);
 323         }
 324         if (remaining) {
 325                 for (j = 0; j < sizeof(u32); j++) {
 326                         if (j < remaining)
 327                                 *(tmp + j) = *bufptr++;
 328                         else
 329                                 *(tmp + j) = 0;
 330
 331                         *sum += *(tmp + j);
 332                 }
 333                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i, data);
 334         }
 335
 336 out:
 337         return ret_val;
 338 }
 339
 340 /**
 341  *  e1000_enable_mng_pass_thru - Enable processing of ARP's
 342  *  @hw: pointer to the HW structure
 343  *
 344  *  Verifies the hardware needs to allow ARPs to be processed by the host.
 345  **/
 346 bool e1000_enable_mng_pass_thru(struct e1000_hw *hw)
 347 {
 348         u32 manc;
 349         u32 fwsm, factps;
 350         bool ret_val = FALSE;
 351
 352         DEBUGFUNC("e1000_enable_mng_pass_thru");
 353
 354         if (!hw->mac.asf_firmware_present)
 355                 goto out;
 356
 357         manc = E1000_READ_REG(hw, E1000_MANC);
 358
 359         if (!(manc & E1000_MANC_RCV_TCO_EN) ||
 360             !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
 361                 goto out;
 362
 363         if (hw->mac.arc_subsystem_valid) {
 364                 fwsm = E1000_READ_REG(hw, E1000_FWSM);
 365                 factps = E1000_READ_REG(hw, E1000_FACTPS);
 366
 367                 if (!(factps & E1000_FACTPS_MNGCG) &&
 368                     ((fwsm & E1000_FWSM_MODE_MASK) ==
 369                      (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
 370                         ret_val = TRUE;
 371                         goto out;
 372                 }
 373         } else {
 374                 if ((manc & E1000_MANC_SMBUS_EN) &&
 375                     !(manc & E1000_MANC_ASF_EN)) {
 376                         ret_val = TRUE;
 377                         goto out;
 378                 }
 379         }
 380
 381 out:
 382         return ret_val;
 383 }
 384