arch/.unmaintained/m68k-native/exec/cacheclearu.s

   1 /*
   2     Copyright © 1995-2001, The AROS Development Team. All rights reserved.
   3     $Id$
   4 */
   5
   6 /*****************************************************************************
   7
   8     NAME
   9
  10         AROS_LH0(void, CacheClearU,
  11
  12     LOCATION
  13         struct ExecBase *, SysBase, 106, Exec)
  14
  15     FUNCTION
  16         Flushes the contents of all CPU caches in a simple way.
  17
  18     INPUTS
  19
  20     RESULT
  21
  22     NOTES
  23
  24     EXAMPLE
  25
  26     BUGS
  27
  28     SEE ALSO
  29
  30     INTERNALS
  31         68000/10: do nothing
  32         68020/30: clear instruction cache and (030) data cache
  33         68040/60: push dirty lines to memory and invalidate both caches
  34
  35     HISTORY
  36
  37 ******************************************************************************/
  38
  39
  40 /*
  41    XDEF AROS_SLIB_ENTRY(CacheClearU,Exec)       ; for 68000/68010
  42    XDEF AROS_SLIB_ENTRY(CacheClearU_20,Exec)    ; for 68020/68030
  43    XDEF AROS_SLIB_ENTRY(CacheClearU_40,Exec)    ; for 68040/68060
  44    XDEF AROS_SLIB_ENTRY(CacheClearU_60,Exec)    ; for 68060 (clears not only
  45                                                 ; the i and d caches, but also
  46                                                 ; the branch cache)
  47 */
  48
  49         #include "machine.i"
  50
  51         .text
  52         .balign 4
  53         .globl  AROS_SLIB_ENTRY(CacheClearU,Exec)
  54         .type   AROS_SLIB_ENTRY(CacheClearU,Exec),@function
  55 AROS_SLIB_ENTRY(CacheClearU,Exec):
  56         /* Simple 68000s have no chaches */
  57         rts
  58
  59         .text
  60         .balign 4
  61         .globl  AROS_SLIB_ENTRY(CacheClearU_20,Exec)
  62         .type   AROS_SLIB_ENTRY(CacheClearU_20,Exec),@function
  63 AROS_SLIB_ENTRY(CacheClearU_20,Exec):
  64         move.l  a5,a1           /* Save a5 */
  65         lea.l   cacheclearusup_20(pc),a5
  66         jmp     Supervisor(a6)  /* No jsr: this saves an rts */
  67
  68 cacheclearusup_20:
  69         or.w    #0x0700,sr      /* Disable interrupts so cacr can not be influenced
  70                                    while we clear the caches */
  71         movec   cacr,d0
  72         or.w    #0x0808,d0      /* Set CD and CI bit in cacr */
  73         movec   d0,cacr
  74         move.l  a1,a5           /* Restore a5 */
  75         rte                     /* This rte will restore the SR from the stack */
  76
  77         .text
  78         .balign 4
  79         .globl  AROS_SLIB_ENTRY(CacheClearU_40,Exec)
  80         .type   AROS_SLIB_ENTRY(CacheClearU_40,Exec),@function
  81 AROS_SLIB_ENTRY(CacheClearU_40,Exec):
  82         move.l  a5,a1
  83         lea.l   cacheclearusup_40(pc),a5
  84         jmp     Supervisor(a6)
  85
  86 cacheclearusup_40:
  87         cpusha  bc      /* Push dirty cache lines to memory and invalidate both caches */
  88         cinva   bc      /* 68060 invalidates depending on DPI (Disable CPUSH invalidation)
  89                            bit of CACR. Force an invalidation with CINV. */
  90         move.l  a1,a5
  91         rte
  92
  93         .text
  94         .balign 4
  95         .globl  AROS_SLIB_ENTRY(CacheClearU_60,Exec)
  96         .type   AROS_SLIB_ENTRY(CacheClearU_60,Exec),@function
  97 AROS_SLIB_ENTRY(CacheClearU_60,Exec):
  98         move.l  a5,a1
  99         lea.l   cacheclearusup_60(pc),a5
 100         jmp     Supervisor(a6)
 101
 102 cacheclearusup_60:
 103         cpusha  bc      /* Push dirty cache lines to memory and invalidate both caches */
 104         cinva   bc      /* 68060 invalidates depending on DPI (Disable CPUSH invalidation)
 105                            bit of CACR. Force an invalidation with CINV. */
 106         or.w    #0x0700,sr
 107         movec   cacr,d0
 108         bset.l  #20,d0          /* set CABC Clear All (entries in) Branch Cache bit */
 109         movec   d0,cacr         /* clear Branch Cache */
 110         move.l  a1,a5
 111         rte
 112