arch/.unmaintained/m68k-native/exec/cachepredma.s

   1 /*
   2     Copyright © 1995-2001, The AROS Development Team. All rights reserved.
   3     $Id$
   4 */
   5
   6 /*****************************************************************************
   7
   8     NAME
   9
  10         AROS_LH3(APTR, CachePreDMA,
  11
  12     SYNOPSIS
  13         AROS_LHA(APTR,    address, A0),
  14         AROS_LHA(ULONG *, length,  A1),
  15         AROS_LHA(ULONG,   flags,  D0),
  16
  17     LOCATION
  18         struct ExecBase *, SysBase, 127, Exec)
  19
  20     FUNCTION
  21         Do everything necessary to make CPU caches aware that a DMA will happen.
  22         Virtual memory systems will make it possible that your memory is not at
  23         one block and not at the address you thought. This function gives you
  24         all the information you need to split the DMA request up and to convert
  25         virtual to physical addresses.
  26
  27     INPUTS
  28         address - Virtual address of memory affected by the DMA
  29         *length - Number of bytes affected
  30         flags   - DMA_Continue    - This is a call to continue a request that
  31                                     was broken up.
  32                   DMA_ReadFromRAM - Indicate that the DMA goes from RAM
  33                                     to the device. Set this bit in bot calls.
  34
  35     RESULT
  36         The physical address in memory.
  37         *length contains the number of contiguous bytes in physical memory.
  38
  39     NOTES
  40         DMA must follow a call to CachePreDMA() and must be followed
  41         by a call to CachePostDMA().
  42
  43     EXAMPLE
  44
  45     BUGS
  46
  47     SEE ALSO
  48         CachePostDMA()
  49
  50     INTERNALS
  51
  52     HISTORY
  53
  54 ******************************************************************************/
  55
  56 /*
  57    XDEF AROS_SLIB_ENTRY(CachePreDMA,Exec)       ; for 68000/10/20/30
  58    XDEF AROS_SLIB_ENTRY(CachePreDMA_40,Exec)    ; for 68040+
  59 */
  60
  61         #include "machine.i"
  62
  63         .text
  64         .balign 4
  65         .globl  AROS_SLIB_ENTRY(CachePreDMA,Exec)
  66         .type   AROS_SLIB_ENTRY(CachePreDMA,Exec),@function
  67 AROS_SLIB_ENTRY(CachePreDMA,Exec):
  68         move.l  a0,d0   /* return input address */
  69         rts
  70
  71         .text
  72         .balign 4
  73         .globl  AROS_SLIB_ENTRY(CachePreDMA_40,Exec)
  74         .type   AROS_SLIB_ENTRY(CachePreDMA_40,Exec),@function
  75 AROS_SLIB_ENTRY(CachePreDMA_40,Exec):
  76         move.l  a5,a1           /* save a5 */
  77         lea.l   cachepredmasup_40(pc),a5
  78         jmp     Supervisor(a6)
  79
  80 cachepredmasup_40:
  81         cpusha  dc      /* Push dirty data cache lines to memory and invalidate cache */
  82         cinva   dc      /* 68060 invalidates depending on DPI (Disable CPUSH invalidation)
  83                            bit of CACR. Force an invalidation with CINV. */
  84         move.l  a0,d0   /* return input address */
  85         rte