added concrete implementations of putc(), getc(), getchar() and gets()
[tangerine.git] / arch / .unmaintained / m68k-native / exec / exception.s
blob16652a9c4f8f36d81f46acdd30c18e2dd2318672
1 /*
2 Copyright © 1995-2001, The AROS Development Team. All rights reserved.
3 $Id$
4 */
6 /*****************************************************************************
8 NAME
9 AROS_LH0(void, Exception,
11 LOCATION
12 struct ExecBase *, SysBase, 11, Exec)
14 FUNCTION
15 Exception handler. This function is called by the dispatcher if a
16 exception has to be delivered. It is called in Disable()d state
17 (atomically) so that all Signals are still unchanged.
18 TF_EXCEPT is still set and must be reset by this routine.
20 INPUTS
22 RESULT
24 NOTES
25 This function has a context on its own and does not need to preserve
26 any registers.
28 Internal exec function.
30 EXAMPLE
32 BUGS
34 SEE ALSO
36 INTERNALS
38 HISTORY
40 ******************************************************************************/
42 #include "machine.i"
44 .text
45 .balign 4
46 .globl AROS_SLIB_ENTRY(Exception,Exec)
47 .type AROS_SLIB_ENTRY(Exception,Exec),@function
48 AROS_SLIB_ENTRY(Exception,Exec):
49 /* First clear task exception bit. */
50 move.l ThisTask(a6),a2
51 bclr #TB_EXCEPT,tc_Flags(a2)
53 /* If the exception is raised out of a Wait()
54 IDNestCnt may be almost everything.
55 Store nesting level and set it to a
56 defined value 1 beyond -1.
58 excusr: move.b IDNestCnt(a6),d2
59 clr.b IDNestCnt(a6)
61 exloop: /* get signals causing the exception (do nothing if there are none) */
62 move.l tc_SigExcept(a2),d0
63 and.l tc_SigRecvd(a2),d0
64 beq excend
66 /* disable the signals */
67 eor.l d0,tc_SigExcept(a2)
68 eor.l d0,tc_SigRecvd(a2)
70 /* call the exception vector with interrupts enabled */
71 move.l tc_ExceptData(a2),a1
72 move.l tc_ExceptCode(a2),a0
73 jsr Enable(a6)
74 jsr (a0)
75 jsr Disable(a6)
77 /* reenable signals and look again */
78 or.l d0,tc_SigExcept(a2)
79 bra exloop
81 /* restore state of Disable() and return */
82 excend: move.b d2,IDNestCnt(a6)
83 rts