arch/i386-pc/Drivers/serial.hidd/serial_intern.h

   1 /*
   2     Copyright © 1995-2007, The AROS Development Team. All rights reserved.
   3     $Id$
   4 */
   5
   6 #ifndef SERIAL_HIDD_INTERN_H
   7 #define SERIAL_HIDD_INTERN_H
   8
   9 /* Include files */
  10
  11 // #include <sys/termios.h>
  12
  13 #ifndef EXEC_LIBRARIES_H
  14 #   include <exec/libraries.h>
  15 #endif
  16 #ifndef OOP_OOP_H
  17 #   include <oop/oop.h>
  18 #endif
  19 #ifndef HIDD_SERIAL_H
  20 #   include <hidd/serial.h>
  21 #endif
  22 #include <dos/dos.h>
  23
  24 #define SER_MAX_UNITS   4
  25
  26 struct HIDDSerialData
  27 {
  28     OOP_Class *SerialHIDDClass;
  29
  30     OOP_Object          *SerialUnits[SER_MAX_UNITS];
  31     UBYTE               usedunits;
  32 };
  33
  34 #define SER_UNIT_0_F    1
  35 #define SER_UNIT_1_F    2
  36 #define SER_UNIT_2_F    4
  37 #define SER_UNIT_3_F    8
  38
  39 struct HIDDSerialUnitData
  40 {
  41     ULONG (*DataWriteCallBack)  (ULONG unitnum, APTR userdata);
  42     VOID (*DataReceivedCallBack)(UBYTE *buffer, ULONG len, ULONG unitnum, APTR userdata);
  43     VOID                *DataWriteUserData;
  44     VOID                *DataReceivedUserData;
  45
  46     ULONG               unitnum;
  47     ULONG               baseaddr;
  48     ULONG               baudrate;
  49     UBYTE               datalength;
  50     BOOL                parity;
  51     UBYTE               paritytype;
  52     UBYTE               stopbits;
  53     BOOL                breakcontrol;
  54     BOOL                stopped;
  55 };
  56
  57 struct class_static_data
  58 {
  59     OOP_Class            *serialhiddclass;
  60     OOP_Class            *serialunitclass;
  61
  62     OOP_Object               *irqhidd;
  63
  64     struct HIDDSerialUnitData   *units[SER_MAX_UNITS];
  65     OOP_AttrBase                hiddSerialUnitAB;
  66 };
  67
  68 #define __IHidd_SerialUnitAB   (csd->hiddSerialUnitAB)
  69
  70 #define SER_DEFAULT_BAUDRATE    57600
  71
  72
  73
  74 /* Library base */
  75
  76 struct IntHIDDSerialBase
  77 {
  78     struct Library            hdg_LibNode;
  79
  80     struct class_static_data  hdg_csd;
  81 };
  82
  83
  84 #define CSD(x) (&((struct IntHIDDSerialBase *)x)->hdg_csd)
  85
  86 /* pre declarations */
  87
  88 OOP_Class *init_serialhiddclass(struct class_static_data *csd);
  89 void   free_serialhiddclass(struct class_static_data *csd);
  90
  91 OOP_Class *init_serialunitclass(struct class_static_data *csd);
  92 void   free_serialunitclass(struct class_static_data *csd);
  93
  94
  95 /*
  96    UART specific defines.
  97    Taken from /usr/include/linux/serial_reg.h
  98 */
  99
 100 #define UART_RX         0       /* In:  Receive buffer (DLAB=0) */
 101 #define UART_TX         0       /* Out: Transmit buffer (DLAB=0) */
 102 #define UART_DLL        0       /* Out: Divisor Latch Low (DLAB=1) */
 103 #define UART_DLM        1       /* Out: Divisor Latch High (DLAB=1) */
 104 #define UART_IER        1       /* Out: Interrupt Enable Register */
 105 #define UART_IIR        2       /* In:  Interrupt ID Register */
 106 #define UART_FCR        2       /* Out: FIFO Control Register */
 107 #define UART_EFR        2       /* I/O: Extended Features Register */
 108                                 /* (DLAB=1, 16C660 only) */
 109 #define UART_LCR        3       /* Out: Line Control Register */
 110 #define UART_MCR        4       /* Out: Modem Control Register */
 111 #define UART_LSR        5       /* In:  Line Status Register */
 112 #define UART_MSR        6       /* In:  Modem Status Register */
 113 #define UART_SCR        7       /* I/O: Scratch Register */
 114
 115 /*
 116  * These are the definitions for the FIFO Control Register
 117  * (16650 only)
 118  */
 119 #define UART_FCR_ENABLE_FIFO    0x01 /* Enable the FIFO */
 120 #define UART_FCR_CLEAR_RCVR     0x02 /* Clear the RCVR FIFO */
 121 #define UART_FCR_CLEAR_XMIT     0x04 /* Clear the XMIT FIFO */
 122 #define UART_FCR_DMA_SELECT     0x08 /* For DMA applications */
 123 #define UART_FCR_TRIGGER_MASK   0xC0 /* Mask for the FIFO trigger range */
 124 #define UART_FCR_TRIGGER_1      0x00 /* Mask for trigger set at 1 */
 125 #define UART_FCR_TRIGGER_4      0x40 /* Mask for trigger set at 4 */
 126 #define UART_FCR_TRIGGER_8      0x80 /* Mask for trigger set at 8 */
 127 #define UART_FCR_TRIGGER_14     0xC0 /* Mask for trigger set at 14 */
 128 /* 16650 redefinitions */
 129 #define UART_FCR6_R_TRIGGER_8   0x00 /* Mask for receive trigger set at 1 */
 130 #define UART_FCR6_R_TRIGGER_16  0x40 /* Mask for receive trigger set at 4 */
 131 #define UART_FCR6_R_TRIGGER_24  0x80 /* Mask for receive trigger set at 8 */
 132 #define UART_FCR6_R_TRIGGER_28  0xC0 /* Mask for receive trigger set at 14 */
 133 #define UART_FCR6_T_TRIGGER_16  0x00 /* Mask for transmit trigger set at 16 */
 134 #define UART_FCR6_T_TRIGGER_8   0x10 /* Mask for transmit trigger set at 8 */
 135 #define UART_FCR6_T_TRIGGER_24  0x20 /* Mask for transmit trigger set at 24 */
 136 #define UART_FCR6_T_TRIGGER_30  0x30 /* Mask for transmit trigger set at 30 */
 137 /* TI 16750 definitions */
 138 #define UART_FCR7_64BYTE        0x20 /* Go into 64 byte mode */
 139
 140 /*
 141  * These are the definitions for the Line Control Register
 142  *
 143  * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
 144  * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
 145  */
 146 #define UART_LCR_DLAB   0x80    /* Divisor latch access bit */
 147 #define UART_LCR_SBC    0x40    /* Set break control */
 148 #define UART_LCR_SPAR   0x20    /* Stick parity (?) */
 149 #define UART_LCR_EPAR   0x10    /* Even parity select */
 150 #define UART_LCR_PARITY 0x08    /* Parity Enable */
 151 #define UART_LCR_STOP   0x04    /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
 152 #define UART_LCR_WLEN5  0x00    /* Wordlength: 5 bits */
 153 #define UART_LCR_WLEN6  0x01    /* Wordlength: 6 bits */
 154 #define UART_LCR_WLEN7  0x02    /* Wordlength: 7 bits */
 155 #define UART_LCR_WLEN8  0x03    /* Wordlength: 8 bits */
 156
 157 /*
 158  * These are the definitions for the Line Status Register
 159  */
 160 #define UART_LSR_TEMT   0x40    /* Transmitter empty */
 161 #define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
 162 #define UART_LSR_BI     0x10    /* Break interrupt indicator */
 163 #define UART_LSR_FE     0x08    /* Frame error indicator */
 164 #define UART_LSR_PE     0x04    /* Parity error indicator */
 165 #define UART_LSR_OE     0x02    /* Overrun error indicator */
 166 #define UART_LSR_DR     0x01    /* Receiver data ready */
 167
 168 /*
 169  * These are the definitions for the Interrupt Identification Register
 170  */
 171 #define UART_IIR_NO_INT 0x01    /* No interrupts pending */
 172 #define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
 173
 174 #define UART_IIR_MSI    0x00    /* Modem status interrupt */
 175 #define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
 176 #define UART_IIR_RDI    0x04    /* Receiver data interrupt */
 177 #define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
 178
 179 /*
 180  * These are the definitions for the Interrupt Enable Register
 181  */
 182 #define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
 183 #define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
 184 #define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
 185 #define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
 186 /*
 187  * Sleep mode for ST16650 and TI16750.
 188  * Note that for 16650, EFR-bit 4 must be selected as well.
 189  */
 190 #define UART_IERX_SLEEP  0x10   /* Enable sleep mode */
 191
 192 /*
 193  * These are the definitions for the Modem Control Register
 194  */
 195 #define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
 196 #define UART_MCR_OUT2   0x08    /* Out2 complement */
 197 #define UART_MCR_OUT1   0x04    /* Out1 complement */
 198 #define UART_MCR_RTS    0x02    /* RTS complement */
 199 #define UART_MCR_DTR    0x01    /* DTR complement */
 200
 201 /*
 202  * These are the definitions for the Modem Status Register
 203  */
 204 #define UART_MSR_DCD    0x80    /* Data Carrier Detect */
 205 #define UART_MSR_RI     0x40    /* Ring Indicator */
 206 #define UART_MSR_DSR    0x20    /* Data Set Ready */
 207 #define UART_MSR_CTS    0x10    /* Clear to Send */
 208 #define UART_MSR_DDCD   0x08    /* Delta DCD */
 209 #define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
 210 #define UART_MSR_DDSR   0x02    /* Delta DSR */
 211 #define UART_MSR_DCTS   0x01    /* Delta CTS */
 212 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
 213
 214 /*
 215  * These are the definitions for the Extended Features Register
 216  * (StarTech 16C660 only, when DLAB=1)
 217  */
 218 #define UART_EFR_CTS    0x80    /* CTS flow control */
 219 #define UART_EFR_RTS    0x40    /* RTS flow control */
 220 #define UART_EFR_SCD    0x20    /* Special character detect */
 221 #define UART_EFR_ECB    0x10    /* Enhanced control bit */
 222 /*
 223  * the low four bits control software flow control
 224  */
 225
 226
 227 #endif /* SERIAL_HIDD_INTERN_H */