arch/ppc-sam440/include/asm/amcc440.h

   1 #ifndef ASM_AMCC440_H
   2 #define ASM_AMCC440_H
   3
   4 #include <inttypes.h>
   5
   6 typedef struct regs {
   7     uint32_t    gpr[32];
   8     uint32_t    srr0;
   9     uint32_t    srr1;
  10     uint32_t    ctr;
  11     uint32_t    lr;
  12     uint32_t    xer;
  13     uint32_t    ccr;
  14     uint32_t    dar;
  15     uint32_t    dsisr;
  16 } regs_t;
  17
  18 typedef struct fpuregs {
  19     double      fpr[32];
  20     uint32_t    fpscr;
  21 } fpuregs_t;
  22
  23 typedef struct context {
  24     regs_t      cpu;
  25     fpuregs_t   fpu;
  26 } context_t;
  27
  28 #define SIZEOF_ALL_REGISTERS (sizeof(context_t))
  29
  30 static inline uint32_t rdmsr() {
  31     uint32_t msr; asm volatile("mfmsr %0":"=r"(msr)); return msr;
  32 }
  33
  34 static inline void wrmsr(uint32_t msr) {
  35     asm volatile("mtmsr %0"::"r"(msr));
  36 }
  37
  38 /* Machine State Register */
  39 #define MSR_POW 0x00040000
  40 #define MSR_CE  0x00020000
  41 #define MSR_EE  0x00008000
  42 #define MSR_PR  0x00004000
  43 #define MSR_FP  0x00002000
  44 #define MSR_ME  0x00001000
  45 #define MSR_FE0 0x00000800
  46 #define MSR_DWE 0x00000400
  47 #define MSR_DE  0x00000200
  48 #define MSR_FE1 0x00000100
  49 #define MSR_IS  0x00000020
  50 #define MSR_DS  0x00000010
  51
  52 /* MMU TLB word 0 */
  53 #define TLB_V   0x00000200
  54
  55 /* MMU protection bits (TLB word 2) */
  56 #define TLB_SR  0x00000001      /* Supervisor State Read Enable */
  57 #define TLB_SW  0x00000002      /* Supervisor State Write Enable */
  58 #define TLB_SX  0x00000004      /* Supervisor State Execute Enable */
  59 #define TLB_UR  0x00000008      /* User State Read Enable */
  60 #define TLB_UW  0x00000010      /* User State Write Enable */
  61 #define TLB_UX  0x00000020      /* User State Execute Enable */
  62 #define TLB_E   0x00000080      /* Little Endian Enable */
  63 #define TLB_G   0x00000100      /* Guarded */
  64 #define TLB_M   0x00000200      /* Memory Coherence Required */
  65 #define TLB_I   0x00000400      /* Caching Inhibited */
  66 #define TLB_W   0x00000800      /* Write Through */
  67
  68 #define rdspr(reg) \
  69     ({ unsigned long val; asm volatile("mfspr %0,%1":"=r"(val):"i"(reg)); val; })
  70
  71 #define wrspr(reg, val) \
  72     do { asm volatile("mtspr %0,%1"::"i"(reg),"r"(val)); } while(0)
  73
  74 /* SPR registers */
  75 #define XER     0x001   /* Integer Exception Register */
  76 #define LR      0x008   /* Link Register */
  77 #define CTR     0x009   /* Count Register */
  78 #define DEC     0x016   /* Decrementer */
  79 #define SRR0    0x01A   /* Save/Restore Register 0 */
  80 #define SRR1    0x01B   /* Save/Restore Register 1 */
  81 #define PID     0x030   /* Process ID */
  82 #define DECAR   0x036   /* Decrementer Auto-Reload */
  83 #define CSRR0   0x03A   /* Critical Save/Restore Register 0 */
  84 #define CSRR1   0x03B   /* Critical Save/Restore Register 1 */
  85 #define DEAR    0x03D   /* Data Exception Address Register */
  86 #define ESR     0x03E   /* Exception Syndrome Register */
  87 #define IVPR    0x03F   /* Interrupt Vector Prefix Register */
  88 #define USPRG0  0x100   /* User Special Purpose Register General 0 */
  89 #define SPRG4U  0x104   /* Special Purpose Register General 4. Usermode - read only */
  90 #define SPRG5U  0x105   /* Special Purpose Register General 5. Usermode - read only */
  91 #define SPRG6U  0x106   /* Special Purpose Register General 6. Usermode - read only */
  92 #define SPRG7U  0x107   /* Special Purpose Register General 7. Usermode - read only */
  93 #define TBL     0x10C   /* Time Base Lower */
  94 #define TBU     0x10D   /* Time Base Upper */
  95 #define SPRG0   0x110   /* Special Purpose Register General 0 */
  96 #define SPRG1   0x111   /* Special Purpose Register General 1 */
  97 #define SPRG2   0x112   /* Special Purpose Register General 2 */
  98 #define SPRG3   0x113   /* Special Purpose Register General 3 */
  99 #define SPRG4   0x114   /* Special Purpose Register General 4 */
 100 #define SPRG5   0x115   /* Special Purpose Register General 5 */
 101 #define SPRG6   0x116   /* Special Purpose Register General 6 */
 102 #define SPRG7   0x117   /* Special Purpose Register General 7 */
 103 #define TBL     0x11C   /* Time Base Lower */
 104 #define TBU     0x11D   /* Time Base Upper */
 105 #define PIR     0x11E   /* Processor ID Register */
 106 #define PVR     0x11F   /* Processor Version Register */
 107 #define DBSR    0x130   /* Debug Status Register */
 108 #define DBCR0   0x134   /* Debug Control Register 0 */
 109 #define DBCR1   0x135   /* Debug Control Register 1 */
 110 #define DBCR2   0x136   /* Debug Control Register 2 */
 111 #define IAC1    0x138   /* Instruction Address Compare 1 */
 112 #define IAC2    0x139   /* Instruction Address Compare 2 */
 113 #define IAC3    0x13A   /* Instruction Address Compare 3 */
 114 #define IAC4    0x13B   /* Instruction Address Compare 4 */
 115 #define DAC1    0x13C   /* Data Address Compare 1 */
 116 #define DAC2    0x13D   /* Data Address Compare 2 */
 117 #define DVC1    0x13E   /* Data Value Compare 1 */
 118 #define DVC2    0x13F   /* Data Value Compare 2 */
 119 #define TSR     0x150   /* Timer Status Register */
 120 #define TCR     0x154   /* Timer Control Register */
 121 #define IVOR0   0x190   /* Interrupt Vector Offset Register 0 */
 122 #define IVOR1   0x191   /* Interrupt Vector Offset Register 1 */
 123 #define IVOR2   0x192   /* Interrupt Vector Offset Register 2 */
 124 #define IVOR3   0x193   /* Interrupt Vector Offset Register 3 */
 125 #define IVOR4   0x194   /* Interrupt Vector Offset Register 4 */
 126 #define IVOR5   0x195   /* Interrupt Vector Offset Register 5 */
 127 #define IVOR6   0x196   /* Interrupt Vector Offset Register 6 */
 128 #define IVOR7   0x197   /* Interrupt Vector Offset Register 7 */
 129 #define IVOR8   0x198   /* Interrupt Vector Offset Register 8 */
 130 #define IVOR9   0x199   /* Interrupt Vector Offset Register 9 */
 131 #define IVOR10  0x19A   /* Interrupt Vector Offset Register 10 */
 132 #define IVOR11  0x19B   /* Interrupt Vector Offset Register 11 */
 133 #define IVOR12  0x19C   /* Interrupt Vector Offset Register 12 */
 134 #define IVOR13  0x19D   /* Interrupt Vector Offset Register 13 */
 135 #define IVOR14  0x19E   /* Interrupt Vector Offset Register 14 */
 136 #define IVOR15  0x19F   /* Interrupt Vector Offset Register 15 */
 137 #define MCSRR0  0x23A   /* Machine Check Save Restore Register 0 */
 138 #define MCSRR1  0x23B   /* Machine Check Save Restore Register 1 */
 139 #define MCSR    0x23C   /* Machine Check Status Register */
 140 #define INV0    0x370   /* Instruction Cache Normal Victim 0 */
 141 #define INV1    0x371   /* Instruction Cache Normal Victim 1 */
 142 #define INV2    0x372   /* Instruction Cache Normal Victim 2 */
 143 #define INV3    0x373   /* Instruction Cache Normal Victim 3 */
 144 #define ITV0    0x374   /* Instruction Cache Transient Victim 0 */
 145 #define ITV1    0x375   /* Instruction Cache Transient Victim 1 */
 146 #define ITV2    0x376   /* Instruction Cache Transient Victim 2 */
 147 #define ITV3    0x377   /* Instruction Cache Transient Victim 3 */
 148 #define CCR1    0x378   /* Core Configuration Register 1 */
 149 #define DNV0    0x390   /* Data Cache Normal Victim 0 */
 150 #define DNV1    0x391   /* Data Cache Normal Victim 1 */
 151 #define DNV2    0x392   /* Data Cache Normal Victim 2 */
 152 #define DNV3    0x393   /* Data Cache Normal Victim 3 */
 153 #define DTV0    0x394   /* Data Cache Transient Victim 0 */
 154 #define DTV1    0x395   /* Data Cache Transient Victim 1 */
 155 #define DTV2    0x396   /* Data Cache Transient Victim 2 */
 156 #define DTV3    0x397   /* Data Cache Transient Victim 3 */
 157 #define DVLIM   0x398   /* Data Cache Victim Limit */
 158 #define IVLIM   0x399   /* Instruction Cache Victim Limit */
 159 #define RSTCFG  0x39B   /* Reset Configuration */
 160 #define DCDBTRL 0x39C   /* Data Cache Debug Tag Register Low */
 161 #define DCDBTRH 0x39D   /* Data Cache Debug Tag Register High */
 162 #define ICDBTRL 0x39E   /* Instruction Cache Debug Tag Register Low */
 163 #define ICDBTRH 0x39F   /* Instruction Cache Debug Tag Register High */
 164 #define MMUCR   0x3B2   /* Memory Management Unit Control Register */
 165 #define CCR0    0x3B3   /* Core Configuration Register 0 */
 166 #define ICDBDR  0x3D3   /* Instruction Cache Debug Data Register */
 167 #define DBDR    0x3F3   /* Debug Data Register */
 168
 169 /* TCR register */
 170 #define TCR_WP          0xc0000000
 171 #define TCR_WP21        0x00000000
 172 #define TCR_WP25        0x40000000
 173 #define TCR_WP29        0x80000000
 174 #define TCR_WP33        0xc0000000
 175 #define TCR_WRC         0x30000000
 176 #define TCR_WRC_NORESET 0x00000000
 177 #define TCR_WRC_CORE    0x10000000
 178 #define TCR_WRC_CHIP    0x20000000
 179 #define TCR_WRC_SYSTEM  0x30000000
 180 #define TCR_WIE         0x08000000
 181 #define TCR_DIE         0x04000000
 182 #define TCR_FP          0x03000000
 183 #define TCR_FP_13       0x00000000
 184 #define TCR_FP_17       0x01000000
 185 #define TCR_FP_21       0x02000000
 186 #define TCR_FP_25       0x03000000
 187 #define TCR_FP_FIE      0x00800000
 188 #define TCR_FP_ARE      0x00400000
 189
 190 /* TSR register */
 191 #define TSR_ENW         0x80000000
 192 #define TSR_WIS         0x40000000
 193 #define TSR_WRS         0x30000000
 194 #define TSR_WRS_NORESET 0x00000000
 195 #define TSR_WRS_CORE    0x10000000
 196 #define TSR_WRS_CHIP    0x20000000
 197 #define TSR_WRS_SYSTEM  0x30000000
 198 #define TSR_DIS         0x08000000
 199 #define TSR_FIS         0x04000000
 200
 201 /* DCR registers */
 202
 203 #define rddcr(reg) \
 204     ({ unsigned long val; asm volatile("mfdcr %0,%1":"=r"(val):"i"(reg)); val; })
 205
 206 #define wrdcr(reg, val) \
 207     do { asm volatile("mtdcr %0,%1"::"i"(reg),"r"(val)); } while(0)
 208
 209 /* System device control */
 210 #define SDR0_CFGADDR    0x000E  /* R/W System DCR Configuration Address Register */
 211 #define SDR0_CFGDATA    0x000F  /* R/W System DCR Configuration Data Register */
 212 #define SDR0_SDSTP0     0x0020  /*  R  Serial Device Strap Register 0 */
 213 #define SDR0_SDSTP1     0x0021  /*  R  Serial Device Strap Register 1 */
 214 #define SDR0_PINSTP     0x0040  /*  R  Pin Strapping Register */
 215 #define SDR0_SDCS0      0x0060  /* R/W Serial Device Controller Settings Register */
 216 #define SDR0_ECID0      0x0080  /* R/W Electronic Chip ID Register 0 */
 217 #define SDR0_ECID1      0x0081  /* R/W Electronic Chip ID Register 1 */
 218 #define SDR0_ECID2      0x0082  /* R/W Electronic Chip ID Register 2 */
 219 #define SDR0_ECID3      0x0083  /* R/W Electronic Chip ID Register 3 */
 220 #define SDR0_JTAG       0x00C0  /* R/W JTAG ID Register */
 221 #define SDR0_DDRDL0     0x00E0  /* R/W DDR Delay Line Register */
 222 #define SDR0_EBC0       0x0100  /* R/W EBC Configuration Register */
 223 #define SDR0_UART0      0x0120  /* R/W UART Configuration Register 0 */
 224 #define SDR0_UART1      0x0121  /* R/W UART Configuration Register 1 */
 225 #define SDR0_UART2      0x0122  /* R/W UART Configuration Register 2 */
 226 #define SDR0_UART3      0x0123  /* R/W UART Configuration Register 3 */
 227 #define SDR0_CP440      0x0180  /* R/W 440CPU Control Register */
 228 #define SDR0_SRST0      0x0200  /* R/W Individual Core Reset Control Register 0 */
 229 #define SDR0_SRST1      0x0201  /* R/W Individual Core Reset Control Register 1 */
 230 #define SDR0_SLPIPE0    0x0220  /* R/W PLB Slave Address Pipeline Disabling Register */
 231 #define SDR0_AMP0       0x0240  /* R/W Alternate PLB4 Master Priority Register */
 232 #define SDR0_AMP1       0x0241  /* R/W Alternate PLB3 Master Priority Register */
 233 #define SDR0_MIRQ0      0x0260  /* R/W Master Interrupt Request Register 0 (PLB3) */
 234 #define SDR0_MALTBL     0x0280  /* R/W MAL Transmit Burst Length Register */
 235 #define SDR0_MALRBL     0x02A0  /* R/W MAL Receive Burst Length Register */
 236 #define SDR0_MALTBS     0x02C0  /* R/W Reserved */
 237 #define SDR0_MALRBS     0x02E0  /* R/W Reserved */
 238 #define SDR0_PCI0       0x0300  /* R/W PCI Control Register */
 239 #define SDR0_USB0       0x0320  /*  R  Universal Serial Bus Register 0 */
 240 #define SDR0_CUST0      0x4000  /* R/W Register0 Reserved for Customer Use */
 241 #define SDR0_SDSTP2     0x4001  /*  R  Read Only Version of SDR0_CUST0 */
 242 #define SDR0_CUST1      0x4002  /* R/W Register1 Reserved for Customer Use */
 243 #define SDR0_SDSTP3     0x4003  /*  R  Read Only Version of SDR0_CUST1 */
 244 #define SDR0_PFC0       0x4100  /* R/W Pin Function Control Register 0 */
 245 #define SDR0_PFC1       0x4101  /* R/W Pin Function Control Register 1 */
 246 #define SDR0_MFR        0x4300  /* R/W Miscellaneous Function Register */
 247 #define SDR0_EMAC0RXST  0x4301  /* R/W EMAC0 RX Status Register */
 248 #define SDR0_EMAC0TXST  0x4302  /* R/W EMAC0 TX Status Register */
 249 #define SDR0_EMAC0REJCNT 0x4303 /*  R  EMAC0 RX Packet Reject Counter */
 250 #define SDR0_EMAC1RXST  0x4304  /* R/W EMAC1 RX Status Register */
 251 #define SDR0_EMAC1TXST  0x4305  /* R/W EMAC1 TX Status Register */
 252 #define SDR0_EMAC1REJCNT 0x4306 /*  R  EMAC1 RX Packet Reject Counter */
 253 #define SDR0_HSF        0x4400  /* R/W DDR Hardware Self Refresh Register */
 254
 255 /* Universal Interrupt Controller 0 */
 256 #define UIC0_SR         0x00C0 /* R/Clear UIC 0 Status Register */
 257 #define UIC0_SRS        0x00C1 /* W/Set   UIC 0 Status Register Set (reserved for debug only) */
 258 #define UIC0_ER         0x00C2 /*  R/W    UIC 0 Enable Register */
 259 #define UIC0_CR         0x00C3 /*  R/W    UIC 0 Critical Register */
 260 #define UIC0_PR         0x00C4 /*  R/W    UIC 0 Polarity Register */
 261 #define UIC0_TR         0x00C5 /*  R/W    UIC 0 Triggering Register */
 262 #define UIC0_MSR        0x00C6 /*   R     UIC 0 Masked Status Register */
 263 #define UIC0_VR         0x00C7 /*   R     UIC 0 Vector Register */
 264 #define UIC0_VCR        0x00C8 /*   W     UIC 0 Vector Configuration Register */
 265
 266 /* Universal Interrupt Controller 1 */
 267 #define UIC1_SR         0x00D0 /* R/Clear UIC 1 Status Register */
 268 #define UIC1_SRS        0x00D1 /* W/Set   UIC 1 Status Register Set (reserved for debug only) */
 269 #define UIC1_ER         0x00D2 /*  R/W    UIC 1 Enable Register */
 270 #define UIC1_CR         0x00D3 /*  R/W    UIC 1 Critical Register */
 271 #define UIC1_PR         0x00D4 /*  R/W    UIC 1 Polarity Register */
 272 #define UIC1_TR         0x00D5 /*  R/W    UIC 1 Triggering Register */
 273 #define UIC1_MSR        0x00D6 /*   R     UIC 1 Masked Status Register */
 274 #define UIC1_VR         0x00D7 /*   R     UIC 1 Vector Register */
 275 #define UIC1_VCR        0x00D8 /*   W     UIC 1 Vector Configuration Register */
 276
 277 /* External interrupt sources */
 278 #define INTR_U0         0       /* UART0 Interrupt Status*/
 279 #define INTR_U1         1       /* UART1 Interrupt Status*/
 280 #define INTR_IIC0       2       /* IIC0 Interrupt Status*/
 281 #define INTR_U2         3       /* UART2 Interrupt Status*/
 282 #define INTR_U3         4       /* UART3 Interrupt Status*/
 283 #define INTR_PCRW       5       /* PCI Command Register Write Interrupt Status */
 284 #define INTR_PPM        6       /* PCI Power Management Interrupt Status */
 285 #define INTR_IIC1       7       /* IIC1 Interrupt Status */
 286 #define INTR_SPI        8       /* SPI Interrupt Status */
 287 #define INTR_EPS        9       /* Ext PCI SERR Interrupt Status */
 288 #define INTR_MTE        10      /* MAL TX EOB Interrupt Status */
 289 #define INTR_MRE        11      /* MAL RX EOB Interrupt Status */
 290 #define INTR_D0         12      /* DMA2P30 Channel 0 Interrupt Status */
 291 #define INTR_D1         13      /* DMA2P30 Channel 1 Interrupt Status */
 292 #define INTR_D2         14      /* DMA2P30 Channel 2 Interrupt Status */
 293 #define INTR_D3         15      /* DMA2P30 Channel 3 Interrupt Status */
 294 #define INTR_CT5        16      /* GPT Compare Timer 5 Interrupt Status */
 295 #define INTR_CT6        17      /* GPT Compare Timer 6 Interrupt Status */
 296 #define INTR_CT0        18      /* GPT Compare Timer 0 Interrupt Status */
 297 #define INTR_CT1        19      /* GPT Compare Timer 1 Interrupt Status */
 298 #define INTR_CT2        20      /* GPT Compare Timer 2 Interrupt Status */
 299 #define INTR_CT3        21      /* GPT Compare Timer 3 Interrupt Status */
 300 #define INTR_CT4        22      /* GPT Compare Timer 4 Interrupt Status */
 301 #define INTR_EIR0       23      /* External IRQ 0 Interrupt Status */
 302 #define INTR_EIR1       24      /* External IRQ 1 Interrupt Status */
 303 #define INTR_EIR2       25      /* External IRQ 2 Interrupt Status */
 304 #define INTR_EIR3       26      /* External IRQ 3 Interrupt Status */
 305 #define INTR_EIR4       27      /* External IRQ 4 Interrupt Status */
 306 #define INTR_EIR5       28      /* External IRQ 5 Interrupt Status */
 307 #define INTR_EIR6       29      /* External IRQ 6 Interrupt Status */
 308
 309 #define INTR_MS         30      /* MAL SERR Interrupt Status */
 310 #define INTR_MTDE       31      /* MAL TXDE Interrupt Status */
 311 #define INTR_MRDE       32      /* MAL RXDE Interrupt Status */
 312 #define INTR_DEUE       33      /* DDRSDRAM ECC Uncorrectable Error Interrupt Status */
 313 #define INTR_DECE       34      /* DDRSDRAM ECC Correctable Error Interrupt Status */
 314 #define INTR_EBC        35      /* EBC Interrupt Status */
 315 #define INTR_NDFC       36      /* NDFC Interrupt Status */
 316 #define INTR_OPB        37      /* OPB to PLB Bridge Interrupt Status */
 317 #define INTR_USB1H1     38      /* USB1.1 Host 1 Interrupt Status */
 318 #define INTR_USB1H2     39      /* USB1.1 Host 2 interrupt Status */
 319 #define INTR_P2P0       40      /* PLB3 to PLB4 Bridge 0 Interrupt Status */
 320 #define INTR_P2P1       41      /* PLB3 to PLB4 Bridge 1 Interrupt Status */
 321 #define INTR_P2P2       42      /* PLB3 to PLB4 Bridge 2 Interrupt Status */
 322 #define INTR_P2P3       43      /* PLB3 to PLB4 Bridge 3 Interrupt Status */
 323 #define INTR_P2P4       44      /* PLB3 to PLB4 Bridge 4 Interrupt Status */
 324 #define INTR_P2P5       45      /* PLB3 to PLB4 Bridge 5 Interrupt Status */
 325 #define INTR_UDMA0      46      /* UDMA0 Interrupt Status */
 326 #define INTR_UDMA1      47      /* UDMA1 Interrupt Status */
 327 #define INTR_EIR7       48      /* External IRQ 7 Interrupt Status */
 328 #define INTR_EIR8       49      /* External IRQ 8 Interrupt Status */
 329 #define INTR_EIR9       50      /* External IRQ 9 Interrupt Status */
 330 #define INTR_UDMA2      51      /* UDMA2 Interrupt Status */
 331 #define INTR_UDMA3      52      /* UDMA3 Interrupt Status */
 332 #define INTR_USBD       53      /* USB1.1 USB2.0 Device Interrupt Status */
 333 #define INTR_SRE        54      /* Serial ROM Error Interrupt Status */
 334 #define INTR_GDP        55      /* GPT Decrement Pulse Interrupt Status */
 335 #define INTR_PPM        56      /* PLB Performance Monitor Interrupt Status */
 336 #define INTR_EPP        57      /* EXT_PCI_PERR (parity) Interrupt Status */
 337 #define INTR_ETH0       58      /* Ethernet 0 Interrupt Status */
 338 #define INTR_EWU0       59      /* Ethernet 0 Wake-up Interrupt Status */
 339 #define INTR_ETH1       60      /* Ethernet 1 Interrupt Status */
 340 #define INTR_EWU1       61      /* Ethernet 1 Wake-up Interrupt Status */
 341
 342 /* UART registers */
 343
 344 /* UART0 */
 345 #define UART0_RBR       0xEF600300
 346 #define UART0_THR       0xEF600300
 347 #define UART0_IER       0xEF600301
 348 #define UART0_IIR       0xEF600302
 349 #define UART0_FCR       0xEF600302
 350 #define UART0_LCR       0xEF600303
 351 #define UART0_MCR       0xEF600304
 352 #define UART0_LSR       0xEF600305
 353 #define UART0_MSR       0xEF600306
 354 #define UART0_SCR       0xEF600307
 355 #define UART0_DLL       0xEF600300
 356 #define UART0_DLM       0xEF600301
 357
 358 /* UART1 */
 359 #define UART1_RBR       0xEF600400
 360 #define UART1_THR       0xEF600400
 361 #define UART1_IER       0xEF600401
 362 #define UART1_IIR       0xEF600402
 363 #define UART1_FCR       0xEF600402
 364 #define UART1_LCR       0xEF600403
 365 #define UART1_MCR       0xEF600404
 366 #define UART1_LSR       0xEF600405
 367 #define UART1_MSR       0xEF600406
 368 #define UART1_SCR       0xEF600407
 369 #define UART1_DLL       0xEF600400
 370 #define UART1_DLM       0xEF600401
 371
 372 /* UART2 */
 373 #define UART2_RBR       0xEF600500
 374 #define UART2_THR       0xEF600500
 375 #define UART2_IER       0xEF600501
 376 #define UART2_IIR       0xEF600502
 377 #define UART2_FCR       0xEF600502
 378 #define UART2_LCR       0xEF600503
 379 #define UART2_MCR       0xEF600504
 380 #define UART2_LSR       0xEF600505
 381 #define UART2_MSR       0xEF600506
 382 #define UART2_SCR       0xEF600507
 383 #define UART2_DLL       0xEF600500
 384 #define UART2_DLM       0xEF600501
 385
 386 /* UART3 */
 387 #define UART3_RBR       0xEF600600
 388 #define UART3_THR       0xEF600600
 389 #define UART3_IER       0xEF600601
 390 #define UART3_IIR       0xEF600602
 391 #define UART3_FCR       0xEF600602
 392 #define UART3_LCR       0xEF600603
 393 #define UART3_MCR       0xEF600604
 394 #define UART3_LSR       0xEF600605
 395 #define UART3_MSR       0xEF600606
 396 #define UART3_SCR       0xEF600607
 397 #define UART3_DLL       0xEF600600
 398 #define UART3_DLM       0xEF600601
 399
 400 #define UART_IER_EDSSI  0x08
 401 #define UART_IER_ELSI   0x04
 402 #define UART_IER_ETBEI  0x02
 403 #define UART_IER_ERBFI  0x01
 404
 405 #define UART_IIR_FE             0xc0
 406 #define UART_IIR_FE_ENABLED     0xc0
 407 #define UART_IIR_FE_DISABLED    0x00
 408 #define UART_IIR_INTID          0x0e
 409 #define UART_IIR_INTID_4        0x00
 410 #define UART_IIR_INTID_3        0x02
 411 #define UART_IIR_INTID_2        0x04
 412 #define UART_IIR_INITD_1        0x06
 413 #define UART_IIR_INTID_0        0x0c
 414 #define UART_IIR_INTP           0x01
 415
 416 #define UART_FCR_RFTL       0xc0
 417 #define UART_FCR_RFTL_01    0x00
 418 #define UART_FCR_RFTL_16    0x40
 419 #define UART_FCR_RFTL_32    0x80
 420 #define UART_FCR_RFTL_56    0xc0
 421 #define UART_FCR_DMS        0x08
 422 #define UART_FCR_TFR        0x04
 423 #define UART_FCR_RFR        0x02
 424 #define UART_FCR_FE         0x01
 425
 426 #define UART_LCR_DLAB       0x80
 427 #define UART_LCR_SB         0x40
 428 #define UART_LCR_SP         0x20
 429 #define UART_LCR_EPS        0x10
 430 #define UART_LCR_PEN        0x08
 431 #define UART_LCR_SBS        0x04
 432 #define UART_LCR_WLS        0x03
 433 #define UART_LCR_WLS_5      0x00
 434 #define UART_LCR_WLS_6      0x01
 435 #define UART_LCR_WLS_7      0x02
 436 #define UART_LCR_WLS_8      0x03
 437
 438 #define UART_MCR_AFC        0x20
 439 #define UART_MCR_LOOP       0x10
 440 #define UART_MCR_OUT2       0x08
 441 #define UART_MCR_OUT1       0x04
 442 #define UART_MCR_RTS        0x02
 443 #define UART_MCR_DTR        0x01
 444
 445 #define UART_LSR_RFE    0x80
 446 #define UART_LSR_TEMT   0x40
 447 #define UART_LSR_THRE   0x20
 448 #define UART_LSR_BI     0x10
 449 #define UART_LSR_FE     0x08
 450 #define UART_LSR_PE     0x04
 451 #define UART_LSR_OE     0x02
 452 #define UART_LSR_DR     0x01
 453
 454 #define UART_MSR_DCD    0x80
 455 #define UART_LSR_RI     0x40
 456 #define UART_LSR_DSR    0x20
 457 #define UART_LSR_CTS    0x10
 458 #define UART_LSR_DDCD   0x08
 459 #define UART_LSR_TERI   0x04
 460 #define UART_LSR_DDSR   0x02
 461 #define UART_LSR_DCTS   0x01
 462
 463
 464 #define PCIC0_CFGADDR   0xeec00000
 465 #define PCIC0_CFGDATA   0xeec00004
 466
 467 #endif /*ASM_AMCC440_H*/