arch/x86_64-pc/include/asm/cpu.h

   1 #ifndef ASM_CPU_H
   2 #define ASM_CPU_H
   3
   4 #include <inttypes.h>
   5
   6 #ifdef __cplusplus
   7 extern "C" {
   8 #endif
   9
  10 typedef struct regs {
  11     uint64_t    ds;
  12     uint64_t    r15;
  13     uint64_t    r14;
  14     uint64_t    r13;
  15     uint64_t    r12;
  16     uint64_t    r11;
  17     uint64_t    r10;
  18     uint64_t    r9;
  19     uint64_t    r8;
  20     uint64_t    rcx;
  21     uint64_t    rdx;
  22     uint64_t    rsi;
  23     uint64_t    rdi;
  24     uint64_t    rbx;
  25     uint64_t    rbp;
  26     uint64_t    rax;
  27     uint64_t    irq_number;
  28     uint64_t    error_code;
  29     uint64_t    return_rip;
  30     uint64_t    return_cs;
  31     uint64_t    return_rflags;
  32     uint64_t    return_rsp;
  33     uint64_t    return_ss;
  34 } regs_t;
  35
  36
  37 /* Segment registers */
  38 #define SEG_SUPER_CS    0x08
  39 #define SEG_SUPER_DS    0x10
  40 #define SEG_USER_CS32   0x18
  41 #define SEG_USER_CS64   0x28
  42 #define SEG_USER_DS     0x20
  43 #define SEG_TSS         0x30
  44
  45 /* CR0 bits */
  46 #define _CR0_PE_B  0    /* RW: Protected mode enable */
  47 #define _CR0_MP_B  1    /* RW: Monitor FPU? If 1 then #NM exception may be generated */
  48 #define _CR0_EM_B  2    /* RW: Eulate FPU */
  49 #define _CR0_TS_B  3    /* RW: Task switched */
  50 #define _CR0_ET_B  4    /* RO: Exception type */
  51 #define _CR0_NE_B  5    /* RW: Numeric error */
  52 #define _CR0_WP_B 16    /* RW: Write protect for RO pages in supervisor mode */
  53 #define _CR0_AM_B 18    /* RW: Require data alignment */
  54 #define _CR0_NW_B 29    /* RW: IGNORED: Not writethrough */
  55 #define _CR0_CD_B 30    /* RW: Cache disable */
  56 #define _CR0_PG_B 31    /* RW: Paging enable */
  57
  58 #define _CR0_PE (1 << _CR0_PE_B)
  59 #define _CR0_MP (1 << _CR0_MP_B)
  60 #define _CR0_EM (1 << _CR0_EM_B)
  61 #define _CR0_TS (1 << _CR0_TS_B)
  62 #define _CR0_ET (1 << _CR0_ET_B)
  63 #define _CR0_NE (1 << _CR0_NE_B)
  64 #define _CR0_WP (1 << _CR0_WP_B)
  65 #define _CR0_AM (1 << _CR0_AM_B)
  66 #define _CR0_NW (1 << _CR0_NW_B)
  67 #define _CR0_CD (1 << _CR0_CD_B)
  68 #define _CR0_PG (1 << _CR0_PG_B)
  69
  70 /* CR3 bits */
  71 #define _CR3_PWT_B  3   /* RW: Page writethrough */
  72 #define _CR3_PCD_B  4   /* RW: Cache disable */
  73
  74 #define _CR3_PWT (1 << _CR3_PWT_B)
  75 #define _CR3_PCD (1 << _CR3_PCD_B)
  76
  77 /* CR4 bits */
  78 #define _CR4_VME_B       0  /* RW: Virtual-8086 enable */
  79 #define _CR4_PVI_B       1  /* RW: Protected mode virtual interrupts */
  80 #define _CR4_TSD_B       2  /* RW: Time stamp disable for usermode */
  81 #define _CR4_DE_B        3  /* RW: Debug extensions */
  82 #define _CR4_PSE_B       4  /* RW: Page size extensions */
  83 #define _CR4_PAE_B       5  /* RW: Physical-address extensions */
  84 #define _CR4_MCE_B       6  /* RW: Machine check enable */
  85 #define _CR4_PGE_B       7  /* RW: Page-Global enable */
  86 #define _CR4_PCE_B       8  /* RW: Performance monitoring counter enable */
  87 #define _CR4_OSFXSR_B    9  /* RW: Operating system fxsave/fsrstor support */
  88 #define _CR4_OSXMMEXCPT_B 10 /*RW: Operating system unmasked exception support */
  89
  90 #define _CR4_VME (1 << _CR4_VME_B)
  91 #define _CR4_PVI (1 << _CR4_PVI_B)
  92 #define _CR4_TSD (1 << _CR4_TSD_B)
  93 #define _CR4_DE  (1 << _CR4_DE_B)
  94 #define _CR4_PSE (1 << _CR4_PSE_B)
  95 #define _CR4_PAE (1 << _CR4_PAE_B)
  96 #define _CR4_MCE (1 << _CR4_MCE_B)
  97 #define _CR4_PGE (1 << _CR4_PGE_B)
  98 #define _CR4_PCE (1 << _CR4_PCE_B)
  99 #define _CR4_OSFXSR (1 << _CR4_OSFXSR_B)
 100 #define _CR4_OSXMMEXCPT (1 << _CR4_OSXMMEXCPT_B)
 101
 102 /* EFER */
 103 #define EFER        0xc0000080  /* EFER number for rsmsr/wrmsr */
 104 #define _EFER_SCE_B      0      /* RW: System call extensions */
 105 #define _EFER_LME_B      8      /* RW: Long mode enable */
 106 #define _EFER_LMA_B     10      /* RW: Long mode activated */
 107 #define _EFER_NXE_B     11      /* RW: No-execute bit enable */
 108 #define _EFER_FFXSR_B   14      /* RW: Fast fxsave/fxrstor */
 109
 110 #define _EFER_SCE   (1 << _EFER_SCE_B)
 111 #define _EFER_LME   (1 << _EFER_LME_B)
 112 #define _EFER_LMA   (1 << _EFER_LMA_B)
 113 #define _EFER_NXE   (1 << _EFER_NXE_B)
 114 #define _EFER_FFXSR (1 << _EFER_FFXSR_B)
 115
 116 struct int_gate_64bit {
 117     uint16_t    offset_low;
 118     uint16_t    selector;
 119     unsigned    ist:3, __pad0:5, type:5, dpl:2, p:1;
 120     uint16_t    offset_mid;
 121     uint32_t    offset_high;
 122     uint32_t    __pad1;
 123 } __attribute__((packed));
 124
 125 struct segment_desc {
 126     uint16_t    limit_low;
 127     uint16_t    base_low;
 128     unsigned    base_mid:8, type:5, dpl:2, p:1;
 129     unsigned    limit_high:4, avl:1, l:1, d:1, g:1, base_high:8;
 130 } __attribute__((packed));
 131
 132 struct segment_ext {
 133     uint32_t    base_ext;
 134     uint32_t    __pad0;
 135 } __attribute__((packed));
 136
 137 struct tss_64bit {
 138     uint32_t    __pad0;
 139     uint64_t    rsp0;
 140     uint64_t    rsp1;
 141     uint64_t    rsp2;
 142     uint64_t    __pad1;
 143     uint64_t    ist1;
 144     uint64_t    ist2;
 145     uint64_t    ist3;
 146     uint64_t    ist4;
 147     uint64_t    ist5;
 148     uint64_t    ist6;
 149     uint64_t    ist7;
 150     uint64_t    __pad2;
 151     uint16_t    __pad3;
 152     uint16_t    iopb;
 153     uint32_t    bmp[];
 154 } __attribute__((packed));
 155
 156 #define MMU_PAGEB_P     0
 157 #define MMU_PAGEB_RW    1
 158 #define MMU_PAGEB_US    2
 159 #define MMU_PAGEB_PWT   3
 160 #define MMU_PAGEB_PCD   4
 161 #define MMU_PAGEB_A     5
 162
 163 struct PML4E {
 164     unsigned p:1,rw:1,us:1,pwt:1,pcd:1,a:1,__pad0:1,mbz:2,avl:3,base_low:20;
 165     unsigned base_high:20,avail:11,nx:1;
 166 } __attribute__((packed));
 167
 168 struct PDPE {
 169     unsigned p:1,rw:1,us:1,pwt:1,pcd:1,a:1,__pad0:1,mbz:2,avl:3,base_low:20;
 170     unsigned base_high:20,avail:11,nx:1;
 171 } __attribute__((packed));
 172
 173 struct PDE4K {
 174     unsigned p:1,rw:1,us:1,pwt:1,pcd:1,a:1,__pad0:1,ps:1,_pad1:1,avl:3,base_low:20;
 175     unsigned base_high:20,avail:11,nx:1;
 176 } __attribute__((packed));
 177
 178 struct PDE2M {
 179     unsigned p:1,rw:1,us:1,pwt:1,pcd:1,a:1,d:1,ps:1,g:1,avl:3,pat:1,base_low:19;
 180     unsigned base_high:20,avail:11,nx:1;
 181 } __attribute__((packed));
 182
 183 struct PTE {
 184     unsigned p:1,rw:1,us:1,pwt:1,pcd:1,a:1,d:1,pat:1,g:1,avl:3,base_low:20;
 185     unsigned base_high:20,avail:11,nx:1;
 186 } __attribute__((packed));
 187
 188 #define _ljmp(seg, addr) \
 189     do { asm volatile("ljmp $" #seg ", $" #addr); }while(0)
 190 #define ljmp(s, a) _ljmp(s, a)
 191
 192 #define _ljmp_arg(seg, addr, arg) \
 193     do { asm volatile("ljmp $" #seg ", $" #addr ::"D"(arg)); }while(0)
 194 #define ljmp_arg(s, a, p) _ljmp_arg(s, a, p)
 195
 196 #define rdcr(reg) \
 197     ({ long val; asm volatile("mov %%" #reg ",%0":"=r"(val)); val; })
 198
 199 #define wrcr(reg, val) \
 200     do { asm volatile("mov %0,%%" #reg::"r"(val)); } while(0)
 201
 202 extern inline void __attribute__((always_inline)) rdmsr(uint32_t msr_no, uint32_t *ret_lo, uint32_t *ret_hi)
 203 {
 204     uint32_t ret1,ret2;
 205     asm volatile("rdmsr":"=a"(ret1),"=d"(ret2):"c"(msr_no));
 206     *ret_lo=ret1;
 207     *ret_hi=ret2;
 208 }
 209
 210 extern inline uint64_t __attribute__((always_inline)) rdmsrq(uint32_t msr_no)
 211 {
 212     uint32_t ret1,ret2;
 213     asm volatile("rdmsr":"=a"(ret1),"=d"(ret2):"c"(msr_no));
 214     return ((uint64_t)ret1 | ((uint64_t)ret2 << 32));
 215 }
 216
 217 extern inline void __attribute__((always_inline)) wrmsr(uint32_t msr_no, uint32_t val_lo, uint32_t val_hi)
 218 {
 219     asm volatile("wrmsr"::"a"(val_lo),"d"(val_hi),"c"(msr_no));
 220 }
 221
 222 extern inline void __attribute__((always_inline)) wrmsrq(uint32_t msr_no, uint64_t val)
 223 {
 224     asm volatile("wrmsr"::"a"((uint32_t)(val & 0xffffffff)),"d"((uint32_t)(val >> 32)),"c"(msr_no));
 225 }
 226
 227
 228 #ifdef __cplusplus
 229 }
 230 #endif
 231
 232 #endif /*ASM_CPU_H*/