arch/common/hidd.vmwaresvga/vmwaresvgahardware.c

   1 /*
   2     Copyright © 1995-2008, The AROS Development Team. All rights reserved.
   3     $Id$
   4
   5     Desc: vmware svga hardware functions
   6     Lang: English
   7 */
   8
   9 #define DEBUG 1 /* no SysBase */
  10 #include <aros/debug.h>
  11
  12 #include <asm/io.h>
  13
  14 #include "vmwaresvgahardware.h"
  15 #include "svga_reg.h"
  16 #include "vmwaresvgaclass.h"
  17
  18 ULONG vmwareReadReg(struct HWData *data, ULONG reg)
  19 {
  20     outl(reg, data->indexReg);
  21     return inl(data->valueReg);
  22 }
  23
  24 void vmwareWriteReg(struct HWData *data, ULONG reg, ULONG val)
  25 {
  26     outl(reg, data->indexReg);
  27     outl(val, data->valueReg);
  28 }
  29
  30 #undef SysBase
  31 extern struct ExecBase *SysBase;
  32
  33 ULONG getVMWareSVGAID(struct HWData *data)
  34 {
  35     ULONG id;
  36
  37     vmwareWriteReg(data, SVGA_REG_ID, SVGA_ID_2);
  38     id = vmwareReadReg(data, SVGA_REG_ID);
  39     if (id == SVGA_ID_2)
  40         return id;
  41     vmwareWriteReg(data, SVGA_REG_ID, SVGA_ID_1);
  42     id = vmwareReadReg(data, SVGA_REG_ID);
  43     if (id == SVGA_ID_1)
  44         return id;
  45     if (id == SVGA_ID_0)
  46         return id;
  47     return SVGA_ID_INVALID;
  48 }
  49
  50 VOID initVMWareSVGAFIFO(struct HWData *data)
  51 {
  52     ULONG *fifo;
  53     ULONG fifomin;
  54
  55     vmwareWriteReg(data, SVGA_REG_CONFIG_DONE, 0);              //Stop vmware from reading the fifo
  56
  57     fifo = data->mmiobase = vmwareReadReg(data, SVGA_REG_MEM_START);
  58     data->mmiosize = vmwareReadReg(data, SVGA_REG_MEM_SIZE) & ~3;
  59
  60     if (data->capabilities & SVGA_CAP_EXTENDED_FIFO)
  61         fifomin = vmwareReadReg(data, SVGA_REG_MEM_REGS);
  62     else
  63         fifomin =4;
  64
  65     fifo[SVGA_FIFO_MIN] = fifomin * sizeof(ULONG);
  66     fifo[SVGA_FIFO_MAX] = data->mmiosize;
  67     fifo[SVGA_FIFO_NEXT_CMD] = fifomin * sizeof(ULONG);
  68     fifo[SVGA_FIFO_STOP] = fifomin * sizeof(ULONG);
  69
  70     vmwareWriteReg(data, SVGA_REG_CONFIG_DONE, 1);
  71 }
  72
  73 VOID syncVMWareSVGAFIFO(struct HWData *data)
  74 {
  75     vmwareWriteReg(data, SVGA_REG_SYNC, 1);
  76     while (vmwareReadReg(data, SVGA_REG_BUSY) != 0);
  77 #warning "maybe wait (delay) some time"
  78 }
  79
  80 VOID writeVMWareSVGAFIFO(struct HWData *data, ULONG val)
  81 {
  82     ULONG *fifo;
  83
  84     fifo = data->mmiobase;
  85     if (
  86             (fifo[SVGA_FIFO_NEXT_CMD]+4 == fifo[SVGA_FIFO_STOP]) ||
  87             (
  88                 (fifo[SVGA_FIFO_NEXT_CMD] == (fifo[SVGA_FIFO_MAX]-4)) &&
  89                 (fifo[SVGA_FIFO_STOP] == fifo[SVGA_FIFO_MIN])
  90             )
  91         )
  92         syncVMWareSVGAFIFO(data);
  93
  94     fifo[fifo[SVGA_FIFO_NEXT_CMD] / 4] = val;
  95     fifo[SVGA_FIFO_NEXT_CMD] += 4;
  96
  97     if (fifo[SVGA_FIFO_NEXT_CMD] == fifo[SVGA_FIFO_MAX])
  98         fifo[SVGA_FIFO_NEXT_CMD] = fifo[SVGA_FIFO_MIN];
  99 }
 100
 101 BOOL initVMWareSVGAHW(struct HWData *data, OOP_Object *device)
 102 {
 103     ULONG *ba;
 104     ULONG id;
 105
 106     id = getVMWareSVGAID(data);
 107     if ((id == SVGA_ID_0) || (id == SVGA_ID_INVALID))
 108     {
 109         return FALSE;
 110     }
 111
 112     initVMWareSVGAFIFO(data);
 113
 114     data->capabilities = vmwareReadReg(data, SVGA_REG_CAPABILITIES);
 115     data->depth = vmwareReadReg(data, SVGA_REG_DEPTH);
 116     data->maxwidth = vmwareReadReg(data, SVGA_REG_MAX_WIDTH);
 117     data->maxheight = vmwareReadReg(data, SVGA_REG_MAX_HEIGHT);
 118     data->redmask = vmwareReadReg(data, SVGA_REG_RED_MASK);
 119     data->greenmask = vmwareReadReg(data, SVGA_REG_GREEN_MASK);
 120     data->bluemask = vmwareReadReg(data, SVGA_REG_BLUE_MASK);
 121     data->bytesperpixel = 1;
 122
 123     if (data->depth>16)
 124         data->bytesperpixel = 4;
 125     else if (data->depth>8)
 126         data->bytesperpixel = 2;
 127
 128     if (data->capabilities & SVGA_CAP_8BIT_EMULATION)
 129     {
 130         data->bitsperpixel = vmwareReadReg(data, SVGA_REG_HOST_BITS_PER_PIXEL);
 131         vmwareWriteReg(data,SVGA_REG_BITS_PER_PIXEL, data->bitsperpixel);
 132     }
 133     else
 134         data->bitsperpixel = vmwareReadReg(data, SVGA_REG_BITS_PER_PIXEL);
 135
 136     if (data->capabilities & SVGA_CAP_MULTIMON)
 137     {
 138         data->displaycount = vmwareReadReg(data, SVGA_REG_NUM_DISPLAYS);
 139     }
 140     else
 141     {
 142         data->displaycount = 1;
 143     }
 144
 145     data->vramsize = vmwareReadReg(data, SVGA_REG_VRAM_SIZE);
 146     data->vrambase = vmwareReadReg(data, SVGA_REG_FB_START);
 147     data->pseudocolor = vmwareReadReg(data, SVGA_REG_PSEUDOCOLOR);
 148
 149     D(bug("[VMWareSVGA] Init: caps : 0x%08x\n",data->capabilities));
 150     D(bug("[VMWareSVGA] Init: no.displays: %d\n",data->displaycount));
 151     D(bug("[VMWareSVGA] Init: depth: %d\n",data->depth));
 152     D(bug("[VMWareSVGA] Init: bpp  : %d\n",data->bitsperpixel));
 153     D(bug("[VMWareSVGA] Init: maxw: %d\n",data->maxwidth));
 154     D(bug("[VMWareSVGA] Init: maxh: %d\n",data->maxheight));
 155
 156     return TRUE;
 157 }
 158
 159 VOID setModeVMWareSVGA(struct HWData *data, ULONG width, ULONG height)
 160 {
 161     D(bug("[VMWareSVGA] SetMode: %dx%d\n",width,height));
 162     vmwareWriteReg(data, SVGA_REG_ENABLE, 0);
 163     vmwareWriteReg(data, SVGA_REG_WIDTH, width);
 164     vmwareWriteReg(data, SVGA_REG_HEIGHT, height);
 165
 166     if (data->capabilities & SVGA_CAP_8BIT_EMULATION)
 167         vmwareWriteReg(data, SVGA_REG_BITS_PER_PIXEL,data->bitsperpixel);
 168
 169     vmwareWriteReg(data, SVGA_REG_ENABLE, 1);
 170
 171     data->fboffset = vmwareReadReg(data, SVGA_REG_FB_OFFSET);
 172     data->bytesperline = vmwareReadReg(data, SVGA_REG_BYTES_PER_LINE);
 173     data->depth = vmwareReadReg(data, SVGA_REG_DEPTH);
 174     data->redmask = vmwareReadReg(data, SVGA_REG_RED_MASK);
 175     data->greenmask = vmwareReadReg(data, SVGA_REG_GREEN_MASK);
 176     data->bluemask = vmwareReadReg(data, SVGA_REG_BLUE_MASK);
 177     data->pseudocolor = vmwareReadReg(data, SVGA_REG_PSEUDOCOLOR);
 178 }
 179
 180 VOID refreshAreaVMWareSVGA(struct HWData *data, struct Box *box)
 181 {
 182     writeVMWareSVGAFIFO(data, SVGA_CMD_UPDATE);
 183     writeVMWareSVGAFIFO(data, box->x1);
 184     writeVMWareSVGAFIFO(data, box->y1);
 185     writeVMWareSVGAFIFO(data, box->x2-box->x1+1);
 186     writeVMWareSVGAFIFO(data, box->y2-box->y1+1);
 187 }
 188
 189 VOID rectFillVMWareSVGA(struct HWData *data, ULONG color, LONG x, LONG y, LONG width, LONG height)
 190 {
 191     writeVMWareSVGAFIFO(data, SVGA_CMD_RECT_FILL);
 192     writeVMWareSVGAFIFO(data, color);
 193     writeVMWareSVGAFIFO(data, x);
 194     writeVMWareSVGAFIFO(data, y);
 195     writeVMWareSVGAFIFO(data, width);
 196     writeVMWareSVGAFIFO(data, height);
 197     syncVMWareSVGAFIFO(data);
 198 }
 199
 200 VOID ropFillVMWareSVGA(struct HWData *data, ULONG color, LONG x, LONG y, LONG width, LONG height, ULONG mode)
 201 {
 202     writeVMWareSVGAFIFO(data, SVGA_CMD_RECT_ROP_FILL);
 203     writeVMWareSVGAFIFO(data, color);
 204     writeVMWareSVGAFIFO(data, x);
 205     writeVMWareSVGAFIFO(data, y);
 206     writeVMWareSVGAFIFO(data, width);
 207     writeVMWareSVGAFIFO(data, height);
 208     writeVMWareSVGAFIFO(data, mode);
 209     syncVMWareSVGAFIFO(data);
 210 }
 211
 212 VOID ropCopyVMWareSVGA(struct HWData *data, LONG sx, LONG sy, LONG dx, LONG dy, ULONG width, ULONG height, ULONG mode)
 213 {
 214     writeVMWareSVGAFIFO(data, SVGA_CMD_RECT_ROP_COPY);
 215     writeVMWareSVGAFIFO(data, sx);
 216     writeVMWareSVGAFIFO(data, sy);
 217     writeVMWareSVGAFIFO(data, dx);
 218     writeVMWareSVGAFIFO(data, dy);
 219     writeVMWareSVGAFIFO(data, width);
 220     writeVMWareSVGAFIFO(data, height);
 221     writeVMWareSVGAFIFO(data, mode);
 222     syncVMWareSVGAFIFO(data);
 223 }
 224
 225 VOID defineCursorVMWareSVGA(struct HWData *data, struct MouseData *mouse)
 226 {
 227     int i;
 228     ULONG *cshape = mouse->shape;
 229     struct Box box;
 230     ULONG andmask[SVGA_PIXMAP_SIZE(mouse->width, mouse->height, data->bitsperpixel)];
 231     ULONG *a;
 232     ULONG *b;
 233
 234 #warning "convert mouse shape to current depth"
 235     writeVMWareSVGAFIFO(data, SVGA_CMD_DEFINE_CURSOR);
 236     writeVMWareSVGAFIFO(data, 1);
 237     writeVMWareSVGAFIFO(data, 0); /* hot x value */
 238     writeVMWareSVGAFIFO(data, 0); /* hot y value */
 239     writeVMWareSVGAFIFO(data, mouse->width); /* width */
 240     writeVMWareSVGAFIFO(data, mouse->height); /* height */
 241     writeVMWareSVGAFIFO(data, data->bitsperpixel); /* bits per pixel */
 242     writeVMWareSVGAFIFO(data, data->bitsperpixel); /* bits per pixel */
 243     b = cshape;
 244     a = andmask;
 245     for (i = 0; i<(SVGA_PIXMAP_SIZE(mouse->width, mouse->height, data->bitsperpixel)*2);i++)
 246     {
 247         *((UWORD *)a) = *((UWORD *)b) ? 0 : ~0;
 248
 249         a = ((UWORD *)a) + 1;
 250         b = ((UWORD *)b) + 1;
 251     }
 252     a = andmask;
 253     for (i = 0; i<SVGA_PIXMAP_SIZE(mouse->width, mouse->height, data->bitsperpixel);i++)
 254         writeVMWareSVGAFIFO(data, *a++);
 255     for (i = 0; i<SVGA_PIXMAP_SIZE(mouse->width, mouse->height, data->bitsperpixel);i++)
 256         writeVMWareSVGAFIFO(data, *cshape++);
 257     syncVMWareSVGAFIFO(data);
 258 }
 259
 260 VOID displayCursorVMWareSVGA(struct HWData *data, LONG mode)
 261 {
 262 #if 0
 263     writeVMWareSVGAFIFO(data, SVGA_CMD_DISPLAY_CURSOR);
 264     writeVMWareSVGAFIFO(data, 1);
 265     writeVMWareSVGAFIFO(data, mode);
 266     syncVMWareSVGAFIFO(data);
 267 #else
 268     vmwareWriteReg(data, SVGA_REG_CURSOR_ID, 1);
 269     vmwareWriteReg(data, SVGA_REG_CURSOR_ON, mode);
 270 #endif
 271 }
 272
 273 VOID moveCursorVMWareSVGA(struct HWData *data, LONG x, LONG y)
 274 {
 275 #if 0
 276     writeVMWareSVGAFIFO(data, SVGA_CMD_MOVE_CURSOR);
 277     writeVMWareSVGAFIFO(data, x);
 278     writeVMWareSVGAFIFO(data, y);
 279     syncVMWareSVGAFIFO(data);
 280 #else
 281     vmwareWriteReg(data, SVGA_REG_CURSOR_ID, 1);
 282     vmwareWriteReg(data, SVGA_REG_CURSOR_X, x);
 283     vmwareWriteReg(data, SVGA_REG_CURSOR_Y, y);
 284     vmwareWriteReg(data, SVGA_REG_CURSOR_ON, 1);
 285 #endif
 286 }