arch/i386-pc/exec/cachecleare.c

   1 /*
   2     Copyright © 1995-2008, The AROS Development Team. All rights reserved.
   3     $Id$
   4
   5     Desc: CacheClearE() - Clear the caches with extended control.
   6     Lang: english
   7 */
   8
   9 #include <exec/types.h>
  10 #include <exec/execbase.h>
  11 #include <aros/libcall.h>
  12
  13 /*****************************************************************************
  14
  15     NAME */
  16 #include <proto/exec.h>
  17
  18         AROS_LH3(void, CacheClearE,
  19
  20 /*  SYNOPSIS */
  21         AROS_LHA(APTR, address, A0),
  22         AROS_LHA(ULONG, length, D0),
  23         AROS_LHA(ULONG, caches, D1),
  24
  25 /*  LOCATION */
  26         struct ExecBase *, SysBase, 107, Exec)
  27
  28 /*  FUNCTION
  29         Flush the contents of the CPU instruction or data caches. If some
  30         of the cache contains dirty data, push it to memory first.
  31
  32         For most systems DMA will not effect processor caches. If *any*
  33         external (non-processor) event changes system memory, you MUST
  34         clear the cache. For example:
  35
  36             DMA
  37             Code relocation to run at a different address
  38             Building jump tables
  39             Loading code from disk
  40
  41     INPUTS
  42         address -   Address to start the operation. This address may be
  43                     rounded DOWN due to hardware granularity.
  44         length  -   Length of the memory to flush. This will be rounded
  45                     up, of $FFFFFFFF to indicate that all addresses
  46                     should be cleared.
  47         caches  -   Bit flags to indicate which caches should be cleared
  48
  49                         CACRF_ClearI    -   Clear the instruction cache
  50                         CACRF_ClearD    -   Clear the data cache
  51
  52                     All other bits are reserved.
  53
  54     RESULT
  55         The caches will be flushed.
  56
  57     NOTES
  58         It is possible that on some systems the entire cache will be
  59         even if this was not the specific request.
  60
  61     EXAMPLE
  62
  63     BUGS
  64
  65     SEE ALSO
  66         CacheClearU(), CacheControl()
  67
  68     INTERNALS
  69     Due to the strong cache coherency of x86 systems this function
  70     is actually not needed. CPU snoops the address lines and
  71     invalidate all cache which is out-of-date. It is valid for both
  72     D and I caches). Even a BM-DMA transfer are perfectly safe here.
  73
  74 ******************************************************************************/
  75 {
  76     AROS_LIBFUNC_INIT
  77
  78     AROS_LIBFUNC_EXIT
  79 } /* CacheClearE */
  80