arch/i386-pc/exec/traps.c

   1 /*
   2     Copyright © 1995-2001, The AROS Development Team. All rights reserved.
   3     $Id$
   4 */
   5
   6 #include <asm/segments.h>
   7 #include <asm/linkage.h>
   8 #include <asm/ptrace.h>
   9 #include <exec/alerts.h>
  10 #include <proto/exec.h>
  11 #include <aros/debug.h>
  12
  13 #include "traps.h"
  14
  15 #define __text __attribute__((section(".text")))
  16
  17 BUILD_COMMON_TRAP()
  18
  19 /* 0,1,5-7,9-17,19:
  20                 return address of these exceptions is the address of faulting instr
  21    1,3,4:
  22                 return address is address of instruction followed by trapping instr
  23                 (1 can be FAULT and TRAP)
  24         others:
  25                 ABORT = ??? (no information = no return address)
  26 */
  27
  28 BUILD_TRAP(0x00)
  29 BUILD_TRAP(0x01)
  30 BUILD_TRAP(0x02)
  31 BUILD_TRAP(0x03)
  32 BUILD_TRAP(0x04)
  33 BUILD_TRAP(0x05)
  34 BUILD_TRAP(0x06)
  35 BUILD_TRAP(0x07)
  36 BUILD_TRAP(0x08)
  37 BUILD_TRAP(0x09)
  38 BUILD_TRAP(0x0a)
  39 BUILD_TRAP(0x0b)
  40 BUILD_TRAP(0x0c)
  41 BUILD_TRAP(0x0d)
  42 BUILD_TRAP(0x0e)
  43 BUILD_TRAP(0x0f)
  44 BUILD_TRAP(0x10)
  45 BUILD_TRAP(0x11)
  46 BUILD_TRAP(0x12)
  47 BUILD_TRAP(0x13)
  48
  49 const void (*traps[0x14])(void) __text =
  50 {
  51         TRAP0x00_trap,
  52         TRAP0x01_trap,
  53         TRAP0x02_trap,
  54         TRAP0x03_trap,
  55         TRAP0x04_trap,
  56         TRAP0x05_trap,
  57         TRAP0x06_trap,
  58         TRAP0x07_trap,
  59         TRAP0x08_trap,
  60         TRAP0x09_trap,
  61         TRAP0x0a_trap,
  62         TRAP0x0b_trap,
  63         TRAP0x0c_trap,
  64         TRAP0x0d_trap,
  65         TRAP0x0e_trap,
  66         TRAP0x0f_trap,
  67         TRAP0x10_trap,
  68         TRAP0x11_trap,
  69         TRAP0x12_trap,
  70         TRAP0x13_trap
  71 };
  72
  73 static const struct { long long a; } *idt_base = (struct { long long a; } *)0x100;
  74
  75 #define _set_gate(gate_addr,type,dpl,addr) \
  76 do { \
  77   int __d0, __d1; \
  78   __asm__ __volatile__ ("movw %%dx,%%ax\n\t" \
  79         "movw %4,%%dx\n\t" \
  80         "movl %%eax,%0\n\t" \
  81         "movl %%edx,%1" \
  82         :"=m" (*((long *) (gate_addr))), \
  83          "=m" (*(1+(long *) (gate_addr))), "=&a" (__d0), "=&d" (__d1) \
  84         :"i" ((short) (0x8000+(dpl<<13)+(type<<8))), \
  85          "3" ((char *) (addr)),"2" (KERNEL_CS << 16)); \
  86 } while (0)
  87
  88
  89 void set_intr_gate(unsigned int n, void *addr)
  90 {
  91         _set_gate(idt_base+n,14,0,addr);
  92 }
  93
  94 void set_system_gate(unsigned int n, void *addr)
  95 {
  96         _set_gate(idt_base+n,14,3,addr);
  97 }
  98
  99 void do_TRAP(struct pt_regs regs)
 100 {
 101     ULONG alert;
 102
 103     kprintf("*** trap: eip = %x eflags = %x  ds = %x sp ~= %x\n",
 104             regs.eip, regs.eflags, regs.xds, &regs);
 105
 106         switch (regs.orig_eax)
 107         {
 108         case 0:
 109                 alert = ACPU_DivZero;
 110                 break;
 111         case 6:
 112                 alert = ACPU_InstErr;
 113                 break;
 114         default:
 115                 alert = AT_DeadEnd | 0x100 | regs.orig_eax;
 116         }
 117         Alert(alert);
 118 }
 119
 120 void Init_Traps(void) {
 121 int i;
 122
 123         for (i=0;i<20;i++)
 124         {
 125                 _set_gate(idt_base+i,14,0,traps[i]);
 126         }
 127 }