arch/common/hidd.radeon/radeon_macros.h

   1 /* Greetings text left due to code "borrowed" from XFree86 project */
   2
   3 /*
   4  * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
   5  *                VA Linux Systems Inc., Fremont, California.
   6  *
   7  * All Rights Reserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining
  10  * a copy of this software and associated documentation files (the
  11  * "Software"), to deal in the Software without restriction, including
  12  * without limitation on the rights to use, copy, modify, merge,
  13  * publish, distribute, sublicense, and/or sell copies of the Software,
  14  * and to permit persons to whom the Software is furnished to do so,
  15  * subject to the following conditions:
  16  *
  17  * The above copyright notice and this permission notice (including the
  18  * next paragraph) shall be included in all copies or substantial
  19  * portions of the Software.
  20  *
  21  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  24  * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
  25  * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  26  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  28  * DEALINGS IN THE SOFTWARE.
  29  */
  30
  31 /*
  32  * Authors:
  33  *   Kevin E. Martin <martin@xfree86.org>
  34  *   Rickard E. Faith <faith@valinux.com>
  35  *   Alan Hourihane <alanh@fairlite.demon.co.uk>
  36  *
  37  * References:
  38  *
  39  * !!!! FIXME !!!!
  40  *   RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
  41  *   Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
  42  *   1999.
  43  *
  44  * !!!! FIXME !!!!
  45  *   RAGE 128 Software Development Manual (Technical Reference Manual P/N
  46  *   SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
  47  *
  48  */
  49
  50
  51 #include <aros/macros.h>
  52
  53 #ifndef _RADEON_MACROS_H_
  54 #define _RADEON_MACROS_H_
  55
  56 #define RADEONMMIO  (sd->Card.MMIO)
  57
  58 #define RADEON_BIOS8(v)  (sd->Card.VBIOS[v])
  59 #define RADEON_BIOS16(v) (sd->Card.VBIOS[v] | \
  60                           (sd->Card.VBIOS[(v) + 1] << 8))
  61 #define RADEON_BIOS32(v) (sd->Card.VBIOS[v] | \
  62                           (sd->Card.VBIOS[(v) + 1] << 8) | \
  63                           (sd->Card.VBIOS[(v) + 2] << 16) | \
  64                           (sd->Card.VBIOS[(v) + 3] << 24))
  65
  66                                 /* Memory mapped register access macros */
  67 #define INREG8(addr)        (*(volatile UBYTE*)((UBYTE*)(RADEONMMIO)+(addr)))
  68 #define INREG16(addr)       AROS_LE2WORD((*(volatile UWORD*)((UBYTE*)(RADEONMMIO)+(addr))))
  69 #define INREG(addr)         AROS_LE2LONG((*(volatile ULONG*)((UBYTE*)(RADEONMMIO)+(addr))))
  70 #define OUTREG8(addr, val)  (*(volatile UBYTE*)((UBYTE*)(RADEONMMIO)+(addr)) = (val))
  71 #define OUTREG16(addr, val) (*(volatile UWORD*)((UBYTE*)(RADEONMMIO)+(addr)) = AROS_WORD2LE((val)))
  72 #define OUTREG(addr, val)   (*(volatile ULONG*)((UBYTE*)(RADEONMMIO)+(addr)) = AROS_LONG2LE((val)))
  73
  74 #define ADDRREG(addr)       ((volatile ULONG *)(APTR)(RADEONMMIO + (addr)))
  75
  76 #define OUTREGP(addr, val, mask)                                        \
  77 do {                                                                    \
  78     ULONG tmp = INREG(addr);                                            \
  79     tmp &= (mask);                                                      \
  80     tmp |= (val);                                                       \
  81     OUTREG(addr, tmp);                                                  \
  82 } while (0)
  83
  84 #define INPLL(sd, addr) RADEONINPLL(sd, addr)
  85
  86 #define OUTPLL(addr, val)                                               \
  87 do {                                                                    \
  88     OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) |                 \
  89                                       RADEON_PLL_WR_EN));               \
  90     OUTREG(RADEON_CLOCK_CNTL_DATA, val);                                \
  91 } while (0)
  92
  93 #define OUTPLLP(sd, addr, val, mask)                                    \
  94 do {                                                                    \
  95     ULONG tmp_ = INPLL(sd, addr);                                       \
  96     tmp_ &= (mask);                                                     \
  97     tmp_ |= (val);                                                      \
  98     OUTPLL(addr, tmp_);                                                 \
  99 } while (0)
 100
 101 #define OUTPAL_START(idx)                                               \
 102 do {                                                                    \
 103     OUTREG8(RADEON_PALETTE_INDEX, (idx));                               \
 104 } while (0)
 105
 106 #define OUTPAL_NEXT(r, g, b)                                            \
 107 do {                                                                    \
 108     OUTREG(RADEON_PALETTE_DATA, ((r) << 16) | ((g) << 8) | (b));        \
 109 } while (0)
 110
 111 #define OUTPAL_NEXT_CARD32(v)                                           \
 112 do {                                                                    \
 113     OUTREG(RADEON_PALETTE_DATA, (v & 0x00ffffff));                      \
 114 } while (0)
 115
 116 #define OUTPAL(idx, r, g, b)                                            \
 117 do {                                                                    \
 118     OUTPAL_START((idx));                                                \
 119     OUTPAL_NEXT((r), (g), (b));                                         \
 120 } while (0)
 121
 122 #define INPAL_START(idx)                                                \
 123 do {                                                                    \
 124     OUTREG(RADEON_PALETTE_INDEX, (idx) << 16);                          \
 125 } while (0)
 126
 127 #define INPAL_NEXT() INREG(RADEON_PALETTE_DATA)
 128
 129 #define PAL_SELECT(idx)                                                 \
 130 do {                                                                    \
 131     if (!idx) {                                                         \
 132         OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) &              \
 133                (ULONG)~RADEON_DAC2_PALETTE_ACC_CTL);                    \
 134     } else {                                                            \
 135         OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) |              \
 136                RADEON_DAC2_PALETTE_ACC_CTL);                            \
 137     }                                                                   \
 138 } while (0)
 139
 140
 141 #endif
 142