arch/x86_64-pc/kernel/intr.c

   1 #include <inttypes.h>
   2 #define DEBUG 0
   3 #include <aros/debug.h>
   4
   5 #include <stdio.h>
   6 #include <asm/cpu.h>
   7 #include <asm/io.h>
   8 #include <asm/segments.h>
   9 #include <aros/libcall.h>
  10 #include <aros/asmcall.h>
  11 #include <exec/execbase.h>
  12 #include <hardware/intbits.h>
  13
  14 #include <proto/exec.h>
  15
  16 #include "kernel_intern.h"
  17
  18 static void core_XTPIC_DisableIRQ(uint8_t irqnum);
  19 static void core_XTPIC_EnableIRQ(uint8_t irqnum);
  20
  21 AROS_LH4(void *, KrnAddIRQHandler,
  22          AROS_LHA(uint8_t, irq, D0),
  23          AROS_LHA(void *, handler, A0),
  24          AROS_LHA(void *, handlerData, A1),
  25          AROS_LHA(void *, handlerData2, A2),
  26          struct KernelBase *, KernelBase, 7, Kernel)
  27 {
  28     AROS_LIBFUNC_INIT
  29
  30     struct ExecBase *SysBase = TLS_GET(SysBase);
  31     struct IntrNode *handle = NULL;
  32     D(bug("[Kernel] KrnAddIRQHandler(%02x, %012p, %012p, %012p):\n", irq, handler, handlerData, handlerData2));
  33
  34     if (irq >=0 && irq <= 0xff)
  35     {
  36
  37         handle = AllocVecPooled(KernelBase->kb_MemPool, sizeof(struct IntrNode));
  38
  39 #warning TODO: Add IP range checking
  40
  41         D(bug("[Kernel]   handle=%012p\n", handle));
  42
  43         if (handle)
  44         {
  45             handle->in_Handler = handler;
  46             handle->in_HandlerData = handlerData;
  47             handle->in_HandlerData2 = handlerData2;
  48
  49             Disable();
  50             ADDHEAD(&KernelBase->kb_Intr[irq], &handle->in_Node);
  51             Enable();
  52
  53             if (KernelBase->kb_Intr[irq].lh_Type == KBL_XTPIC)
  54                 core_XTPIC_EnableIRQ(irq);
  55         }
  56     }
  57     return handle;
  58
  59     AROS_LIBFUNC_EXIT
  60 }
  61
  62 AROS_LH1(void, KrnRemIRQHandler,
  63          AROS_LHA(void *, handle, A0),
  64          struct KernelBase *, KernelBase, 8, Kernel)
  65 {
  66     AROS_LIBFUNC_INIT
  67
  68     struct IntrNode *h = handle;
  69
  70     Disable();
  71     REMOVE(h);
  72     Enable();
  73
  74     FreeVecPooled(KernelBase->kb_MemPool, h);
  75
  76     AROS_LIBFUNC_EXIT
  77 }
  78
  79 AROS_LH0I(void, KrnCli,
  80          struct KernelBase *, KernelBase, 9, Kernel)
  81 {
  82     AROS_LIBFUNC_INIT
  83
  84     asm volatile("cli");
  85
  86     AROS_LIBFUNC_EXIT
  87 }
  88
  89 AROS_LH0I(void, KrnSti,
  90          struct KernelBase *, KernelBase, 10, Kernel)
  91 {
  92     AROS_LIBFUNC_INIT
  93
  94     asm volatile("sti");
  95
  96     AROS_LIBFUNC_EXIT
  97 }
  98
  99
 100 static struct int_gate_64bit IGATES[256] __attribute__((used,aligned(256)));
 101 const struct
 102 {
 103     uint16_t size __attribute__((packed));
 104     uint64_t base __attribute__((packed));
 105 } IDT_sel = {sizeof(IGATES)-1, (uint64_t)IGATES};
 106
 107 #define STR_(x) #x
 108 #define STR(x) STR_(x)
 109
 110 #define IRQ_NAME_(nr) nr##_intr(void)
 111 #define IRQ_NAME(nr) IRQ_NAME_(IRQ##nr)
 112
 113 #define BUILD_IRQ(nr) \
 114     void IRQ_NAME(nr); \
 115     asm(".balign 8  ,0x90\n\t" \
 116         ".globl IRQ" STR(nr) "_intr\n\t" \
 117         ".type IRQ" STR(nr) "_intr,@function\n" \
 118         "IRQ" STR(nr) "_intr: pushq $0; pushq $" #nr "\n\t" \
 119         "jmp core_EnterInterrupt\n\t" \
 120         ".size IRQ" STR(nr) "_intr, . - IRQ" STR(nr) "_intr" \
 121     );
 122
 123 #define BUILD_IRQ_ERR(nr) \
 124     void IRQ_NAME(nr); \
 125     asm(".balign 8  ,0x90\n\t" \
 126         ".globl IRQ" STR(nr) "_intr\n\t" \
 127         ".type IRQ" STR(nr) "_intr,@function\n" \
 128         "IRQ" STR(nr) "_intr: pushq $" #nr "\n\t" \
 129         "jmp core_EnterInterrupt\n\t" \
 130         ".size IRQ" STR(nr) "_intr, . - IRQ" STR(nr) "_intr" \
 131     );
 132
 133 BUILD_IRQ(0x00)         // Divide-By-Zero Exception
 134 BUILD_IRQ(0x01)         // Debug Exception
 135 BUILD_IRQ(0x02)         // NMI Exception
 136 BUILD_IRQ(0x03)         // Breakpoint Exception
 137 BUILD_IRQ(0x04)         // Overflow Exception
 138 BUILD_IRQ(0x05)         // Bound-Range Exception
 139 BUILD_IRQ(0x06)         // Invalid-Opcode Exception
 140 BUILD_IRQ(0x07)         // Device-Not-Available Exception
 141 BUILD_IRQ_ERR(0x08)     // Double-Fault Exception
 142 BUILD_IRQ(0x09)         // Unused (used to be Coprocesor-Segment-Overrun)
 143 BUILD_IRQ_ERR(0x0a)     // Invalid-TSS Exception
 144 BUILD_IRQ_ERR(0x0b)     // Segment-Not-Present Exception
 145 BUILD_IRQ_ERR(0x0c)     // Stack Exception
 146 BUILD_IRQ_ERR(0x0d)     // General-Protection Exception
 147 BUILD_IRQ_ERR(0x0e)     // Page-Fault Exception
 148 BUILD_IRQ(0x0f)         // Reserved
 149 BUILD_IRQ(0x10)         // Floating-Point Exception
 150 BUILD_IRQ_ERR(0x11)     // Alignment-Check Exception
 151 BUILD_IRQ(0x12)         // Machine-Check Exception
 152 BUILD_IRQ(0x13)         // SIMD-Floating-Point Exception
 153 BUILD_IRQ(0x14) BUILD_IRQ(0x15) BUILD_IRQ(0x16) BUILD_IRQ(0x17)
 154 BUILD_IRQ(0x18) BUILD_IRQ(0x19) BUILD_IRQ(0x1a) BUILD_IRQ(0x1b)
 155 BUILD_IRQ(0x1c) BUILD_IRQ(0x1d) BUILD_IRQ(0x1e) BUILD_IRQ(0x1f)
 156
 157 #define B(x,y) BUILD_IRQ(x##y)
 158 #define B16(x) \
 159     B(x,0) B(x,1) B(x,2) B(x,3) B(x,4) B(x,5) B(x,6) B(x,7) \
 160     B(x,8) B(x,9) B(x,a) B(x,b) B(x,c) B(x,d) B(x,e) B(x,f)
 161
 162 B16(0x2)
 163 BUILD_IRQ(0x80)
 164 BUILD_IRQ(0xfe) // APIC timer
 165
 166 #define SAVE_REGS        \
 167         "pushq %rax; pushq %rbp; pushq %rbx; pushq %rdi; pushq %rsi; pushq %rdx;"  \
 168         "pushq %rcx; pushq %r8; pushq %r9; pushq %r10; pushq %r11; pushq %r12;"  \
 169         "pushq %r13; pushq %r14; pushq %r15; mov %ds,%eax; pushq %rax;"
 170
 171 #define RESTORE_REGS    \
 172         "popq %rax; mov %ax,%ds; mov %ax,%es; popq %r15; popq %r14; popq %r13;"  \
 173         "popq %r12; popq %r11; popq %r10; popq %r9; popq %r8; popq %rcx;" \
 174         "popq %rdx; popq %rsi; popq %rdi; popq %rbx; popq %rbp; popq %rax"
 175
 176 asm(
 177 "                .balign 32,0x90      \n"
 178 "                .globl core_EnterInterrupt \n"
 179 "                .type core_EnterInterrupt,@function \n"
 180 "core_EnterInterrupt: \n\t" SAVE_REGS "\n"
 181 "                movl    $" STR(KERNEL_DS) ",%eax \n"
 182 "                mov     %ax,%ds \n"
 183 "                mov     %ax,%es \n"
 184 "                movq    %rsp,%rdi \n"
 185 "                call    core_IRQHandle \n"
 186 "                movq    %rsp,%rdi \n"
 187 "                jmp     core_ExitInterrupt \n"
 188 "                .size core_EnterInterrupt, .-core_EnterInterrupt"
 189 );
 190
 191 asm(
 192 "                .balign 32,0x90      \n"
 193 "                .globl core_LeaveInterrupt \n"
 194 "                .type core_LeaveInterrupt,@function \n"
 195 "core_LeaveInterrupt: movq %rdi,%rsp \n\t" RESTORE_REGS "\n"
 196 "                addq $16,%rsp \n"
 197 "                iretq \n"
 198 "                .size core_LeaveInterrupt, .-core_LeaveInterrupt"
 199 );
 200
 201 #define IRQ(x,y) \
 202     (const void (*)(void))IRQ##x##y##_intr
 203
 204 #define IRQLIST_16(x) \
 205     IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
 206     IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
 207     IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
 208     IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
 209
 210 const void __attribute__((section(".text"))) (*interrupt[256])(void) = {
 211     IRQLIST_16(0x0), IRQLIST_16(0x1), IRQLIST_16(0x2)
 212 };
 213
 214 void core_SetupIDT()
 215 {
 216     int i;
 217     uintptr_t off;
 218     rkprintf("[Kernel] Setting all interrupt handlers to default value\n");
 219
 220     for (i=0; i < 256; i++)
 221     {
 222         if (interrupt[i])
 223             off = (uintptr_t)interrupt[i];
 224         else if (i == 0x80)
 225             off = (uintptr_t)&IRQ0x80_intr;
 226         else if (i == 0xfe)
 227             off = (uintptr_t)&IRQ0xfe_intr;
 228         else
 229             off = (uintptr_t)&core_DefaultIRETQ;
 230
 231         IGATES[i].offset_low = off & 0xffff;
 232         IGATES[i].offset_mid = (off >> 16) & 0xffff;
 233         IGATES[i].offset_high = (off >> 32) & 0xffffffff;
 234         IGATES[i].type = 0x0e;
 235         IGATES[i].dpl = 3;
 236         IGATES[i].p = 1;
 237         IGATES[i].selector = KERNEL_CS;
 238         IGATES[i].ist = 0;
 239     }
 240
 241     asm volatile ("lidt %0"::"m"(IDT_sel));
 242 }
 243
 244
 245 void core_Cause(struct ExecBase *SysBase)
 246 {
 247     struct IntVector *iv = &SysBase->IntVects[INTB_SOFTINT];
 248
 249     /* If the SoftInt vector in SysBase is set, call it. It will do the rest for us */
 250     if (iv->iv_Code)
 251     {
 252         AROS_UFC5(void, iv->iv_Code,
 253             AROS_UFCA(ULONG, 0, D1),
 254             AROS_UFCA(ULONG, 0, A0),
 255             AROS_UFCA(APTR, 0, A1),
 256             AROS_UFCA(APTR, iv->iv_Code, A5),
 257             AROS_UFCA(struct ExecBase *, SysBase, A6)
 258         );
 259     }
 260 }
 261
 262 static void core_APIC_AckIntr(uint8_t intnum)
 263 {
 264     struct KernelBase *KernelBase = TLS_GET(KernelBase);
 265     asm volatile ("movl %0,(%1)"::"r"(0),"r"(KernelBase->kb_APICBase + 0xb0));
 266 }
 267
 268 static void core_XTPIC_DisableIRQ(uint8_t irqnum)
 269 {
 270     struct KernelBase *KernelBase = TLS_GET(KernelBase);
 271     irqnum &= 15;
 272     KernelBase->kb_XTPIC_Mask |= 1 << irqnum;
 273
 274     if (irqnum >= 8)
 275     {
 276         outb((KernelBase->kb_XTPIC_Mask >> 8) & 0xff, 0xA1);
 277     }
 278     else
 279     {
 280         outb(KernelBase->kb_XTPIC_Mask & 0xff, 0x21);
 281     }
 282 }
 283
 284 static void core_XTPIC_EnableIRQ(uint8_t irqnum)
 285 {
 286     struct KernelBase *KernelBase = TLS_GET(KernelBase);
 287     irqnum &= 15;
 288     KernelBase->kb_XTPIC_Mask &= ~(1 << irqnum);
 289
 290     if (irqnum >= 8)
 291     {
 292         outb((KernelBase->kb_XTPIC_Mask >> 8) & 0xff, 0xA1);
 293     }
 294     else
 295     {
 296         outb(KernelBase->kb_XTPIC_Mask & 0xff, 0x21);
 297     }
 298 }
 299
 300 static void core_XTPIC_AckIntr(uint8_t intnum)
 301 {
 302     struct KernelBase *KernelBase = TLS_GET(KernelBase);
 303     intnum &= 15;
 304     KernelBase->kb_XTPIC_Mask |= 1 << intnum;
 305
 306     if (intnum >= 8)
 307     {
 308         outb((KernelBase->kb_XTPIC_Mask >> 8) & 0xff, 0xA1);
 309         outb(0x62, 0x20);
 310         outb(0x20, 0xa0);
 311     }
 312     else
 313     {
 314         outb(KernelBase->kb_XTPIC_Mask & 0xff, 0x21);
 315         outb(0x20, 0x20);
 316     }
 317 }
 318
 319 void core_IRQHandle(regs_t regs)
 320 {
 321     struct ExecBase *SysBase = TLS_GET(SysBase);        // *(struct ExecBase **)4;
 322     struct KernelBase *KernelBase = TLS_GET(KernelBase);
 323     struct Task *t = NULL;
 324     int die = 0;
 325
 326     if (SysBase)
 327         t = SysBase->ThisTask;
 328
 329     if ((regs.irq_number < 0x20) && regs.irq_number != 0x0e)
 330         rkprintf("IRQ %02x:", regs.irq_number);
 331
 332     if (regs.irq_number == 0x03)        /* Debug */
 333     {
 334         rkprintf("[Kernel] INT3 debug fault!\n");
 335
 336         rkprintf("[Kernel]  stack=%04x:%012x rflags=%016x ip=%04x:%012x err=%08x\n",
 337                  regs.return_ss, regs.return_rsp, regs.return_rflags,
 338                  regs.return_cs, regs.return_rip, regs.error_code);
 339
 340         rkprintf("[Kernel]  rax=%016lx rbx=%016lx rcx=%016lx rdx=%016lx\n", regs.rax, regs.rbx, regs.rcx, regs.rdx);
 341         rkprintf("[Kernel]  rsi=%016lx rdi=%016lx rbp=%016lx rsp=%016lx\n", regs.rsi, regs.rdi, regs.rbp, regs.return_rsp);
 342         rkprintf("[Kernel]  r08=%016lx r09=%016lx r10=%016lx r11=%016lx\n", regs.r8, regs.r9, regs.r10, regs.r11);
 343         rkprintf("[Kernel]  r12=%016lx r13=%016lx r14=%016lx r15=%016lx\n", regs.r12, regs.r13, regs.r14, regs.r15);
 344
 345         rkprintf("[Kenrel] Stack:\n");
 346         int i;
 347         uint64_t *ptr = (void*)regs.return_rsp;
 348         for (i=0; i < 10; i++)
 349         {
 350             rkprintf("[Kernel]   %02x: %016p\n", i*8, ptr[i]);
 351         }
 352     }
 353     else if (regs.irq_number == 0x06)        /* GPF */
 354     {
 355         rkprintf("[Kernel] UNDEFINED INSTRUCTION!\n");
 356
 357         if (t)
 358         {
 359             rkprintf("[Kernel]  %s %p '%s'\n",
 360                      t->tc_Node.ln_Type == NT_TASK?"task":"process", t, t->tc_Node.ln_Name);
 361         }
 362
 363         rkprintf("[Kernel]  stack=%04x:%012x rflags=%016x ip=%04x:%012x err=%08x\n",
 364                  regs.return_ss, regs.return_rsp, regs.return_rflags,
 365                  regs.return_cs, regs.return_rip, regs.error_code);
 366
 367         rkprintf("[Kernel]  rax=%016lx rbx=%016lx rcx=%016lx rdx=%016lx\n", regs.rax, regs.rbx, regs.rcx, regs.rdx);
 368         rkprintf("[Kernel]  rsi=%016lx rdi=%016lx rbp=%016lx rsp=%016lx\n", regs.rsi, regs.rdi, regs.rbp, regs.return_rsp);
 369         rkprintf("[Kernel]  r08=%016lx r09=%016lx r10=%016lx r11=%016lx\n", regs.r8, regs.r9, regs.r10, regs.r11);
 370         rkprintf("[Kernel]  r12=%016lx r13=%016lx r14=%016lx r15=%016lx\n", regs.r12, regs.r13, regs.r14, regs.r15);
 371         die = 1;
 372
 373         int i;
 374         uint8_t *ptr = (uint8_t *)regs.return_rip;
 375
 376         rkprintf("[Kernel]  ");
 377
 378         for (i=0; i < 16; i++)
 379             rkprintf("%02x ", ptr[i]);
 380
 381         rkprintf("\n");
 382     }
 383     else if (regs.irq_number == 0x07)        /* GPF */
 384     {
 385         rkprintf("[Kernel] Device Not Available!\n");
 386
 387         if (t)
 388         {
 389             rkprintf("[Kernel]  %s %p '%s'\n",
 390                      t->tc_Node.ln_Type == NT_TASK?"task":"process", t, t->tc_Node.ln_Name);
 391         }
 392
 393         rkprintf("[Kernel]  stack=%04x:%012x rflags=%016x ip=%04x:%012x err=%08x\n",
 394                  regs.return_ss, regs.return_rsp, regs.return_rflags,
 395                  regs.return_cs, regs.return_rip, regs.error_code);
 396
 397         rkprintf("[Kernel]  rax=%016lx rbx=%016lx rcx=%016lx rdx=%016lx\n", regs.rax, regs.rbx, regs.rcx, regs.rdx);
 398         rkprintf("[Kernel]  rsi=%016lx rdi=%016lx rbp=%016lx rsp=%016lx\n", regs.rsi, regs.rdi, regs.rbp, regs.return_rsp);
 399         rkprintf("[Kernel]  r08=%016lx r09=%016lx r10=%016lx r11=%016lx\n", regs.r8, regs.r9, regs.r10, regs.r11);
 400         rkprintf("[Kernel]  r12=%016lx r13=%016lx r14=%016lx r15=%016lx\n", regs.r12, regs.r13, regs.r14, regs.r15);
 401         die = 1;
 402     }
 403     else if (regs.irq_number == 0x0D)        /* GPF */
 404     {
 405         rkprintf("[Kernel] GENERAL PROTECTION FAULT!\n");
 406
 407         if (t)
 408         {
 409             rkprintf("[Kernel]  %s %p '%s'\n",
 410                      t->tc_Node.ln_Type == NT_TASK?"task":"process", t, t->tc_Node.ln_Name);
 411         }
 412
 413         rkprintf("[Kernel]  stack=%04x:%012x rflags=%016x ip=%04x:%012x err=%08x\n",
 414                  regs.return_ss, regs.return_rsp, regs.return_rflags,
 415                  regs.return_cs, regs.return_rip, regs.error_code);
 416
 417         rkprintf("[Kernel]  rax=%016lx rbx=%016lx rcx=%016lx rdx=%016lx\n", regs.rax, regs.rbx, regs.rcx, regs.rdx);
 418         rkprintf("[Kernel]  rsi=%016lx rdi=%016lx rbp=%016lx rsp=%016lx\n", regs.rsi, regs.rdi, regs.rbp, regs.return_rsp);
 419         rkprintf("[Kernel]  r08=%016lx r09=%016lx r10=%016lx r11=%016lx\n", regs.r8, regs.r9, regs.r10, regs.r11);
 420         rkprintf("[Kernel]  r12=%016lx r13=%016lx r14=%016lx r15=%016lx\n", regs.r12, regs.r13, regs.r14, regs.r15);
 421         rkprintf("[Kernel]  *rsp=%016lx\n", *(uint64_t *)regs.return_rsp);
 422         die = 1;
 423     }
 424     else if (regs.irq_number == 0x0e)        /* Page fault */
 425     {
 426         void *ptr = rdcr(cr2);
 427         unsigned char *ip = regs.return_rip;
 428         int i;
 429
 430         die = 1;
 431
 432         if (ptr == (void*)4)
 433         {
 434 //            rkprintf("[Kernel] ** Code at %012lx is trying to access the SysBase at 4UL.\n", regs.return_rip);
 435
 436             if (   (ip[0] & 0xfb) == 0x48 &&
 437                     ip[1]         == 0x8b &&
 438                    (ip[2] & 0xc7) == 0x04 &&
 439                     ip[3]         == 0x25
 440                )
 441             {
 442                 int reg = ((ip[2] >> 3) & 0x07) | ((ip[0] & 0x04) << 1);
 443
 444                 switch(reg)
 445                 {
 446                     case 0:
 447                         regs.rax = SysBase;
 448                         break;
 449                     case 1:
 450                         regs.rcx = SysBase;
 451                         break;
 452                     case 2:
 453                         regs.rdx = SysBase;
 454                         break;
 455                     case 3:
 456                         regs.rbx = SysBase;
 457                         break;
 458 //                    case 4:   /* Cannot put SysBase into rSP register */
 459 //                        regs.return_rsp = SysBase;
 460 //                        break;
 461                     case 5:
 462                         regs.rbp = SysBase;
 463                         break;
 464                     case 6:
 465                         regs.rsi = SysBase;
 466                         break;
 467                     case 7:
 468                         regs.rdi = SysBase;
 469                         break;
 470                     case 8:
 471                         regs.r8 = SysBase;
 472                         break;
 473                     case 9:
 474                         regs.r9 = SysBase;
 475                         break;
 476                     case 10:
 477                         regs.r10 = SysBase;
 478                         break;
 479                     case 11:
 480                         regs.r11 = SysBase;
 481                         break;
 482                     case 12:
 483                         regs.r12 = SysBase;
 484                         break;
 485                     case 13:
 486                         regs.r13 = SysBase;
 487                         break;
 488                     case 14:
 489                         regs.r14 = SysBase;
 490                         break;
 491                     case 15:
 492                         regs.r15 = SysBase;
 493                         break;
 494                 }
 495
 496                 regs.return_rip += 8;
 497
 498                 die = 0;
 499             }
 500             else if (   (ip[0] & 0xfb) == 0x48 &&
 501                     ip[1]         == 0x8b &&
 502                    (ip[2] & 0xc7) == 0x05
 503                )
 504             {
 505                 int reg = ((ip[2] >> 3) & 0x07) | ((ip[0] & 0x04) << 1);
 506
 507                 switch(reg)
 508                 {
 509                     case 0:
 510                         regs.rax = SysBase;
 511                         break;
 512                     case 1:
 513                         regs.rcx = SysBase;
 514                         break;
 515                     case 2:
 516                         regs.rdx = SysBase;
 517                         break;
 518                     case 3:
 519                         regs.rbx = SysBase;
 520                         break;
 521 //                    case 4:   /* Cannot put SysBase into rSP register */
 522 //                        regs.return_rsp = SysBase;
 523 //                        break;
 524                     case 5:
 525                         regs.rbp = SysBase;
 526                         break;
 527                     case 6:
 528                         regs.rsi = SysBase;
 529                         break;
 530                     case 7:
 531                         regs.rdi = SysBase;
 532                         break;
 533                     case 8:
 534                         regs.r8 = SysBase;
 535                         break;
 536                     case 9:
 537                         regs.r9 = SysBase;
 538                         break;
 539                     case 10:
 540                         regs.r10 = SysBase;
 541                         break;
 542                     case 11:
 543                         regs.r11 = SysBase;
 544                         break;
 545                     case 12:
 546                         regs.r12 = SysBase;
 547                         break;
 548                     case 13:
 549                         regs.r13 = SysBase;
 550                         break;
 551                     case 14:
 552                         regs.r14 = SysBase;
 553                         break;
 554                     case 15:
 555                         regs.r15 = SysBase;
 556                         break;
 557                 }
 558
 559                 regs.return_rip += 7;
 560
 561                 die = 0;
 562             }
 563         }
 564
 565         if (die)
 566         {
 567             rkprintf("IRQ %02x:", regs.irq_number);
 568             rkprintf("[Kernel] PAGE FAULT EXCEPTION! %016p\n",ptr);
 569
 570             if (t)
 571             {
 572                 rkprintf("[Kernel]  %s %p '%s'\n",
 573                          t->tc_Node.ln_Type == NT_TASK?"task":"process", t, t->tc_Node.ln_Name);
 574             }
 575
 576             rkprintf("[Kernel]  stack=%04x:%012x rflags=%016x ip=%04x:%012x err=%08x\n",
 577                      regs.return_ss, regs.return_rsp, regs.return_rflags,
 578                      regs.return_cs, regs.return_rip, regs.error_code);
 579
 580             rkprintf("[Kernel]  rax=%016lx rbx=%016lx rcx=%016lx rdx=%016lx\n", regs.rax, regs.rbx, regs.rcx, regs.rdx);
 581             rkprintf("[Kernel]  rsi=%016lx rdi=%016lx rbp=%016lx rsp=%016lx\n", regs.rsi, regs.rdi, regs.rbp, regs.return_rsp);
 582             rkprintf("[Kernel]  r08=%016lx r09=%016lx r10=%016lx r11=%016lx\n", regs.r8, regs.r9, regs.r10, regs.r11);
 583             rkprintf("[Kernel]  r12=%016lx r13=%016lx r14=%016lx r15=%016lx\n", regs.r12, regs.r13, regs.r14, regs.r15);
 584             rkprintf("[Kernel]  *rsp=%016lx\n", *(uint64_t *)regs.return_rsp);
 585
 586             rkprintf("[Kernel]  Insn: ");
 587             for (i = 0; i < 16; i++)
 588                 rkprintf("%02x ", ip[i]);
 589             rkprintf("\n");
 590
 591         }
 592     }
 593     else if (regs.irq_number == 0x80) /* Syscall? */
 594     {
 595         switch (regs.rax)
 596         {
 597             case SC_CAUSE:
 598                 core_Cause(SysBase);
 599                 break;
 600
 601             case SC_DISPATCH:
 602                 core_Dispatch(&regs);
 603                 break;
 604
 605             case SC_SWITCH:
 606                 core_Switch(&regs);
 607                 break;
 608
 609             case SC_SCHEDULE:
 610                 if (regs.ds != KERNEL_DS)
 611                     core_Schedule(&regs);
 612                 break;
 613         }
 614     }
 615
 616     if (KernelBase)
 617     {
 618         if (KernelBase->kb_Intr[regs.irq_number].lh_Type == KBL_APIC)
 619             core_APIC_AckIntr(regs.irq_number);
 620
 621         if (KernelBase->kb_Intr[regs.irq_number].lh_Type == KBL_XTPIC)
 622             core_XTPIC_AckIntr(regs.irq_number);
 623
 624
 625         if (!IsListEmpty(&KernelBase->kb_Intr[regs.irq_number]))
 626         {
 627             struct IntrNode *in, *in2;
 628
 629             ForeachNodeSafe(&KernelBase->kb_Intr[regs.irq_number], in, in2)
 630             {
 631                 if (in->in_Handler)
 632                     in->in_Handler(in->in_HandlerData, in->in_HandlerData2);
 633             }
 634
 635             if (KernelBase->kb_Intr[regs.irq_number].lh_Type == KBL_XTPIC)
 636                 core_XTPIC_EnableIRQ(regs.irq_number);
 637         }
 638     }
 639
 640     while (die) asm volatile ("hlt");
 641 }
 642
 643 asm(".text\n\t"
 644     ".globl core_DefaultIRETQ\n\t"
 645     ".type core_DefaultIRETQ,@function\n"
 646 "core_DefaultIRETQ: iretq");