Updated PCI IDs to latest snapshot.
[tangerine.git] / arch / .unmaintained / dummy / cachecontrol.c
blob9d84997ebc2e8af7a630afe26b4fcbe8f5ea6a18
1 |*****************************************************************************
3 | NAME
5 | __AROS_LH2(ULONG, CacheControl,
7 | SYNOPSIS
8 | __AROS_LA(ULONG, cacheBits, D0),
9 | __AROS_LA(ULONG, cacheMask, D1),
11 | LOCATION
12 | struct ExecBase *, SysBase, 108, Exec)
14 | FUNCTION
15 | Change/read the values in the 68030 cacr register. Only the bits set
16 | in the mask parameter are affected.
18 | INPUTS
19 | cacheBits - new bit values.
20 | cacheMask - Bits to change.
22 | RESULT
23 | Old contents of cacr register.
25 | NOTES
27 | EXAMPLE
29 | BUGS
31 | SEE ALSO
33 | INTERNALS
35 | HISTORY
37 |******************************************************************************
39 | Simple 68000s have no chaches
40 .globl _Exec_CacheControl
41 _Exec_CacheControl:
42 rts