arch/common/boot/grub/netboot/3c509.h

   1 /*
   2  * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions are
   6  * met: 1. Redistributions of source code must retain the above copyright
   7  * notice, this list of conditions and the following disclaimer. 2. The name
   8  * of the author may not be used to endorse or promote products derived from
   9  * this software withough specific prior written permission
  10  *
  11  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
  12  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
  14  * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  15  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
  16  * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  17  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  18  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  19  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  20  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  21  *
  22  * if_epreg.h,v 1.4 1994/11/13 10:12:37 gibbs Exp Modified by:
  23  *
  24  October 2, 1994
  25
  26  Modified by: Andres Vega Garcia
  27
  28  INRIA - Sophia Antipolis, France
  29  e-mail: avega@sophia.inria.fr
  30  finger: avega@pax.inria.fr
  31
  32  */
  33
  34 /*
  35  * Ethernet software status per interface.
  36  */
  37 /*
  38  * Some global constants
  39  */
  40
  41 #define TX_INIT_RATE            16
  42 #define TX_INIT_MAX_RATE        64
  43 #define RX_INIT_LATENCY         64
  44 #define RX_INIT_EARLY_THRESH    64
  45 #define MIN_RX_EARLY_THRESHF    16      /* not less than ether_header */
  46 #define MIN_RX_EARLY_THRESHL    4
  47
  48 #define EEPROMSIZE      0x40
  49 #define MAX_EEPROMBUSY  1000
  50 #define EP_LAST_TAG     0xd7
  51 #define EP_MAX_BOARDS   16
  52 #define EP_ID_PORT      0x100
  53
  54 /*
  55  * some macros to acces long named fields
  56  */
  57 #define IS_BASE (eth_nic_base)
  58 #define BASE    (eth_nic_base)
  59
  60 /*
  61  * Commands to read/write EEPROM trough EEPROM command register (Window 0,
  62  * Offset 0xa)
  63  */
  64 #define EEPROM_CMD_RD   0x0080  /* Read:  Address required (5 bits) */
  65 #define EEPROM_CMD_WR   0x0040  /* Write: Address required (5 bits) */
  66 #define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */
  67 #define EEPROM_CMD_EWEN 0x0030  /* Erase/Write Enable: No data required */
  68
  69 #define EEPROM_BUSY             (1<<15)
  70 #define EEPROM_TST_MODE         (1<<14)
  71
  72 /*
  73  * Some short functions, worth to let them be a macro
  74  */
  75 #define is_eeprom_busy(b) (inw((b)+EP_W0_EEPROM_COMMAND)&EEPROM_BUSY)
  76 #define GO_WINDOW(x)    outw(WINDOW_SELECT|(x), BASE+EP_COMMAND)
  77
  78 /**************************************************************************
  79  *
  80  * These define the EEPROM data structure.  They are used in the probe
  81  * function to verify the existance of the adapter after having sent
  82  * the ID_Sequence.
  83  *
  84  * There are others but only the ones we use are defined here.
  85  *
  86  **************************************************************************/
  87
  88 #define EEPROM_NODE_ADDR_0      0x0     /* Word */
  89 #define EEPROM_NODE_ADDR_1      0x1     /* Word */
  90 #define EEPROM_NODE_ADDR_2      0x2     /* Word */
  91 #define EEPROM_PROD_ID          0x3     /* 0x9[0-f]50 */
  92 #define EEPROM_MFG_ID           0x7     /* 0x6d50 */
  93 #define EEPROM_ADDR_CFG         0x8     /* Base addr */
  94 #define EEPROM_RESOURCE_CFG     0x9     /* IRQ. Bits 12-15 */
  95
  96 /**************************************************************************
  97  *
  98  * These are the registers for the 3Com 3c509 and their bit patterns when
  99  * applicable.  They have been taken out the the "EtherLink III Parallel
 100  * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual
 101  * from 3com.
 102  *
 103  **************************************************************************/
 104
 105 #define EP_COMMAND              0x0e    /* Write. BASE+0x0e is always a
 106                                          * command reg. */
 107 #define EP_STATUS               0x0e    /* Read. BASE+0x0e is always status
 108                                          * reg. */
 109 #define EP_WINDOW               0x0f    /* Read. BASE+0x0f is always window
 110                                          * reg. */
 111 /*
 112  * Window 0 registers. Setup.
 113  */
 114 /* Write */
 115 #define EP_W0_EEPROM_DATA       0x0c
 116 #define EP_W0_EEPROM_COMMAND    0x0a
 117 #define EP_W0_RESOURCE_CFG      0x08
 118 #define EP_W0_ADDRESS_CFG       0x06
 119 #define EP_W0_CONFIG_CTRL       0x04
 120 /* Read */
 121 #define EP_W0_PRODUCT_ID        0x02
 122 #define EP_W0_MFG_ID            0x00
 123
 124 /*
 125  * Window 1 registers. Operating Set.
 126  */
 127 /* Write */
 128 #define EP_W1_TX_PIO_WR_2       0x02
 129 #define EP_W1_TX_PIO_WR_1       0x00
 130 /* Read */
 131 #define EP_W1_FREE_TX           0x0c
 132 #define EP_W1_TX_STATUS         0x0b    /* byte */
 133 #define EP_W1_TIMER             0x0a    /* byte */
 134 #define EP_W1_RX_STATUS         0x08
 135 #define EP_W1_RX_PIO_RD_2       0x02
 136 #define EP_W1_RX_PIO_RD_1       0x00
 137
 138 /*
 139  * Window 2 registers. Station Address Setup/Read
 140  */
 141 /* Read/Write */
 142 #define EP_W2_ADDR_5            0x05
 143 #define EP_W2_ADDR_4            0x04
 144 #define EP_W2_ADDR_3            0x03
 145 #define EP_W2_ADDR_2            0x02
 146 #define EP_W2_ADDR_1            0x01
 147 #define EP_W2_ADDR_0            0x00
 148
 149 /*
 150  * Window 3 registers.  FIFO Management.
 151  */
 152 /* Read */
 153 #define EP_W3_FREE_TX           0x0c
 154 #define EP_W3_FREE_RX           0x0a
 155
 156 /*
 157  * Window 4 registers. Diagnostics.
 158  */
 159 /* Read/Write */
 160 #define EP_W4_MEDIA_TYPE        0x0a
 161 #define EP_W4_CTRLR_STATUS      0x08
 162 #define EP_W4_NET_DIAG          0x06
 163 #define EP_W4_FIFO_DIAG         0x04
 164 #define EP_W4_HOST_DIAG         0x02
 165 #define EP_W4_TX_DIAG           0x00
 166
 167 /*
 168  * Window 5 Registers.  Results and Internal status.
 169  */
 170 /* Read */
 171 #define EP_W5_READ_0_MASK       0x0c
 172 #define EP_W5_INTR_MASK         0x0a
 173 #define EP_W5_RX_FILTER         0x08
 174 #define EP_W5_RX_EARLY_THRESH   0x06
 175 #define EP_W5_TX_AVAIL_THRESH   0x02
 176 #define EP_W5_TX_START_THRESH   0x00
 177
 178 /*
 179  * Window 6 registers. Statistics.
 180  */
 181 /* Read/Write */
 182 #define TX_TOTAL_OK             0x0c
 183 #define RX_TOTAL_OK             0x0a
 184 #define TX_DEFERRALS            0x08
 185 #define RX_FRAMES_OK            0x07
 186 #define TX_FRAMES_OK            0x06
 187 #define RX_OVERRUNS             0x05
 188 #define TX_COLLISIONS           0x04
 189 #define TX_AFTER_1_COLLISION    0x03
 190 #define TX_AFTER_X_COLLISIONS   0x02
 191 #define TX_NO_SQE               0x01
 192 #define TX_CD_LOST              0x00
 193
 194 /****************************************
 195  *
 196  * Register definitions.
 197  *
 198  ****************************************/
 199
 200 /*
 201  * Command register. All windows.
 202  *
 203  * 16 bit register.
 204  *     15-11:  5-bit code for command to be executed.
 205  *     10-0:   11-bit arg if any. For commands with no args;
 206  *            this can be set to anything.
 207  */
 208 #define GLOBAL_RESET            (unsigned short) 0x0000 /* Wait at least 1ms
 209                                                          * after issuing */
 210 #define WINDOW_SELECT           (unsigned short) (0x1<<11)
 211 #define START_TRANSCEIVER       (unsigned short) (0x2<<11)      /* Read ADDR_CFG reg to
 212                                                          * determine whether
 213                                                          * this is needed. If
 214                                                          * so; wait 800 uSec
 215                                                          * before using trans-
 216                                                          * ceiver. */
 217 #define RX_DISABLE              (unsigned short) (0x3<<11)      /* state disabled on
 218                                                          * power-up */
 219 #define RX_ENABLE               (unsigned short) (0x4<<11)
 220 #define RX_RESET                (unsigned short) (0x5<<11)
 221 #define RX_DISCARD_TOP_PACK     (unsigned short) (0x8<<11)
 222 #define TX_ENABLE               (unsigned short) (0x9<<11)
 223 #define TX_DISABLE              (unsigned short) (0xa<<11)
 224 #define TX_RESET                (unsigned short) (0xb<<11)
 225 #define REQ_INTR                (unsigned short) (0xc<<11)
 226 #define SET_INTR_MASK           (unsigned short) (0xe<<11)
 227 #define SET_RD_0_MASK           (unsigned short) (0xf<<11)
 228 #define SET_RX_FILTER           (unsigned short) (0x10<<11)
 229 #define FIL_INDIVIDUAL  (unsigned short) (0x1)
 230 #define FIL_GROUP               (unsigned short) (0x2)
 231 #define FIL_BRDCST      (unsigned short) (0x4)
 232 #define FIL_ALL         (unsigned short) (0x8)
 233 #define SET_RX_EARLY_THRESH     (unsigned short) (0x11<<11)
 234 #define SET_TX_AVAIL_THRESH     (unsigned short) (0x12<<11)
 235 #define SET_TX_START_THRESH     (unsigned short) (0x13<<11)
 236 #define STATS_ENABLE            (unsigned short) (0x15<<11)
 237 #define STATS_DISABLE           (unsigned short) (0x16<<11)
 238 #define STOP_TRANSCEIVER        (unsigned short) (0x17<<11)
 239 /*
 240  * The following C_* acknowledge the various interrupts. Some of them don't
 241  * do anything.  See the manual.
 242  */
 243 #define ACK_INTR                (unsigned short) (0x6800)
 244 #define C_INTR_LATCH    (unsigned short) (ACK_INTR|0x1)
 245 #define C_CARD_FAILURE  (unsigned short) (ACK_INTR|0x2)
 246 #define C_TX_COMPLETE   (unsigned short) (ACK_INTR|0x4)
 247 #define C_TX_AVAIL      (unsigned short) (ACK_INTR|0x8)
 248 #define C_RX_COMPLETE   (unsigned short) (ACK_INTR|0x10)
 249 #define C_RX_EARLY      (unsigned short) (ACK_INTR|0x20)
 250 #define C_INT_RQD               (unsigned short) (ACK_INTR|0x40)
 251 #define C_UPD_STATS     (unsigned short) (ACK_INTR|0x80)
 252
 253 /*
 254  * Status register. All windows.
 255  *
 256  *     15-13:  Window number(0-7).
 257  *     12:     Command_in_progress.
 258  *     11:     reserved.
 259  *     10:     reserved.
 260  *     9:      reserved.
 261  *     8:      reserved.
 262  *     7:      Update Statistics.
 263  *     6:      Interrupt Requested.
 264  *     5:      RX Early.
 265  *     4:      RX Complete.
 266  *     3:      TX Available.
 267  *     2:      TX Complete.
 268  *     1:      Adapter Failure.
 269  *     0:      Interrupt Latch.
 270  */
 271 #define S_INTR_LATCH            (unsigned short) (0x1)
 272 #define S_CARD_FAILURE          (unsigned short) (0x2)
 273 #define S_TX_COMPLETE           (unsigned short) (0x4)
 274 #define S_TX_AVAIL              (unsigned short) (0x8)
 275 #define S_RX_COMPLETE           (unsigned short) (0x10)
 276 #define S_RX_EARLY              (unsigned short) (0x20)
 277 #define S_INT_RQD               (unsigned short) (0x40)
 278 #define S_UPD_STATS             (unsigned short) (0x80)
 279 #define S_5_INTS                (S_CARD_FAILURE|S_TX_COMPLETE|\
 280                                  S_TX_AVAIL|S_RX_COMPLETE|S_RX_EARLY)
 281 #define S_COMMAND_IN_PROGRESS   (unsigned short) (0x1000)
 282
 283 /*
 284  * FIFO Registers.
 285  * RX Status. Window 1/Port 08
 286  *
 287  *     15:     Incomplete or FIFO empty.
 288  *     14:     1: Error in RX Packet   0: Incomplete or no error.
 289  *     13-11:  Type of error.
 290  *            1000 = Overrun.
 291  *            1011 = Run Packet Error.
 292  *            1100 = Alignment Error.
 293  *            1101 = CRC Error.
 294  *            1001 = Oversize Packet Error (>1514 bytes)
 295  *            0010 = Dribble Bits.
 296  *            (all other error codes, no errors.)
 297  *
 298  *     10-0:   RX Bytes (0-1514)
 299  */
 300 #define ERR_RX_INCOMPLETE       (unsigned short) (0x1<<15)
 301 #define ERR_RX                  (unsigned short) (0x1<<14)
 302 #define ERR_RX_OVERRUN          (unsigned short) (0x8<<11)
 303 #define ERR_RX_RUN_PKT          (unsigned short) (0xb<<11)
 304 #define ERR_RX_ALIGN            (unsigned short) (0xc<<11)
 305 #define ERR_RX_CRC              (unsigned short) (0xd<<11)
 306 #define ERR_RX_OVERSIZE         (unsigned short) (0x9<<11)
 307 #define ERR_RX_DRIBBLE          (unsigned short) (0x2<<11)
 308
 309 /*
 310  * FIFO Registers.
 311  * TX Status. Window 1/Port 0B
 312  *
 313  *   Reports the transmit status of a completed transmission. Writing this
 314  *   register pops the transmit completion stack.
 315  *
 316  *   Window 1/Port 0x0b.
 317  *
 318  *     7:      Complete
 319  *     6:      Interrupt on successful transmission requested.
 320  *     5:      Jabber Error (TP Only, TX Reset required. )
 321  *     4:      Underrun (TX Reset required. )
 322  *     3:      Maximum Collisions.
 323  *     2:      TX Status Overflow.
 324  *     1-0:    Undefined.
 325  *
 326  */
 327 #define TXS_COMPLETE            0x80
 328 #define TXS_SUCCES_INTR_REQ             0x40
 329 #define TXS_JABBER              0x20
 330 #define TXS_UNDERRUN            0x10
 331 #define TXS_MAX_COLLISION       0x8
 332 #define TXS_STATUS_OVERFLOW     0x4
 333
 334 /*
 335  * Configuration control register.
 336  * Window 0/Port 04
 337  */
 338 /* Read */
 339 #define IS_AUI                          (1<<13)
 340 #define IS_BNC                          (1<<12)
 341 #define IS_UTP                          (1<<9)
 342 /* Write */
 343 #define ENABLE_DRQ_IRQ                  0x0001
 344 #define W0_P4_CMD_RESET_ADAPTER         0x4
 345 #define W0_P4_CMD_ENABLE_ADAPTER        0x1
 346 /*
 347  * Media type and status.
 348  * Window 4/Port 0A
 349  */
 350 #define ENABLE_UTP                      0xc0
 351 #define DISABLE_UTP                     0x0
 352
 353 /*
 354  * Resource control register
 355  */
 356
 357 #define SET_IRQ(i)      ( ((i)<<12) | 0xF00) /* set IRQ i */
 358
 359 /*
 360  * Receive status register
 361  */
 362
 363 #define RX_BYTES_MASK                   (unsigned short) (0x07ff)
 364 #define RX_ERROR        0x4000
 365 #define RX_INCOMPLETE   0x8000
 366
 367
 368 /*
 369  * Misc defines for various things.
 370  */
 371 #define ACTIVATE_ADAPTER_TO_CONFIG      0xff /* to the id_port */
 372 #define MFG_ID                          0x6d50 /* in EEPROM and W0 ADDR_CONFIG */
 373 #define PROD_ID                         0x9150
 374
 375 #define AUI                             0x1
 376 #define BNC                             0x2
 377 #define UTP                             0x4
 378
 379 #define RX_BYTES_MASK                   (unsigned short) (0x07ff)
 380
 381  /* EISA support */
 382 #define EP_EISA_START                   0x1000
 383 #define EP_EISA_W0                      0x0c80
 384
 385 #ifdef  INCLUDE_3C529
 386  /* MCA support */
 387 #define MCA_MOTHERBOARD_SETUP_REG       0x94
 388 #define MCA_ADAPTER_SETUP_REG           0x96
 389 #define MCA_MAX_SLOT_NR                 8
 390 #define MCA_POS_REG(n)                  (0x100+(n))
 391 #endif
 392
 393 /*
 394  * Local variables:
 395  *  c-basic-offset: 8
 396  * End:
 397  */