arch/common/hidd.pci/include/pci_hidd.h

   1 #ifndef HIDD_PCI_H
   2 #define HIDD_PCI_H
   3
   4 /*
   5     Copyright © 2003, The AROS Development Team. All rights reserved.
   6     $Id$
   7 */
   8 /*
   9  * 2008-03-30 T. Wiszkowski  Corrected typo and added InterruptStatus, CapabilitiesPresent attributes
  10  */
  11
  12 #ifndef EXEC_TYPES_H
  13 #include <exec/types.h>
  14 #endif
  15
  16 #ifndef HIDD_HIDD_H
  17 #include <hidd/hidd.h>
  18 #endif
  19
  20 #ifndef OOP_OOP_H
  21 #include <oop/oop.h>
  22 #endif
  23
  24 #ifndef UTILITY_HOOKS_H
  25 #include <utility/hooks.h>
  26 #endif
  27
  28 #ifndef UTILITY_TAGITEM_H
  29 #include <utility/tagitem.h>
  30 #endif
  31
  32 /* Base PCI class */
  33
  34 #define CLID_Hidd_PCI   "hidd.pci"
  35 #define IID_Hidd_PCI    "hidd.pci"
  36
  37 #define HiddPCIAttrBase __IHidd_PCI
  38
  39 #ifndef __OOP_NOATTRBASES__
  40 extern OOP_AttrBase HiddPCIAttrBase;
  41 #endif
  42
  43 /* PCI Class methods */
  44 enum
  45 {
  46     moHidd_PCI_AddHardwareDriver = 0,
  47     moHidd_PCI_EnumDevices,
  48     moHidd_PCI_RemHardwareDriver,
  49
  50     NUM_PCI_METHODS
  51 };
  52
  53 /* Tags for EnumDevices method */
  54 enum
  55 {
  56     tHidd_PCI_VendorID          = TAG_USER,
  57     tHidd_PCI_ProductID,
  58     tHidd_PCI_RevisionID,
  59     tHidd_PCI_Interface,
  60     tHidd_PCI_Class,
  61     tHidd_PCI_SubClass,
  62     tHidd_PCI_SubsystemVendorID,
  63     tHidd_PCI_SubsystemID
  64 };
  65
  66 struct pHidd_PCI_AddHardwareDriver
  67 {
  68     OOP_MethodID    mID;
  69     OOP_Class       *driverClass;
  70 };
  71
  72 struct pHidd_PCI_EnumDevices
  73 {
  74     OOP_MethodID    mID;
  75     struct Hook     *callback;
  76     struct TagItem  *requirements;
  77 };
  78
  79 struct pHidd_PCI_RemHardwareDriver
  80 {
  81     OOP_MethodID    mID;
  82     OOP_Class       *driverClass;
  83 };
  84
  85 /* PCI device class */
  86
  87 #define CLID_Hidd_PCIDevice     "hidd.pci.device"
  88 #define IID_Hidd_PCIDevice      "hidd.pci.device"
  89
  90 #define HiddPCIDeviceAttrBase   __IHidd_PCIDev
  91
  92 #ifndef __OOP_NOATTRBASES__
  93 extern OOP_AttrBase HiddPCIDeviceAttrBase;
  94 #endif
  95
  96 enum
  97 {
  98     moHidd_PCIDevice_ReadConfigByte,
  99     moHidd_PCIDevice_ReadConfigWord,
 100     moHidd_PCIDevice_ReadConfigLong,
 101     moHidd_PCIDevice_WriteConfigByte,
 102     moHidd_PCIDevice_WriteConfigWord,
 103     moHidd_PCIDevice_WriteConfigLong,
 104
 105     NUM_PCIDEVICE_METHODS
 106 };
 107
 108 enum
 109 {
 110     aoHidd_PCIDevice_Driver,    /* [I.G] Hardware PCI driver that handles this device */
 111     aoHidd_PCIDevice_Bus,       /* [I.G] Bus the device is on */
 112     aoHidd_PCIDevice_Dev,       /* [I.G] Device number */
 113     aoHidd_PCIDevice_Sub,       /* [I.G] Function number */
 114
 115     aoHidd_PCIDevice_VendorID,  /* [..G] VendorID of device as defined in PCI specs */
 116     aoHidd_PCIDevice_ProductID, /* [..G] ProductID */
 117     aoHidd_PCIDevice_RevisionID,/* [..G] RevisionID */
 118
 119     aoHidd_PCIDevice_Interface, /* [..G] */
 120     aoHidd_PCIDevice_Class,     /* [..G] */
 121     aoHidd_PCIDevice_SubClass,  /* [..G] */
 122
 123     aoHidd_PCIDevice_SubsystemVendorID, /* [..G] */
 124     aoHidd_PCIDevice_SubsystemID,       /* [..G] */
 125
 126     aoHidd_PCIDevice_INTLine,   /* [..G] */
 127     aoHidd_PCIDevice_IRQLine,   /* [..G] */
 128
 129     aoHidd_PCIDevice_RomBase,   /* [.SG] Location of ROM on the PCI bus (if ROM exists) */
 130     aoHidd_PCIDevice_RomSize,   /* [..G] Size of ROM area */
 131
 132     aoHidd_PCIDevice_Base0,     /* [.SG] Location of Memory Area 0 */
 133     aoHidd_PCIDevice_Size0,     /* [..G] Size of Memory Area 0 */
 134     aoHidd_PCIDevice_Type0,     /* [..G] Type of Memory Area 0 */
 135     aoHidd_PCIDevice_Base1,     /* [.SG] Ditto */
 136     aoHidd_PCIDevice_Size1,     /* [..G] */
 137     aoHidd_PCIDevice_Type1,     /* [..G] */
 138     aoHidd_PCIDevice_Base2,     /* [.SG] */
 139     aoHidd_PCIDevice_Size2,     /* [..G] */
 140     aoHidd_PCIDevice_Type2,     /* [..G] */
 141     aoHidd_PCIDevice_Base3,     /* [.SG] */
 142     aoHidd_PCIDevice_Size3,     /* [..G] */
 143     aoHidd_PCIDevice_Type3,     /* [..G] */
 144     aoHidd_PCIDevice_Base4,     /* [.SG] */
 145     aoHidd_PCIDevice_Size4,     /* [..G] */
 146     aoHidd_PCIDevice_Type4,     /* [..G] */
 147     aoHidd_PCIDevice_Base5,     /* [.SG] */
 148     aoHidd_PCIDevice_Size5,     /* [..G] */
 149     aoHidd_PCIDevice_Type5,     /* [..G] */
 150
 151     aoHidd_PCIDevice_isIO,      /* [.SG] Can device access IO space? */
 152     aoHidd_PCIDevice_isMEM,     /* [.SG] Can device access Mem space? */
 153     aoHidd_PCIDevice_isMaster,  /* [.SG] Can device work in BusMaster mode? */
 154     aoHidd_PCIDevice_paletteSnoop,  /* [.SG] Should VGA compatible card snoop the palette? */
 155
 156     aoHidd_PCIDevice_is66MHz,   /* [..G] Is device 66MHz capable? */
 157
 158     aoHidd_PCIDevice_ClassDesc,     /* [..G] String description of device Class */
 159     aoHidd_PCIDevice_SubClassDesc,  /* [..G] String description of device SubClass */
 160     aoHidd_PCIDevice_InterfaceDesc, /* [..G] String description of defice Interface */
 161
 162     aoHidd_PCIDevice_isBridge,  /* [..G] Is the device a PCI-PCI bridge? */
 163     aoHidd_PCIDevice_SubBus,    /* [..G] Bus number managed by bridge */
 164     aoHidd_PCIDevice_MemoryBase,/* [.SG] PCI bridge will forwart addresses from MemoryBase to */
 165     aoHidd_PCIDevice_MemoryLimit,/*[.SG] MemoryLimit through */
 166     aoHidd_PCIDevice_PrefetchableBase, /* [.SG] like above, regarding the prefetchable memory */
 167     aoHidd_PCIDevice_PrefetchableLimit,/* [.SG] */
 168     aoHidd_PCIDevice_IOBase,    /* [.SG] PCI bridge will forward IO accesses from IOBase to IOLimit */
 169     aoHidd_PCIDevice_IOLimit,   /* [.SG] */
 170     aoHidd_PCIDevice_ISAEnable, /* [.SG] Enable ISA-specific IO forwarding */
 171     aoHidd_PCIDevice_VGAEnable, /* [.SG] Enable VGA-specific IO/MEM forwarding regardless of limits */
 172
 173     aoHidd_PCIDevice_IRQStatus, /* [..G] Get current irq status (does device request irq?) */
 174     aoHidd_PCIDevice_CapabilitiesPresent,   /* [..G] Use this to check if PCI features extra capabilities (such as PM, MSI, PCI-X, PCI-E) */
 175
 176     num_Hidd_PCIDevice_Attrs
 177 };
 178
 179 #define aHidd_PCIDevice_Driver      (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Driver)
 180 #define aHidd_PCIDevice_Bus         (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Bus)
 181 #define aHidd_PCIDevice_Dev         (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Dev)
 182 #define aHidd_PCIDevice_Sub         (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Sub)
 183 #define aHidd_PCIDevice_VendorID    (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_VendorID)
 184 #define aHidd_PCIDevice_ProductID   (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_ProductID)
 185 #define aHidd_PCIDevice_RevisionID  (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_RevisionID)
 186 #define aHidd_PCIDevice_Interface   (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Interface)
 187 #define aHidd_PCIDevice_Class       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Class)
 188 #define aHidd_PCIDevice_SubClass    (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_SubClass)
 189 #define aHidd_PCIDevice_SubsystemVendorID   (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_SubsystemVendorID)
 190 #define aHidd_PCIDevice_SubsystemID (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_SubsystemID)
 191 #define aHidd_PCIDevice_INTLine     (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_INTLine)
 192 #define aHidd_PCIDevice_IRQLine     (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_IRQLine)
 193 #define aHidd_PCIDevice_RomBase     (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_RomBase)
 194 #define aHidd_PCIDevice_RomSize     (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_RomSize)
 195
 196 #define aHidd_PCIDevice_Base0       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Base0)
 197 #define aHidd_PCIDevice_Base1       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Base1)
 198 #define aHidd_PCIDevice_Base2       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Base2)
 199 #define aHidd_PCIDevice_Base3       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Base3)
 200 #define aHidd_PCIDevice_Base4       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Base4)
 201 #define aHidd_PCIDevice_Base5       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Base5)
 202
 203 #define aHidd_PCIDevice_Size0       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Size0)
 204 #define aHidd_PCIDevice_Size1       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Size1)
 205 #define aHidd_PCIDevice_Size2       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Size2)
 206 #define aHidd_PCIDevice_Size3       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Size3)
 207 #define aHidd_PCIDevice_Size4       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Size4)
 208 #define aHidd_PCIDevice_Size5       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Size5)
 209
 210 #define aHidd_PCIDevice_Type0       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Type0)
 211 #define aHidd_PCIDevice_Type1       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Type1)
 212 #define aHidd_PCIDevice_Type2       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Type2)
 213 #define aHidd_PCIDevice_Type3       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Type3)
 214 #define aHidd_PCIDevice_Type4       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Type4)
 215 #define aHidd_PCIDevice_Type5       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Type5)
 216
 217 #define aHidd_PCIDevice_isIO        (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_isIO)
 218 #define aHidd_PCIDevice_isMEM       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_isMEM)
 219 #define aHidd_PCIDevice_isMaster    (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_isMaster)
 220 #define aHidd_PCIDevice_paletteSnoop (HiddPCIDeviceAttrBase +aoHidd_PCIDevice_paletteSnoop)
 221 #define aHidd_PCIDevice_is66MHz     (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_is66MHz)
 222
 223 #define aHidd_PCIDevice_ClassDesc   (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_ClassDesc)
 224 #define aHidd_PCIDevice_SubClassDesc (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_SubClassDesc)
 225 #define aHidd_PCIDevice_InterfaceDesc (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_InterfaceDesc)
 226
 227 #define aHidd_PCIDevice_isBridge    (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_isBridge)
 228 #define aHidd_PCIDevice_SubBus      (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_SubBus)
 229 #define aHidd_PCIDevice_MemoryBase  (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_MemoryBase)
 230 #define aHidd_PCIDevice_MemoryLimit (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_MemoryLimit)
 231 #define aHidd_PCIDevice_PrefetchableBase (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_PrefetchableBase)
 232 #define aHidd_PCIDevice_PrefetchableLimit (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_PrefetchableLimit)
 233 #define aHidd_PCIDevice_IOBase      (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_IOBase)
 234 #define aHidd_PCIDevice_IOLimit     (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_IOLimit)
 235 #define aHidd_PCIDevice_ISAEnable   (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_ISAEnable)
 236 #define aHidd_PCIDevice_VGAEnable   (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_VGAEnable)
 237 #define aHidd_PCIDevice_IRQStatus   (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_IRQStatus)
 238 #define aHidd_PCIDevice_CapabilitiesPresent (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_CapabilitiesPresent)
 239
 240 #define IS_PCIDEV_ATTR(attr, idx) \
 241     (((idx) = (attr) - HiddPCIDeviceAttrBase) < num_Hidd_PCIDevice_Attrs)
 242
 243 /* Types of BaseAddresses */
 244 #define ADDRB_IO        0
 245 #define ADDRB_PREFETCH  3
 246
 247 #define ADDRF_IO        (1 << ADDRB_IO)
 248 #define ADDRF_PREFETCH  (1 << ADDRB_PREFETCH)
 249
 250 struct pHidd_PCIDevice_ReadConfigByte
 251 {
 252     OOP_MethodID    mID;
 253     UBYTE           reg;    /* Register number */
 254 };
 255
 256 struct pHidd_PCIDevice_ReadConfigWord
 257 {
 258     OOP_MethodID    mID;
 259     UBYTE           reg;    /* Register number */
 260 };
 261
 262 struct pHidd_PCIDevice_ReadConfigLong
 263 {
 264     OOP_MethodID    mID;
 265     UBYTE           reg;    /* Register number */
 266 };
 267
 268 struct pHidd_PCIDevice_WriteConfigByte
 269 {
 270     OOP_MethodID    mID;
 271     UBYTE           reg;    /* Register number */
 272     UBYTE           val;    /* Value to be written */
 273 };
 274
 275 struct pHidd_PCIDevice_WriteConfigWord
 276 {
 277     OOP_MethodID    mID;
 278     UBYTE           reg;    /* Register number */
 279     UWORD           val;    /* Value to be written */
 280 };
 281
 282
 283 struct pHidd_PCIDevice_WriteConfigLong
 284 {
 285     OOP_MethodID    mID;
 286     UBYTE           reg;    /* Register number */
 287     ULONG           val;    /* Value to be written */
 288 };
 289
 290
 291 /* PCI driver class */
 292
 293 #define CLID_Hidd_PCIDriver     "hidd.pci.driver"
 294 #define IID_Hidd_PCIDriver      "hidd.pci.driver"
 295
 296 #define HiddPCIDriverAttrBase   __IHidd_PCIDrv
 297
 298 enum
 299 {
 300     moHidd_PCIDriver_ReadConfigByte,
 301     moHidd_PCIDriver_ReadConfigWord,
 302     moHidd_PCIDriver_ReadConfigLong,
 303     moHidd_PCIDriver_WriteConfigByte,
 304     moHidd_PCIDriver_WriteConfigWord,
 305     moHidd_PCIDriver_WriteConfigLong,
 306     moHidd_PCIDriver_CPUtoPCI,
 307     moHidd_PCIDriver_PCItoCPU,
 308     moHidd_PCIDriver_MapPCI,
 309     moHidd_PCIDriver_UnmapPCI,
 310     moHidd_PCIDriver_AllocPCIMem,
 311     moHidd_PCIDriver_FreePCIMem,
 312
 313     NUM_PCIDRIVER_METHODS
 314 };
 315
 316 enum
 317 {
 318     aoHidd_PCIDriver_DirectBus,  /* [..G] DirectBus shows whether CPUtoPCI and PCItoCPU methods are usable */
 319
 320     num_Hidd_PCIDriver_Attrs
 321 };
 322
 323 #define aHidd_PCIDriver_DirectBus   (aoHidd_PCIDriver_DirectBus + HiddPCIDriverAttrBase)
 324
 325 #define IS_PCIDRV_ATTR(attr, idx) \
 326     (((idx) = (attr) - HiddPCIDriverAttrBase) < num_Hidd_PCIDriver_Attrs)
 327
 328
 329 struct pHidd_PCIDriver_ReadConfigByte
 330 {
 331     OOP_MethodID    mID;
 332     UBYTE           bus;    /* Bus number */
 333     UBYTE           dev;    /* Device number */
 334     UBYTE           sub;    /* Function number */
 335     UBYTE           reg;    /* Register number */
 336 };
 337
 338 struct pHidd_PCIDriver_ReadConfigWord
 339 {
 340     OOP_MethodID    mID;
 341     UBYTE           bus;    /* Bus number */
 342     UBYTE           dev;    /* Device number */
 343     UBYTE           sub;    /* Function number */
 344     UBYTE           reg;    /* Register number */
 345 };
 346
 347 struct pHidd_PCIDriver_ReadConfigLong
 348 {
 349     OOP_MethodID    mID;
 350     UBYTE           bus;    /* Bus number */
 351     UBYTE           dev;    /* Device number */
 352     UBYTE           sub;    /* Function number */
 353     UBYTE           reg;    /* Register number */
 354 };
 355
 356 struct pHidd_PCIDriver_WriteConfigByte
 357 {
 358     OOP_MethodID    mID;
 359     UBYTE           bus;    /* Bus number */
 360     UBYTE           dev;    /* Device number */
 361     UBYTE           sub;    /* Function number */
 362     UBYTE           reg;    /* Register number */
 363     UBYTE           val;    /* Value to be written */
 364 };
 365
 366 struct pHidd_PCIDriver_WriteConfigWord
 367 {
 368     OOP_MethodID    mID;
 369     UBYTE           bus;    /* Bus number */
 370     UBYTE           dev;    /* Device number */
 371     UBYTE           sub;    /* Function number */
 372     UBYTE           reg;    /* Register number */
 373     UWORD           val;    /* Value to be written */
 374 };
 375
 376
 377 struct pHidd_PCIDriver_WriteConfigLong
 378 {
 379     OOP_MethodID    mID;
 380     UBYTE           bus;    /* Bus number */
 381     UBYTE           dev;    /* Device number */
 382     UBYTE           sub;    /* Function number */
 383     UBYTE           reg;    /* Register number */
 384     ULONG           val;    /* Value to be written */
 385 };
 386
 387 struct pHidd_PCIDriver_CPUtoPCI
 388 {
 389     OOP_MethodID    mID;
 390     APTR            address;    /* CPU address to be translated */
 391 };
 392
 393 struct pHidd_PCIDriver_PCItoCPU
 394 {
 395     OOP_MethodID    mID;
 396     APTR            address;    /* PCI address to be translated */
 397 };
 398
 399 struct pHidd_PCIDriver_MapPCI
 400 {
 401     OOP_MethodID    mID;
 402     APTR            PCIAddress; /* Address on the PCIBus to be mapped to CPU address space */
 403     ULONG           Length;     /* Length of mapped area */
 404 };
 405
 406 struct pHidd_PCIDriver_UnmapPCI
 407 {
 408     OOP_MethodID    mID;
 409     APTR            CPUAddress; /* Address as seen by the CPU of the PCI address space to unmap */
 410     ULONG           Length;     /* Length of unmapped area */
 411 };
 412
 413 struct pHidd_PCIDriver_AllocPCIMem
 414 {
 415     OOP_MethodID    mID;
 416     ULONG           Size;
 417 };
 418
 419 struct pHidd_PCIDriver_FreePCIMem
 420 {
 421     OOP_MethodID    mID;
 422     APTR            Address;
 423 };
 424
 425 /* Prototypes for stubs */
 426 VOID HIDD_PCI_EnumDevices(OOP_Object *obj, struct Hook *hook, struct TagItem *requirements);
 427 VOID HIDD_PCI_AddHardwareDriver(OOP_Object *obj, OOP_Class *driver);
 428 APTR HIDD_PCIDriver_CPUtoPCI(OOP_Object *obj, APTR address);
 429 APTR HIDD_PCIDriver_PCItoCPU(OOP_Object *obj, APTR address);
 430 APTR HIDD_PCIDriver_MapPCI(OOP_Object *obj, APTR address, ULONG length);
 431 VOID HIDD_PCIDriver_UnmapPCI(OOP_Object *obj, APTR address, ULONG length);
 432 APTR HIDD_PCIDriver_AllocPCIMem(OOP_Object *obj, ULONG length);
 433 VOID HIDD_PCIDriver_FreePCIMem(OOP_Object *obj, APTR address);
 434
 435 #endif
 436