compiler/include/hardware/cpu/cpu_i386.h

   1 /*
   2     Copyright © 1995-2001, The AROS Development Team. All rights reserved.
   3     $Id$
   4
   5     Desc: i386 compatable Processor information.
   6     Lang: english
   7 */
   8
   9 #ifndef __AROS_CPU_i386_H__
  10 #define __AROS_CPU_i386_H__
  11
  12 #ifndef __AROS_CPU_H__
  13 #   include <hardware/cpu/cpu.h>
  14 #endif
  15
  16 struct i386_compat_intern       /* only applicable to i386 and compatible cpus.. one per cpu */
  17 {
  18     UBYTE           x86;                                        /*                      */
  19     UBYTE           x86_vendor;                                 /*                      */
  20     UBYTE           x86_model;                                  /*                      */
  21     ULONG           x86_mask;                                   /*                      */
  22     UWORD           x86_hard_math;                              /*                      */
  23     ULONG           x86_cpuid;                                  /*                      */
  24     ULONG           x86_capability;                             /*                      */
  25     ULONG           x86_reserved;                               /*                      */
  26     ULONG           x86_vendor_id;                              /*                      */
  27     ULONG           x86_vendor_id2;
  28     ULONG           x86_vendor_id3;
  29 };
  30
  31
  32 #define X86_CR4_MCE         0x0040                              /* Machine check enable */
  33 #define X86_CR4_PGE         0x0080                              /* enable global pages */
  34 #define X86_CR4_PCE         0x0100                              /* enable performance counters at ipl 3 */
  35
  36 /* Intel-defined CPU features,                  CPUID level 0x00000001 (edx), word 0 */
  37 #define X86_FEATURE_FPU         (0*32+ 0)                       /* Onboard FPU */
  38 #define X86_FEATURE_VME         (0*32+ 1)                       /* Virtual Mode Extensions */
  39 #define X86_FEATURE_DE          (0*32+ 2)                       /* Debugging Extensions */
  40 #define X86_FEATURE_PSE         0x0008                          /* Page size extensions */
  41 #define X86_FEATURE_TSC         0x0010                          /* Time stamp counter */
  42 #define X86_FEATURE_MSR         0x0020                          /* RDMSR/WRMSR */
  43 #define X86_FEATURE_PAE         0x0040                          /* Physical address extension */
  44 #define X86_FEATURE_MCE         0x0080                          /* Machine check exception */
  45 #define X86_FEATURE_CXS         0x0100                          /* cmpxchg8 available */
  46 #define X86_FEATURE_APIC        0x0200                          /* internal APIC */
  47 #define X86_FEATURE_10          0x0400
  48 #define X86_FEATURE_11          0x0800
  49 #define X86_FEATURE_MTRR        0x1000                          /* memory type registers */
  50 #define X86_FEATURE_PGE         0x2000                          /* Global page */
  51 #define X86_FEATURE_MCA         0x4000                          /* Machine Check Architecture */
  52 #define X86_FEATURE_CMOV        0x8000                          /* Cmov/fcomi */
  53
  54 /* Intel defined CPU features,                  CPUID level 0x00000001 (ecx), word 4 */
  55 #define X86_FEATURE_EST         (4*32+ 7)                           /* Enhanced SpeedStep */
  56
  57 /* AMD defined CPU features,                    CPUID level 0x80000001, word 1 */
  58 /* Don't duplicate feature flags which are redundant with Intel! */
  59 #define X86_FEATURE_SYSCALL     (1*32+11)                       /* SYSCALL/SYSRET */
  60 #define X86_FEATURE_MP          (1*32+19)                       /* MP Capable. */
  61 #define X86_FEATURE_MMXEXT      (1*32+22)                       /* AMD MMX extensions */
  62 #define X86_FEATURE_LM          (1*32+29)                       /* Long Mode (x86-64) */
  63 #define X86_FEATURE_3DNOWEXT    (1*32+30)                       /* AMD 3DNow! extensions */
  64
  65 #define X86_FEATURE_K6_MTRR     (3*32+ 1)                       /* AMD K6 nonstandard MTRRs */
  66 #define X86_FEATURE_CYRIX_ARR   (3*32+ 2)                       /* Cyrix ARRs (= MTRRs) */
  67 #define X86_FEATURE_CENTAUR_MCR (3*32+ 3)                       /* Centaur MCRs (= MTRRs) */
  68
  69 /* cpu specific tuning types */
  70 #define X86_FEATURE_K8          (3*32+ 4)                       /* Opteron, Athlon64 */
  71 #define X86_FEATURE_K7          (3*32+ 5)                       /* Athlon */
  72 #define X86_FEATURE_P3          (3*32+ 6)                       /* P3 */
  73 #define X86_FEATURE_P4          (3*32+ 7)                       /* P4 */
  74
  75 /* VIA/Cyrix/Centaur defined CPU features,      CPUID level 0xC0000001, word 5 */
  76 #define X86_FEATURE_XSTORE  (5*32+ 2)                           /* on-CPU RNG present (xstore insn) */
  77
  78 /* symbolic names for some interesting MSRs */
  79 /* Intel defined MSRs. */
  80 #define MSR_IA32_P5_MC_ADDR         0
  81 #define MSR_IA32_P5_MC_TYPE                 1
  82 #define MSR_IA32_PLATFORM_ID            0x17
  83 #define MSR_IA32_EBL_CR_POWERON         0x2a
  84
  85 #define MSR_IA32_APICBASE                   0x1b
  86 #define MSR_IA32_APICBASE_BSP           (1<<8)
  87 #define MSR_IA32_APICBASE_ENABLE        (1<<11)
  88 #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
  89
  90 #define MSR_IA32_UCODE_WRITE            0x79
  91 #define MSR_IA32_UCODE_REV                  0x8b
  92
  93 #define MSR_IA32_PERFCTR0                   0xc1
  94 #define MSR_IA32_PERFCTR1                   0xc2
  95
  96 #define MSR_IA32_BBL_CR_CTL                 0x119
  97
  98 #define MSR_IA32_MCG_CAP                    0x179
  99 #define MSR_IA32_MCG_STATUS                 0x17a
 100 #define MSR_IA32_MCG_CTL                    0x17b
 101
 102 #define MSR_IA32_EVNTSEL0                   0x186
 103 #define MSR_IA32_EVNTSEL1                   0x187
 104
 105 #define MSR_IA32_DEBUGCTLMSR            0x1d9
 106 #define MSR_IA32_LASTBRANCHFROMIP       0x1db
 107 #define MSR_IA32_LASTBRANCHTOIP         0x1dc
 108 #define MSR_IA32_LASTINTFROMIP          0x1dd
 109 #define MSR_IA32_LASTINTTOIP            0x1de
 110
 111 #define MSR_IA32_MC0_CTL                    0x400
 112 #define MSR_IA32_MC0_STATUS                 0x401
 113 #define MSR_IA32_MC0_ADDR                   0x402
 114 #define MSR_IA32_MC0_MISC                   0x403
 115
 116 /* AMD Defined MSRs */
 117 #define MSR_K6_EFER                             0xC0000080
 118 #define MSR_K6_STAR                             0xC0000081
 119 #define MSR_K6_WHCR                             0xC0000082
 120 #define MSR_K6_UWCCR                        0xC0000085
 121 #define MSR_K6_PSOR                             0xC0000087
 122 #define MSR_K6_PFIR                             0xC0000088
 123
 124 #define MSR_K7_EVNTSEL0                     0xC0010000
 125 #define MSR_K7_PERFCTR0                     0xC0010004
 126 //                                  0xC0010010
 127 #define MSR_K7_HWCR                             0xC0010015
 128 //                                  0XC001001B
 129
 130 /* Centaur-Hauls/IDT defined MSRs. */
 131 #define MSR_IDT_FCR1                        0x107
 132 #define MSR_IDT_FCR2                        0x108
 133 #define MSR_IDT_FCR3                        0x109
 134 #define MSR_IDT_FCR4                        0x10a
 135
 136 #define MSR_IDT_MCR0                        0x110
 137 #define MSR_IDT_MCR1                        0x111
 138 #define MSR_IDT_MCR2                        0x112
 139 #define MSR_IDT_MCR3                        0x113
 140 #define MSR_IDT_MCR4                        0x114
 141 #define MSR_IDT_MCR5                        0x115
 142 #define MSR_IDT_MCR6                        0x116
 143 #define MSR_IDT_MCR7                        0x117
 144 #define MSR_IDT_MCR_CTRL                    0x120
 145
 146 /* VIA Cyrix defined MSRs*/
 147 #define MSR_VIA_FCR                 0x1107
 148 #define MSR_VIA_LONGHAUL            0x110a
 149 #define MSR_VIA_RNG                 0x110b
 150 #define MSR_VIA_BCR2                0x1147
 151
 152 #endif /* __AROS_CPU_i386_H__ */