compiler/include/hardware/cpu/cpu_mpspec.h

   1 /*
   2     Copyright © 1995-2001, The AROS Development Team. All rights reserved.
   3     $Id$
   4
   5     Desc: Structure definitions for SMP machines following the Intel Multiprocessing Specification 1.1 and 1.4.
   6     Lang: english
   7 */
   8
   9 #ifndef __AROS_CPU_MPSPEC_H__
  10 #define __AROS_CPU_MPSPEC_H__
  11
  12 #ifndef __AROS_CPU_H__
  13 #   include <cpu/cpu.h>
  14 #endif
  15
  16 /* ADJUSTABLE SETTINGS --------------- */
  17
  18 #define MAX_MPC_ENTRY       1024
  19
  20 /*  a maximum of 16 APICs with the current APIC ID architecture. */
  21
  22 #define MAX_APICS           16
  23
  24 /* ----------------------------------- */
  25
  26 /*
  27     This tag identifies where the SMP configuration
  28     information is.
  29 */
  30
  31 #define SMP_MAGIC_IDENT     (('_'<<24)|('P'<<16)|('M'<<8)|'_')
  32
  33 struct intel_mp_confblock
  34 {
  35         char                    mpcf_signature[4];                       /* "_MP_"                       */
  36         unsigned int            mpcf_physptr;                            /* Configuration table address  */
  37         unsigned char           mpcf_length;                             /* Our length (paragraphs)      */
  38         unsigned char           mpcf_specification;                      /* Specification version        */
  39         unsigned char           mpcf_checksum;                           /* Checksum (makes sum 0)       */
  40         unsigned char           mpcf_feature1;                           /* Standard or configuration ?  */
  41         unsigned char           mpcf_feature2;                           /* Bit7 set for IMCR|PIC        */
  42         unsigned char           mpcf_feature3;                           /* Unused (0)                   */
  43         unsigned char           mpcf_feature4;                           /* Unused (0)                   */
  44         unsigned char           mpcf_feature5;                           /* Unused (0)                   */
  45 };
  46
  47 struct mp_config_table
  48 {
  49         char                    mpc_signature[4];
  50         unsigned short          mpc_length;                             /* Size of table                */
  51         char                    mpc_spec;                               /* 0x01                         */
  52         char                    mpc_checksum;
  53         char                    mpc_oem[8];
  54         char                    mpc_productid[12];
  55         unsigned int            mpc_oemptr;                             /* 0 if not present             */
  56         unsigned short          mpc_oemsize;                            /* 0 if not present             */
  57         unsigned short          mpc_oemcount;
  58         unsigned int            mpc_lapic;                              /* APIC address                 */
  59         unsigned int            reserved;
  60 };
  61
  62 #define MPC_SIGNATURE       "PCMP"
  63
  64 /* Followed by entries */
  65
  66 #define MP_PROCESSOR        0
  67 #define MP_BUS              1
  68 #define MP_IOAPIC           2
  69 #define MP_INTSRC           3
  70 #define MP_LINTSRC          4
  71 #define MP_TRANSLATION      192                                     /* Used by IBM NUMA-Q to describe node locality */
  72
  73 struct mpc_config_processor
  74 {
  75         unsigned char           mpc_type;
  76         unsigned char           mpc_apicid;                             /* Local APIC number */
  77         unsigned char           mpc_apicver;                            /* Its versions */
  78         unsigned char           mpc_cpuflag;
  79         unsigned int            mpc_cpufeature;
  80         unsigned int            mpc_featureflag;                        /* CPUID feature value */
  81         unsigned int            mpc_reserved[2];
  82 };
  83
  84 #define CPU_ENABLED         1                                       /* Processor is available */
  85 #define CPU_BOOTPROCESSOR       2                                       /* Processor is the BP */
  86
  87 #define CPU_STEPPING_MASK   0x0F
  88 #define CPU_MODEL_MASK      0xF0
  89 #define CPU_FAMILY_MASK     0xF00
  90
  91 struct mpc_config_bus
  92 {
  93         unsigned char           mpc_type;
  94         unsigned char           mpc_busid;
  95         unsigned char           mpc_bustype[6] __attribute((packed));
  96 };
  97
  98 /* List of Bus Type string values, Intel MP Spec. */
  99
 100 #define BUSTYPE_EISA        "EISA"
 101 #define BUSTYPE_ISA         "ISA"
 102 #define BUSTYPE_INTERN      "INTERN"                                /* Internal BUS */
 103 #define BUSTYPE_MCA         "MCA"
 104 #define BUSTYPE_VL          "VL"                                    /* Local bus */
 105 #define BUSTYPE_PCI         "PCI"
 106 #define BUSTYPE_PCMCIA      "PCMCIA"
 107 #define BUSTYPE_CBUS        "CBUS"
 108 #define BUSTYPE_CBUSII      "CBUSII"
 109 #define BUSTYPE_FUTURE      "FUTURE"
 110 #define BUSTYPE_MBI         "MBI"
 111 #define BUSTYPE_MBII        "MBII"
 112 #define BUSTYPE_MPI         "MPI"
 113 #define BUSTYPE_MPSA        "MPSA"
 114 #define BUSTYPE_NUBUS       "NUBUS"
 115 #define BUSTYPE_TC          "TC"
 116 #define BUSTYPE_VME         "VME"
 117 #define BUSTYPE_XPRESS      "XPRESS"
 118 #define BUSTYPE_NEC98       "NEC98"
 119
 120 struct mpc_config_ioapic
 121 {
 122         unsigned char           mpc_type;
 123         unsigned char           mpc_apicid;
 124         unsigned char           mpc_apicver;
 125         unsigned char           mpc_flags;
 126         unsigned int            mpc_apicaddr;
 127 };
 128
 129 #define MPC_APIC_USABLE         0x01
 130
 131 struct mpc_config_intsrc
 132 {
 133         unsigned char           mpc_type;
 134         unsigned char           mpc_irqtype;
 135         unsigned short          mpc_irqflag;
 136         unsigned char           mpc_srcbus;
 137         unsigned char           mpc_srcbusirq;
 138         unsigned char           mpc_dstapic;
 139         unsigned char           mpc_dstirq;
 140 };
 141
 142 enum mp_irq_source_types {
 143         mp_INT      = 0,
 144         mp_NMI      = 1,
 145         mp_SMI      = 2,
 146         mp_ExtINT   = 3
 147 };
 148
 149 #define MP_IRQDIR_DEFAULT       0
 150 #define MP_IRQDIR_HIGH          1
 151 #define MP_IRQDIR_LOW           3
 152
 153
 154 struct mpc_config_lintsrc
 155 {
 156         unsigned char           mpc_type;
 157         unsigned char           mpc_irqtype;
 158         unsigned short          mpc_irqflag;
 159         unsigned char           mpc_srcbusid;
 160         unsigned char           mpc_srcbusirq;
 161         unsigned char           mpc_destapic;
 162         unsigned char           mpc_destapiclint;
 163 };
 164
 165 #define MP_APIC_ALL     0xFF
 166
 167 struct mp_config_oemtable
 168 {
 169         char                    oem_signature[4];
 170         unsigned short          oem_length;                                 /* Size of table */
 171         char                    oem_rev;                                    /* 0x01 */
 172         char                    oem_checksum;
 173         char                    mpc_oem[8];
 174 };
 175
 176 #define MPC_OEM_SIGNATURE "_OEM"
 177
 178 struct mpc_config_translation
 179 {
 180     unsigned char           mpc_type;
 181     unsigned char           trans_len;
 182     unsigned char           trans_type;
 183     unsigned char           trans_quad;
 184     unsigned char           trans_global;
 185     unsigned char           trans_local;
 186     unsigned short          trans_reserved;
 187 };
 188
 189 #define MAX_IRQ_SOURCES 256
 190 #define MAX_MP_BUSSES 32
 191
 192 /*
 193     Default configurations
 194
 195     1   2 CPU ISA 82489DX
 196     2   2 CPU EISA 82489DX neither IRQ 0 timer nor IRQ 13 DMA chaining
 197     3   2 CPU EISA 82489DX
 198     4   2 CPU MCA 82489DX
 199     5   2 CPU ISA+PCI
 200     6   2 CPU EISA+PCI
 201     7   2 CPU MCA+PCI
 202 */
 203
 204 enum mp_bustype {
 205         MP_BUS_ISA = 1,
 206         MP_BUS_EISA,
 207         MP_BUS_PCI,
 208         MP_BUS_MCA,
 209         MP_BUS_NEC98
 210 };
 211
 212 #endif  /* __AROS_CPU_MPSPEC_H__ */