?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Updated PCI IDs to latest snapshot.
[tangerine.git] / workbench / devs / networks / e1000 / e1000_82541.c
blobc098daf839163e4a2285a0ab9c04c6da31425fe7
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /* e1000_82541
30 * e1000_82547
31 * e1000_82541_rev_2
32 * e1000_82547_rev_2
33 */
34
35 #include "e1000_api.h"
36 #include "e1000_82541.h"
37
38 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw);
39 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw);
40 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw);
41 static s32 e1000_reset_hw_82541(struct e1000_hw *hw);
42 static s32 e1000_init_hw_82541(struct e1000_hw *hw);
43 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
44 u16 *duplex);
45 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw);
46 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw);
47 static s32 e1000_check_for_link_82541(struct e1000_hw *hw);
48 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw);
49 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw,
50 bool active);
51 static s32 e1000_setup_led_82541(struct e1000_hw *hw);
52 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw);
53 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw);
54 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
55 bool link_up);
56 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw);
57 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw);
58
59 static const u16 e1000_igp_cable_length_table[] =
60 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
61 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
62 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
63 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
64 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
65 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
66 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
67 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
68 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE \
69 (sizeof(e1000_igp_cable_length_table) / \
70 sizeof(e1000_igp_cable_length_table[0]))
71
72 struct e1000_dev_spec_82541 {
73 e1000_dsp_config dsp_config;
74 e1000_ffe_config ffe_config;
75 u16 spd_default;
76 bool phy_init_script;
77 };
78
79 /**
80 * e1000_init_phy_params_82541 - Init PHY func ptrs.
81 * @hw: pointer to the HW structure
82 *
83 * This is a function pointer entry point called by the api module.
84 **/
85 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw)
86 {
87 struct e1000_phy_info *phy = &hw->phy;
88 s32 ret_val = E1000_SUCCESS;
89
90 DEBUGFUNC("e1000_init_phy_params_82541");
91
92 phy->addr = 1;
93 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
94 phy->reset_delay_us = 10000;
95 phy->type = e1000_phy_igp;
96
97 /* Function Pointers */
98 phy->ops.check_polarity = e1000_check_polarity_igp;
99 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
100 phy->ops.get_cable_length = e1000_get_cable_length_igp_82541;
101 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
102 phy->ops.get_info = e1000_get_phy_info_igp;
103 phy->ops.read_reg = e1000_read_phy_reg_igp;
104 phy->ops.reset = e1000_phy_hw_reset_82541;
105 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541;
106 phy->ops.write_reg = e1000_write_phy_reg_igp;
107 phy->ops.power_up = e1000_power_up_phy_copper;
108 phy->ops.power_down = e1000_power_down_phy_copper_82541;
109
110 ret_val = e1000_get_phy_id(hw);
111 if (ret_val)
112 goto out;
113
114 /* Verify phy id */
115 if (phy->id != IGP01E1000_I_PHY_ID) {
116 ret_val = -E1000_ERR_PHY;
117 goto out;
118 }
119
120 out:
121 return ret_val;
122 }
123
124 /**
125 * e1000_init_nvm_params_82541 - Init NVM func ptrs.
126 * @hw: pointer to the HW structure
127 *
128 * This is a function pointer entry point called by the api module.
129 **/
130 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw)
131 {
132 struct e1000_nvm_info *nvm = &hw->nvm;
133 s32 ret_val = E1000_SUCCESS;
134 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
135 u16 size;
136
137 DEBUGFUNC("e1000_init_nvm_params_82541");
138
139 switch (nvm->override) {
140 case e1000_nvm_override_spi_large:
141 nvm->type = e1000_nvm_eeprom_spi;
142 eecd |= E1000_EECD_ADDR_BITS;
143 break;
144 case e1000_nvm_override_spi_small:
145 nvm->type = e1000_nvm_eeprom_spi;
146 eecd &= ~E1000_EECD_ADDR_BITS;
147 break;
148 case e1000_nvm_override_microwire_large:
149 nvm->type = e1000_nvm_eeprom_microwire;
150 eecd |= E1000_EECD_SIZE;
151 break;
152 case e1000_nvm_override_microwire_small:
153 nvm->type = e1000_nvm_eeprom_microwire;
154 eecd &= ~E1000_EECD_SIZE;
155 break;
156 default:
157 nvm->type = eecd & E1000_EECD_TYPE
158 ? e1000_nvm_eeprom_spi
159 : e1000_nvm_eeprom_microwire;
160 break;
161 }
162
163 if (nvm->type == e1000_nvm_eeprom_spi) {
164 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS)
165 ? 16 : 8;
166 nvm->delay_usec = 1;
167 nvm->opcode_bits = 8;
168 nvm->page_size = (eecd & E1000_EECD_ADDR_BITS)
169 ? 32 : 8;
170
171 /* Function Pointers */
172 nvm->ops.acquire = e1000_acquire_nvm_generic;
173 nvm->ops.read = e1000_read_nvm_spi;
174 nvm->ops.release = e1000_release_nvm_generic;
175 nvm->ops.update = e1000_update_nvm_checksum_generic;
176 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
177 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
178 nvm->ops.write = e1000_write_nvm_spi;
179
180 /*
181 * nvm->word_size must be discovered after the pointers
182 * are set so we can verify the size from the nvm image
183 * itself. Temporarily set it to a dummy value so the
184 * read will work.
185 */
186 nvm->word_size = 64;
187 ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size);
188 if (ret_val)
189 goto out;
190 size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT;
191 /*
192 * if size != 0, it can be added to a constant and become
193 * the left-shift value to set the word_size. Otherwise,
194 * word_size stays at 64.
195 */
196 if (size) {
197 size += NVM_WORD_SIZE_BASE_SHIFT_82541;
198 nvm->word_size = 1 << size;
199 }
200 } else {
201 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS)
202 ? 8 : 6;
203 nvm->delay_usec = 50;
204 nvm->opcode_bits = 3;
205 nvm->word_size = (eecd & E1000_EECD_ADDR_BITS)
206 ? 256 : 64;
207
208 /* Function Pointers */
209 nvm->ops.acquire = e1000_acquire_nvm_generic;
210 nvm->ops.read = e1000_read_nvm_microwire;
211 nvm->ops.release = e1000_release_nvm_generic;
212 nvm->ops.update = e1000_update_nvm_checksum_generic;
213 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
214 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
215 nvm->ops.write = e1000_write_nvm_microwire;
216 }
217
218 out:
219 return ret_val;
220 }
221
222 /**
223 * e1000_init_mac_params_82541 - Init MAC func ptrs.
224 * @hw: pointer to the HW structure
225 *
226 * This is a function pointer entry point called by the api module.
227 **/
228 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw)
229 {
230 struct e1000_mac_info *mac = &hw->mac;
231 s32 ret_val;
232
233 DEBUGFUNC("e1000_init_mac_params_82541");
234
235 /* Set media type */
236 hw->phy.media_type = e1000_media_type_copper;
237 /* Set mta register count */
238 mac->mta_reg_count = 128;
239 /* Set rar entry count */
240 mac->rar_entry_count = E1000_RAR_ENTRIES;
241 /* Set if part includes ASF firmware */
242 mac->asf_firmware_present = TRUE;
243
244 /* Function Pointers */
245
246 /* bus type/speed/width */
247 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
248 /* reset */
249 mac->ops.reset_hw = e1000_reset_hw_82541;
250 /* hw initialization */
251 mac->ops.init_hw = e1000_init_hw_82541;
252 /* link setup */
253 mac->ops.setup_link = e1000_setup_link_generic;
254 /* physical interface link setup */
255 mac->ops.setup_physical_interface = e1000_setup_copper_link_82541;
256 /* check for link */
257 mac->ops.check_for_link = e1000_check_for_link_82541;
258 /* link info */
259 mac->ops.get_link_up_info = e1000_get_link_up_info_82541;
260 /* multicast address update */
261 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
262 /* writing VFTA */
263 mac->ops.write_vfta = e1000_write_vfta_generic;
264 /* clearing VFTA */
265 mac->ops.clear_vfta = e1000_clear_vfta_generic;
266 /* setting MTA */
267 mac->ops.mta_set = e1000_mta_set_generic;
268 /* setup LED */
269 mac->ops.setup_led = e1000_setup_led_82541;
270 /* cleanup LED */
271 mac->ops.cleanup_led = e1000_cleanup_led_82541;
272 /* turn on/off LED */
273 mac->ops.led_on = e1000_led_on_generic;
274 mac->ops.led_off = e1000_led_off_generic;
275 /* remove device */
276 mac->ops.remove_device = e1000_remove_device_generic;
277 /* clear hardware counters */
278 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82541;
279
280 hw->dev_spec_size = sizeof(struct e1000_dev_spec_82541);
281
282 /* Device-specific structure allocation */
283 ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size);
284
285 return ret_val;
286 }
287
288 /**
289 * e1000_init_function_pointers_82541 - Init func ptrs.
290 * @hw: pointer to the HW structure
291 *
292 * The only function explicitly called by the api module to initialize
293 * all function pointers and parameters.
294 **/
295 void e1000_init_function_pointers_82541(struct e1000_hw *hw)
296 {
297 DEBUGFUNC("e1000_init_function_pointers_82541");
298
299 hw->mac.ops.init_params = e1000_init_mac_params_82541;
300 hw->nvm.ops.init_params = e1000_init_nvm_params_82541;
301 hw->phy.ops.init_params = e1000_init_phy_params_82541;
302 }
303
304 /**
305 * e1000_reset_hw_82541 - Reset hardware
306 * @hw: pointer to the HW structure
307 *
308 * This resets the hardware into a known state. This is a
309 * function pointer entry point called by the api module.
310 **/
311 static s32 e1000_reset_hw_82541(struct e1000_hw *hw)
312 {
313 u32 ledctl, ctrl, icr, manc;
314
315 DEBUGFUNC("e1000_reset_hw_82541");
316
317 DEBUGOUT("Masking off all interrupts\n");
318 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
319
320 E1000_WRITE_REG(hw, E1000_RCTL, 0);
321 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
322 E1000_WRITE_FLUSH(hw);
323
324 /*
325 * Delay to allow any outstanding PCI transactions to complete
326 * before resetting the device.
327 */
328 msec_delay(10);
329
330 ctrl = E1000_READ_REG(hw, E1000_CTRL);
331
332 /* Must reset the Phy before resetting the MAC */
333 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
334 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST));
335 msec_delay(5);
336 }
337
338 DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n");
339 switch (hw->mac.type) {
340 case e1000_82541:
341 case e1000_82541_rev_2:
342 /*
343 * These controllers can't ack the 64-bit write when
344 * issuing the reset, so we use IO-mapping as a
345 * workaround to issue the reset.
346 */
347 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
348 break;
349 default:
350 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
351 break;
352 }
353
354 /* Wait for NVM reload */
355 msec_delay(20);
356
357 /* Disable HW ARPs on ASF enabled adapters */
358 manc = E1000_READ_REG(hw, E1000_MANC);
359 manc &= ~E1000_MANC_ARP_EN;
360 E1000_WRITE_REG(hw, E1000_MANC, manc);
361
362 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
363 e1000_phy_init_script_82541(hw);
364
365 /* Configure activity LED after Phy reset */
366 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
367 ledctl &= IGP_ACTIVITY_LED_MASK;
368 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
369 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
370 }
371
372 /* Once again, mask the interrupts */
373 DEBUGOUT("Masking off all interrupts\n");
374 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
375
376 /* Clear any pending interrupt events. */
377 icr = E1000_READ_REG(hw, E1000_ICR);
378
379 return E1000_SUCCESS;
380 }
381
382 /**
383 * e1000_init_hw_82541 - Initialize hardware
384 * @hw: pointer to the HW structure
385 *
386 * This inits the hardware readying it for operation. This is a
387 * function pointer entry point called by the api module.
388 **/
389 static s32 e1000_init_hw_82541(struct e1000_hw *hw)
390 {
391 struct e1000_mac_info *mac = &hw->mac;
392 u32 i, txdctl;
393 s32 ret_val;
394
395 DEBUGFUNC("e1000_init_hw_82541");
396
397 /* Initialize identification LED */
398 ret_val = e1000_id_led_init_generic(hw);
399 if (ret_val) {
400 DEBUGOUT("Error initializing identification LED\n");
401 /* This is not fatal and we should not stop init due to this */
402 }
403
404 /* Disabling VLAN filtering */
405 DEBUGOUT("Initializing the IEEE VLAN\n");
406 mac->ops.clear_vfta(hw);
407
408 /* Setup the receive address. */
409 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
410
411 /* Zero out the Multicast HASH table */
412 DEBUGOUT("Zeroing the MTA\n");
413 for (i = 0; i < mac->mta_reg_count; i++) {
414 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
415 /*
416 * Avoid back to back register writes by adding the register
417 * read (flush). This is to protect against some strange
418 * bridge configurations that may issue Memory Write Block
419 * (MWB) to our register space.
420 */
421 E1000_WRITE_FLUSH(hw);
422 }
423
424 /* Setup link and flow control */
425 ret_val = mac->ops.setup_link(hw);
426
427 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
428 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
429 E1000_TXDCTL_FULL_TX_DESC_WB;
430 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
431
432 /*
433 * Clear all of the statistics registers (clear on read). It is
434 * important that we do this after we have tried to establish link
435 * because the symbol error count will increment wildly if there
436 * is no link.
437 */
438 e1000_clear_hw_cntrs_82541(hw);
439
440 return ret_val;
441 }
442
443 /**
444 * e1000_get_link_up_info_82541 - Report speed and duplex
445 * @hw: pointer to the HW structure
446 * @speed: pointer to speed buffer
447 * @duplex: pointer to duplex buffer
448 *
449 * Retrieve the current speed and duplex configuration.
450 * This is a function pointer entry point called by the api module.
451 **/
452 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
453 u16 *duplex)
454 {
455 struct e1000_phy_info *phy = &hw->phy;
456 s32 ret_val;
457 u16 data;
458
459 DEBUGFUNC("e1000_get_link_up_info_82541");
460
461 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
462 if (ret_val)
463 goto out;
464
465 if (!phy->speed_downgraded)
466 goto out;
467
468 /*
469 * IGP01 PHY may advertise full duplex operation after speed
470 * downgrade even if it is operating at half duplex.
471 * Here we set the duplex settings to match the duplex in the
472 * link partner's capabilities.
473 */
474 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data);
475 if (ret_val)
476 goto out;
477
478 if (!(data & NWAY_ER_LP_NWAY_CAPS)) {
479 *duplex = HALF_DUPLEX;
480 } else {
481 ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data);
482 if (ret_val)
483 goto out;
484
485 if (*speed == SPEED_100) {
486 if (!(data & NWAY_LPAR_100TX_FD_CAPS))
487 *duplex = HALF_DUPLEX;
488 } else if (*speed == SPEED_10) {
489 if (!(data & NWAY_LPAR_10T_FD_CAPS))
490 *duplex = HALF_DUPLEX;
491 }
492 }
493
494 out:
495 return ret_val;
496 }
497
498 /**
499 * e1000_phy_hw_reset_82541 - PHY hardware reset
500 * @hw: pointer to the HW structure
501 *
502 * Verify the reset block is not blocking us from resetting. Acquire
503 * semaphore (if necessary) and read/set/write the device control reset
504 * bit in the PHY. Wait the appropriate delay time for the device to
505 * reset and release the semaphore (if necessary).
506 * This is a function pointer entry point called by the api module.
507 **/
508 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw)
509 {
510 s32 ret_val;
511 u32 ledctl;
512
513 DEBUGFUNC("e1000_phy_hw_reset_82541");
514
515 ret_val = e1000_phy_hw_reset_generic(hw);
516 if (ret_val)
517 goto out;
518
519 e1000_phy_init_script_82541(hw);
520
521 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
522 /* Configure activity LED after PHY reset */
523 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
524 ledctl &= IGP_ACTIVITY_LED_MASK;
525 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
526 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
527 }
528
529 out:
530 return ret_val;
531 }
532
533 /**
534 * e1000_setup_copper_link_82541 - Configure copper link settings
535 * @hw: pointer to the HW structure
536 *
537 * Calls the appropriate function to configure the link for auto-neg or forced
538 * speed and duplex. Then we check for link, once link is established calls
539 * to configure collision distance and flow control are called. If link is
540 * not established, we return -E1000_ERR_PHY (-2). This is a function
541 * pointer entry point called by the api module.
542 **/
543 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw)
544 {
545 struct e1000_phy_info *phy = &hw->phy;
546 struct e1000_dev_spec_82541 *dev_spec;
547 s32 ret_val;
548 u32 ctrl, ledctl;
549
550 DEBUGFUNC("e1000_setup_copper_link_82541");
551
552 ctrl = E1000_READ_REG(hw, E1000_CTRL);
553 ctrl |= E1000_CTRL_SLU;
554 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
555 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
556
557 hw->phy.reset_disable = FALSE;
558
559 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec;
560
561 /* Earlier revs of the IGP phy require us to force MDI. */
562 if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) {
563 dev_spec->dsp_config = e1000_dsp_config_disabled;
564 phy->mdix = 1;
565 } else {
566 dev_spec->dsp_config = e1000_dsp_config_enabled;
567 }
568
569 ret_val = e1000_copper_link_setup_igp(hw);
570 if (ret_val)
571 goto out;
572
573 if (hw->mac.autoneg) {
574 if (dev_spec->ffe_config == e1000_ffe_config_active)
575 dev_spec->ffe_config = e1000_ffe_config_enabled;
576 }
577
578 /* Configure activity LED after Phy reset */
579 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
580 ledctl &= IGP_ACTIVITY_LED_MASK;
581 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
582 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
583
584 ret_val = e1000_setup_copper_link_generic(hw);
585
586 out:
587 return ret_val;
588 }
589
590 /**
591 * e1000_check_for_link_82541 - Check/Store link connection
592 * @hw: pointer to the HW structure
593 *
594 * This checks the link condition of the adapter and stores the
595 * results in the hw->mac structure. This is a function pointer entry
596 * point called by the api module.
597 **/
598 static s32 e1000_check_for_link_82541(struct e1000_hw *hw)
599 {
600 struct e1000_mac_info *mac = &hw->mac;
601 s32 ret_val;
602 bool link;
603
604 DEBUGFUNC("e1000_check_for_link_82541");
605
606 /*
607 * We only want to go out to the PHY registers to see if Auto-Neg
608 * has completed and/or if our link status has changed. The
609 * get_link_status flag is set upon receiving a Link Status
610 * Change or Rx Sequence Error interrupt.
611 */
612 if (!mac->get_link_status) {
613 ret_val = E1000_SUCCESS;
614 goto out;
615 }
616
617 /*
618 * First we want to see if the MII Status Register reports
619 * link. If so, then we want to get the current speed/duplex
620 * of the PHY.
621 */
622 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
623 if (ret_val)
624 goto out;
625
626 if (!link) {
627 ret_val = e1000_config_dsp_after_link_change_82541(hw, FALSE);
628 goto out; /* No link detected */
629 }
630
631 mac->get_link_status = FALSE;
632
633 /*
634 * Check if there was DownShift, must be checked
635 * immediately after link-up
636 */
637 e1000_check_downshift_generic(hw);
638
639 /*
640 * If we are forcing speed/duplex, then we simply return since
641 * we have already determined whether we have link or not.
642 */
643 if (!mac->autoneg) {
644 ret_val = -E1000_ERR_CONFIG;
645 goto out;
646 }
647
648 ret_val = e1000_config_dsp_after_link_change_82541(hw, TRUE);
649
650 /*
651 * Auto-Neg is enabled. Auto Speed Detection takes care
652 * of MAC speed/duplex configuration. So we only need to
653 * configure Collision Distance in the MAC.
654 */
655 e1000_config_collision_dist_generic(hw);
656
657 /*
658 * Configure Flow Control now that Auto-Neg has completed.
659 * First, we need to restore the desired flow control
660 * settings because we may have had to re-autoneg with a
661 * different link partner.
662 */
663 ret_val = e1000_config_fc_after_link_up_generic(hw);
664 if (ret_val) {
665 DEBUGOUT("Error configuring flow control\n");
666 }
667
668 out:
669 return ret_val;
670 }
671
672 /**
673 * e1000_config_dsp_after_link_change_82541 - Config DSP after link
674 * @hw: pointer to the HW structure
675 * @link_up: boolean flag for link up status
676 *
677 * Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS
678 * at any other case.
679 *
680 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
681 * gigabit link is achieved to improve link quality.
682 * This is a function pointer entry point called by the api module.
683 **/
684 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
685 bool link_up)
686 {
687 struct e1000_phy_info *phy = &hw->phy;
688 struct e1000_dev_spec_82541 *dev_spec;
689 s32 ret_val;
690 u32 idle_errs = 0;
691 u16 phy_data, phy_saved_data, speed, duplex, i;
692 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
693 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
694 {IGP01E1000_PHY_AGC_PARAM_A,
695 IGP01E1000_PHY_AGC_PARAM_B,
696 IGP01E1000_PHY_AGC_PARAM_C,
697 IGP01E1000_PHY_AGC_PARAM_D};
698
699 DEBUGFUNC("e1000_config_dsp_after_link_change_82541");
700
701 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec;
702
703 if (link_up) {
704 ret_val = hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
705 if (ret_val) {
706 DEBUGOUT("Error getting link speed and duplex\n");
707 goto out;
708 }
709
710 if (speed != SPEED_1000) {
711 ret_val = E1000_SUCCESS;
712 goto out;
713 }
714
715 ret_val = phy->ops.get_cable_length(hw);
716 if (ret_val)
717 goto out;
718
719 if ((dev_spec->dsp_config == e1000_dsp_config_enabled) &&
720 phy->min_cable_length >= 50) {
721
722 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
723 ret_val = phy->ops.read_reg(hw,
724 dsp_reg_array[i],
725 &phy_data);
726 if (ret_val)
727 goto out;
728
729 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
730
731 ret_val = phy->ops.write_reg(hw,
732 dsp_reg_array[i],
733 phy_data);
734 if (ret_val)
735 goto out;
736 }
737 dev_spec->dsp_config = e1000_dsp_config_activated;
738 }
739
740 if ((dev_spec->ffe_config != e1000_ffe_config_enabled) ||
741 (phy->min_cable_length >= 50)) {
742 ret_val = E1000_SUCCESS;
743 goto out;
744 }
745
746 /* clear previous idle error counts */
747 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
748 if (ret_val)
749 goto out;
750
751 for (i = 0; i < ffe_idle_err_timeout; i++) {
752 usec_delay(1000);
753 ret_val = phy->ops.read_reg(hw,
754 PHY_1000T_STATUS,
755 &phy_data);
756 if (ret_val)
757 goto out;
758
759 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
760 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
761 dev_spec->ffe_config = e1000_ffe_config_active;
762
763 ret_val = phy->ops.write_reg(hw,
764 IGP01E1000_PHY_DSP_FFE,
765 IGP01E1000_PHY_DSP_FFE_CM_CP);
766 if (ret_val)
767 goto out;
768 break;
769 }
770
771 if (idle_errs)
772 ffe_idle_err_timeout =
773 FFE_IDLE_ERR_COUNT_TIMEOUT_100;
774 }
775 } else {
776 if (dev_spec->dsp_config == e1000_dsp_config_activated) {
777 /*
778 * Save off the current value of register 0x2F5B
779 * to be restored at the end of the routines.
780 */
781 ret_val = phy->ops.read_reg(hw,
782 0x2F5B,
783 &phy_saved_data);
784 if (ret_val)
785 goto out;
786
787 /* Disable the PHY transmitter */
788 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
789 if (ret_val)
790 goto out;
791
792 msec_delay_irq(20);
793
794 ret_val = phy->ops.write_reg(hw,
795 0x0000,
796 IGP01E1000_IEEE_FORCE_GIG);
797 if (ret_val)
798 goto out;
799 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
800 ret_val = phy->ops.read_reg(hw,
801 dsp_reg_array[i],
802 &phy_data);
803 if (ret_val)
804 goto out;
805
806 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
807 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
808
809 ret_val = phy->ops.write_reg(hw,
810 dsp_reg_array[i],
811 phy_data);
812 if (ret_val)
813 goto out;
814 }
815
816 ret_val = phy->ops.write_reg(hw,
817 0x0000,
818 IGP01E1000_IEEE_RESTART_AUTONEG);
819 if (ret_val)
820 goto out;
821
822 msec_delay_irq(20);
823
824 /* Now enable the transmitter */
825 ret_val = phy->ops.write_reg(hw,
826 0x2F5B,
827 phy_saved_data);
828 if (ret_val)
829 goto out;
830
831 dev_spec->dsp_config = e1000_dsp_config_enabled;
832 }
833
834 if (dev_spec->ffe_config != e1000_ffe_config_active) {
835 ret_val = E1000_SUCCESS;
836 goto out;
837 }
838
839 /*
840 * Save off the current value of register 0x2F5B
841 * to be restored at the end of the routines.
842 */
843 ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data);
844 if (ret_val)
845 goto out;
846
847 /* Disable the PHY transmitter */
848 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
849 if (ret_val)
850 goto out;
851
852 msec_delay_irq(20);
853
854 ret_val = phy->ops.write_reg(hw,
855 0x0000,
856 IGP01E1000_IEEE_FORCE_GIG);
857 if (ret_val)
858 goto out;
859
860 ret_val = phy->ops.write_reg(hw,
861 IGP01E1000_PHY_DSP_FFE,
862 IGP01E1000_PHY_DSP_FFE_DEFAULT);
863 if (ret_val)
864 goto out;
865
866 ret_val = phy->ops.write_reg(hw,
867 0x0000,
868 IGP01E1000_IEEE_RESTART_AUTONEG);
869 if (ret_val)
870 goto out;
871
872 msec_delay_irq(20);
873
874 /* Now enable the transmitter */
875 ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data);
876
877 if (ret_val)
878 goto out;
879
880 dev_spec->ffe_config = e1000_ffe_config_enabled;
881 }
882
883 out:
884 return ret_val;
885 }
886
887 /**
888 * e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY
889 * @hw: pointer to the HW structure
890 *
891 * The automatic gain control (agc) normalizes the amplitude of the
892 * received signal, adjusting for the attenuation produced by the
893 * cable. By reading the AGC registers, which represent the
894 * combination of coarse and fine gain value, the value can be put
895 * into a lookup table to obtain the approximate cable length
896 * for each channel. This is a function pointer entry point called by the
897 * api module.
898 **/
899 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw)
900 {
901 struct e1000_phy_info *phy = &hw->phy;
902 s32 ret_val = E1000_SUCCESS;
903 u16 i, data;
904 u16 cur_agc_value, agc_value = 0;
905 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
906 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
907 {IGP01E1000_PHY_AGC_A,
908 IGP01E1000_PHY_AGC_B,
909 IGP01E1000_PHY_AGC_C,
910 IGP01E1000_PHY_AGC_D};
911
912 DEBUGFUNC("e1000_get_cable_length_igp_82541");
913
914 /* Read the AGC registers for all channels */
915 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
916 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data);
917 if (ret_val)
918 goto out;
919
920 cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT;
921
922 /* Bounds checking */
923 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
924 (cur_agc_value == 0)) {
925 ret_val = -E1000_ERR_PHY;
926 goto out;
927 }
928
929 agc_value += cur_agc_value;
930
931 if (min_agc_value > cur_agc_value)
932 min_agc_value = cur_agc_value;
933 }
934
935 /* Remove the minimal AGC result for length < 50m */
936 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) {
937 agc_value -= min_agc_value;
938 /* Average the three remaining channels for the length. */
939 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
940 } else {
941 /* Average the channels for the length. */
942 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
943 }
944
945 phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] >
946 IGP01E1000_AGC_RANGE)
947 ? (e1000_igp_cable_length_table[agc_value] -
948 IGP01E1000_AGC_RANGE)
949 : 0;
950 phy->max_cable_length = e1000_igp_cable_length_table[agc_value] +
951 IGP01E1000_AGC_RANGE;
952
953 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
954
955 out:
956 return ret_val;
957 }
958
959 /**
960 * e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3
961 * @hw: pointer to the HW structure
962 * @active: boolean used to enable/disable lplu
963 *
964 * Success returns 0, Failure returns 1
965 *
966 * The low power link up (lplu) state is set to the power management level D3
967 * and SmartSpeed is disabled when active is true, else clear lplu for D3
968 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
969 * is used during Dx states where the power conservation is most important.
970 * During driver activity, SmartSpeed should be enabled so performance is
971 * maintained. This is a function pointer entry point called by the
972 * api module.
973 **/
974 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active)
975 {
976 struct e1000_phy_info *phy = &hw->phy;
977 s32 ret_val;
978 u16 data;
979
980 DEBUGFUNC("e1000_set_d3_lplu_state_82541");
981
982 switch (hw->mac.type) {
983 case e1000_82541_rev_2:
984 case e1000_82547_rev_2:
985 break;
986 default:
987 ret_val = e1000_set_d3_lplu_state_generic(hw, active);
988 goto out;
989 break;
990 }
991
992 ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data);
993 if (ret_val)
994 goto out;
995
996 if (!active) {
997 data &= ~IGP01E1000_GMII_FLEX_SPD;
998 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
999 if (ret_val)
1000 goto out;
1001
1002 /*
1003 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1004 * during Dx states where the power conservation is most
1005 * important. During driver activity we should enable
1006 * SmartSpeed, so performance is maintained.
1007 */
1008 if (phy->smart_speed == e1000_smart_speed_on) {
1009 ret_val = phy->ops.read_reg(hw,
1010 IGP01E1000_PHY_PORT_CONFIG,
1011 &data);
1012 if (ret_val)
1013 goto out;
1014
1015 data |= IGP01E1000_PSCFR_SMART_SPEED;
1016 ret_val = phy->ops.write_reg(hw,
1017 IGP01E1000_PHY_PORT_CONFIG,
1018 data);
1019 if (ret_val)
1020 goto out;
1021 } else if (phy->smart_speed == e1000_smart_speed_off) {
1022 ret_val = phy->ops.read_reg(hw,
1023 IGP01E1000_PHY_PORT_CONFIG,
1024 &data);
1025 if (ret_val)
1026 goto out;
1027
1028 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1029 ret_val = phy->ops.write_reg(hw,
1030 IGP01E1000_PHY_PORT_CONFIG,
1031 data);
1032 if (ret_val)
1033 goto out;
1034 }
1035 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1036 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1037 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1038 data |= IGP01E1000_GMII_FLEX_SPD;
1039 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
1040 if (ret_val)
1041 goto out;
1042
1043 /* When LPLU is enabled, we should disable SmartSpeed */
1044 ret_val = phy->ops.read_reg(hw,
1045 IGP01E1000_PHY_PORT_CONFIG,
1046 &data);
1047 if (ret_val)
1048 goto out;
1049
1050 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1051 ret_val = phy->ops.write_reg(hw,
1052 IGP01E1000_PHY_PORT_CONFIG,
1053 data);
1054 }
1055
1056 out:
1057 return ret_val;
1058 }
1059
1060 /**
1061 * e1000_setup_led_82541 - Configures SW controllable LED
1062 * @hw: pointer to the HW structure
1063 *
1064 * This prepares the SW controllable LED for use and saves the current state
1065 * of the LED so it can be later restored. This is a function pointer entry
1066 * point called by the api module.
1067 **/
1068 static s32 e1000_setup_led_82541(struct e1000_hw *hw)
1069 {
1070 struct e1000_dev_spec_82541 *dev_spec;
1071 s32 ret_val;
1072
1073 DEBUGFUNC("e1000_setup_led_82541");
1074
1075 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec;
1076
1077 ret_val = hw->phy.ops.read_reg(hw,
1078 IGP01E1000_GMII_FIFO,
1079 &dev_spec->spd_default);
1080 if (ret_val)
1081 goto out;
1082
1083 ret_val = hw->phy.ops.write_reg(hw,
1084 IGP01E1000_GMII_FIFO,
1085 (u16)(dev_spec->spd_default &
1086 ~IGP01E1000_GMII_SPD));
1087 if (ret_val)
1088 goto out;
1089
1090 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1091
1092 out:
1093 return ret_val;
1094 }
1095
1096 /**
1097 * e1000_cleanup_led_82541 - Set LED config to default operation
1098 * @hw: pointer to the HW structure
1099 *
1100 * Remove the current LED configuration and set the LED configuration
1101 * to the default value, saved from the EEPROM. This is a function pointer
1102 * entry point called by the api module.
1103 **/
1104 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw)
1105 {
1106 struct e1000_dev_spec_82541 *dev_spec;
1107 s32 ret_val;
1108
1109 DEBUGFUNC("e1000_cleanup_led_82541");
1110
1111 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec;
1112
1113 ret_val = hw->phy.ops.write_reg(hw,
1114 IGP01E1000_GMII_FIFO,
1115 dev_spec->spd_default);
1116 if (ret_val)
1117 goto out;
1118
1119 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1120
1121 out:
1122 return ret_val;
1123 }
1124
1125 /**
1126 * e1000_phy_init_script_82541 - Initialize GbE PHY
1127 * @hw: pointer to the HW structure
1128 *
1129 * Initializes the IGP PHY.
1130 **/
1131 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw)
1132 {
1133 struct e1000_dev_spec_82541 *dev_spec;
1134 u32 ret_val;
1135 u16 phy_saved_data;
1136
1137 DEBUGFUNC("e1000_phy_init_script_82541");
1138
1139 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec;
1140
1141 if (!dev_spec->phy_init_script) {
1142 ret_val = E1000_SUCCESS;
1143 goto out;
1144 }
1145
1146 /* Delay after phy reset to enable NVM configuration to load */
1147 msec_delay(20);
1148
1149 /*
1150 * Save off the current value of register 0x2F5B to be restored at
1151 * the end of this routine.
1152 */
1153 ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data);
1154
1155 /* Disabled the PHY transmitter */
1156 hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003);
1157
1158 msec_delay(20);
1159
1160 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
1161
1162 msec_delay(5);
1163
1164 switch (hw->mac.type) {
1165 case e1000_82541:
1166 case e1000_82547:
1167 hw->phy.ops.write_reg(hw, 0x1F95, 0x0001);
1168
1169 hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21);
1170
1171 hw->phy.ops.write_reg(hw, 0x1F79, 0x0018);
1172
1173 hw->phy.ops.write_reg(hw, 0x1F30, 0x1600);
1174
1175 hw->phy.ops.write_reg(hw, 0x1F31, 0x0014);
1176
1177 hw->phy.ops.write_reg(hw, 0x1F32, 0x161C);
1178
1179 hw->phy.ops.write_reg(hw, 0x1F94, 0x0003);
1180
1181 hw->phy.ops.write_reg(hw, 0x1F96, 0x003F);
1182
1183 hw->phy.ops.write_reg(hw, 0x2010, 0x0008);
1184 break;
1185 case e1000_82541_rev_2:
1186 case e1000_82547_rev_2:
1187 hw->phy.ops.write_reg(hw, 0x1F73, 0x0099);
1188 break;
1189 default:
1190 break;
1191 }
1192
1193 hw->phy.ops.write_reg(hw, 0x0000, 0x3300);
1194
1195 msec_delay(20);
1196
1197 /* Now enable the transmitter */
1198 hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data);
1199
1200 if (hw->mac.type == e1000_82547) {
1201 u16 fused, fine, coarse;
1202
1203 /* Move to analog registers page */
1204 hw->phy.ops.read_reg(hw,
1205 IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
1206 &fused);
1207
1208 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
1209 hw->phy.ops.read_reg(hw,
1210 IGP01E1000_ANALOG_FUSE_STATUS,
1211 &fused);
1212
1213 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
1214 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
1215
1216 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
1217 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
1218 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
1219 } else if (coarse ==
1220 IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
1221 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
1222
1223 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
1224 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
1225 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
1226
1227 hw->phy.ops.write_reg(hw,
1228 IGP01E1000_ANALOG_FUSE_CONTROL,
1229 fused);
1230 hw->phy.ops.write_reg(hw,
1231 IGP01E1000_ANALOG_FUSE_BYPASS,
1232 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
1233 }
1234 }
1235
1236 out:
1237 return ret_val;
1238 }
1239
1240 /**
1241 * e1000_init_script_state_82541 - Enable/Disable PHY init script
1242 * @hw: pointer to the HW structure
1243 * @state: boolean value used to enable/disable PHY init script
1244 *
1245 * Allows the driver to enable/disable the PHY init script, if the PHY is an
1246 * IGP PHY. This is a function pointer entry point called by the api module.
1247 **/
1248 void e1000_init_script_state_82541(struct e1000_hw *hw, bool state)
1249 {
1250 struct e1000_dev_spec_82541 *dev_spec;
1251
1252 DEBUGFUNC("e1000_init_script_state_82541");
1253
1254 if (hw->phy.type != e1000_phy_igp) {
1255 DEBUGOUT("Initialization script not necessary.\n");
1256 goto out;
1257 }
1258
1259 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec;
1260
1261 if (!dev_spec) {
1262 DEBUGOUT("dev_spec pointer is set to NULL.\n");
1263 goto out;
1264 }
1265
1266 dev_spec->phy_init_script = state;
1267
1268 out:
1269 return;
1270 }
1271
1272 /**
1273 * e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down
1274 * @hw: pointer to the HW structure
1275 *
1276 * In the case of a PHY power down to save power, or to turn off link during a
1277 * driver unload, or wake on lan is not enabled, remove the link.
1278 **/
1279 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw)
1280 {
1281 /* If the management interface is not enabled, then power down */
1282 if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
1283 e1000_power_down_phy_copper(hw);
1284
1285 return;
1286 }
1287
1288 /**
1289 * e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters
1290 * @hw: pointer to the HW structure
1291 *
1292 * Clears the hardware counters by reading the counter registers.
1293 **/
1294 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw)
1295 {
1296 volatile u32 temp;
1297
1298 DEBUGFUNC("e1000_clear_hw_cntrs_82541");
1299
1300 e1000_clear_hw_cntrs_base_generic(hw);
1301
1302 temp = E1000_READ_REG(hw, E1000_PRC64);
1303 temp = E1000_READ_REG(hw, E1000_PRC127);
1304 temp = E1000_READ_REG(hw, E1000_PRC255);
1305 temp = E1000_READ_REG(hw, E1000_PRC511);
1306 temp = E1000_READ_REG(hw, E1000_PRC1023);
1307 temp = E1000_READ_REG(hw, E1000_PRC1522);
1308 temp = E1000_READ_REG(hw, E1000_PTC64);
1309 temp = E1000_READ_REG(hw, E1000_PTC127);
1310 temp = E1000_READ_REG(hw, E1000_PTC255);
1311 temp = E1000_READ_REG(hw, E1000_PTC511);
1312 temp = E1000_READ_REG(hw, E1000_PTC1023);
1313 temp = E1000_READ_REG(hw, E1000_PTC1522);
1314
1315 temp = E1000_READ_REG(hw, E1000_ALGNERRC);
1316 temp = E1000_READ_REG(hw, E1000_RXERRC);
1317 temp = E1000_READ_REG(hw, E1000_TNCRS);
1318 temp = E1000_READ_REG(hw, E1000_CEXTERR);
1319 temp = E1000_READ_REG(hw, E1000_TSCTC);
1320 temp = E1000_READ_REG(hw, E1000_TSCTFC);
1321
1322 temp = E1000_READ_REG(hw, E1000_MGTPRC);
1323 temp = E1000_READ_REG(hw, E1000_MGTPDC);
1324 temp = E1000_READ_REG(hw, E1000_MGTPTC);
1325 }
A totally sweet operating system