workbench/devs/networks/e1000/e1000_hw.h

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 #ifndef _E1000_HW_H_
  30 #define _E1000_HW_H_
  31
  32 #include "e1000_osdep.h"
  33 #include "e1000_regs.h"
  34 #include "e1000_defines.h"
  35
  36 struct e1000_hw;
  37
  38 #define E1000_DEV_ID_82542                    0x1000
  39 #define E1000_DEV_ID_82543GC_FIBER            0x1001
  40 #define E1000_DEV_ID_82543GC_COPPER           0x1004
  41 #define E1000_DEV_ID_82544EI_COPPER           0x1008
  42 #define E1000_DEV_ID_82544EI_FIBER            0x1009
  43 #define E1000_DEV_ID_82544GC_COPPER           0x100C
  44 #define E1000_DEV_ID_82544GC_LOM              0x100D
  45 #define E1000_DEV_ID_82540EM                  0x100E
  46 #define E1000_DEV_ID_82540EM_LOM              0x1015
  47 #define E1000_DEV_ID_82540EP_LOM              0x1016
  48 #define E1000_DEV_ID_82540EP                  0x1017
  49 #define E1000_DEV_ID_82540EP_LP               0x101E
  50 #define E1000_DEV_ID_82545EM_COPPER           0x100F
  51 #define E1000_DEV_ID_82545EM_FIBER            0x1011
  52 #define E1000_DEV_ID_82545GM_COPPER           0x1026
  53 #define E1000_DEV_ID_82545GM_FIBER            0x1027
  54 #define E1000_DEV_ID_82545GM_SERDES           0x1028
  55 #define E1000_DEV_ID_82546EB_COPPER           0x1010
  56 #define E1000_DEV_ID_82546EB_FIBER            0x1012
  57 #define E1000_DEV_ID_82546EB_QUAD_COPPER      0x101D
  58 #define E1000_DEV_ID_82546GB_COPPER           0x1079
  59 #define E1000_DEV_ID_82546GB_FIBER            0x107A
  60 #define E1000_DEV_ID_82546GB_SERDES           0x107B
  61 #define E1000_DEV_ID_82546GB_PCIE             0x108A
  62 #define E1000_DEV_ID_82546GB_QUAD_COPPER      0x1099
  63 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
  64 #define E1000_DEV_ID_82541EI                  0x1013
  65 #define E1000_DEV_ID_82541EI_MOBILE           0x1018
  66 #define E1000_DEV_ID_82541ER_LOM              0x1014
  67 #define E1000_DEV_ID_82541ER                  0x1078
  68 #define E1000_DEV_ID_82541GI                  0x1076
  69 #define E1000_DEV_ID_82541GI_LF               0x107C
  70 #define E1000_DEV_ID_82541GI_MOBILE           0x1077
  71 #define E1000_DEV_ID_82547EI                  0x1019
  72 #define E1000_DEV_ID_82547EI_MOBILE           0x101A
  73 #define E1000_DEV_ID_82547GI                  0x1075
  74
  75 #define E1000_REVISION_0 0
  76 #define E1000_REVISION_1 1
  77 #define E1000_REVISION_2 2
  78 #define E1000_REVISION_3 3
  79 #define E1000_REVISION_4 4
  80
  81 #define E1000_FUNC_0     0
  82 #define E1000_FUNC_1     1
  83
  84 typedef enum {
  85         e1000_undefined = 0,
  86         e1000_82542,
  87         e1000_82543,
  88         e1000_82544,
  89         e1000_82540,
  90         e1000_82545,
  91         e1000_82545_rev_3,
  92         e1000_82546,
  93         e1000_82546_rev_3,
  94         e1000_82541,
  95         e1000_82541_rev_2,
  96         e1000_82547,
  97         e1000_82547_rev_2,
  98         e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
  99 } e1000_mac_type;
 100
 101 typedef enum {
 102         e1000_media_type_unknown = 0,
 103         e1000_media_type_copper = 1,
 104         e1000_media_type_fiber = 2,
 105         e1000_media_type_internal_serdes = 3,
 106         e1000_num_media_types
 107 } e1000_media_type;
 108
 109 typedef enum {
 110         e1000_nvm_unknown = 0,
 111         e1000_nvm_none,
 112         e1000_nvm_eeprom_spi,
 113         e1000_nvm_eeprom_microwire,
 114         e1000_nvm_flash_hw,
 115         e1000_nvm_flash_sw
 116 } e1000_nvm_type;
 117
 118 typedef enum {
 119         e1000_nvm_override_none = 0,
 120         e1000_nvm_override_spi_small,
 121         e1000_nvm_override_spi_large,
 122         e1000_nvm_override_microwire_small,
 123         e1000_nvm_override_microwire_large
 124 } e1000_nvm_override;
 125
 126 typedef enum {
 127         e1000_phy_unknown = 0,
 128         e1000_phy_none,
 129         e1000_phy_m88,
 130         e1000_phy_igp,
 131         e1000_phy_igp_2,
 132         e1000_phy_gg82563,
 133         e1000_phy_igp_3,
 134         e1000_phy_ife,
 135 } e1000_phy_type;
 136
 137 typedef enum {
 138         e1000_bus_type_unknown = 0,
 139         e1000_bus_type_pci,
 140         e1000_bus_type_pcix,
 141         e1000_bus_type_pci_express,
 142         e1000_bus_type_reserved
 143 } e1000_bus_type;
 144
 145 typedef enum {
 146         e1000_bus_speed_unknown = 0,
 147         e1000_bus_speed_33,
 148         e1000_bus_speed_66,
 149         e1000_bus_speed_100,
 150         e1000_bus_speed_120,
 151         e1000_bus_speed_133,
 152         e1000_bus_speed_2500,
 153         e1000_bus_speed_5000,
 154         e1000_bus_speed_reserved
 155 } e1000_bus_speed;
 156
 157 typedef enum {
 158         e1000_bus_width_unknown = 0,
 159         e1000_bus_width_pcie_x1,
 160         e1000_bus_width_pcie_x2,
 161         e1000_bus_width_pcie_x4 = 4,
 162         e1000_bus_width_pcie_x8 = 8,
 163         e1000_bus_width_32,
 164         e1000_bus_width_64,
 165         e1000_bus_width_reserved
 166 } e1000_bus_width;
 167
 168 typedef enum {
 169         e1000_1000t_rx_status_not_ok = 0,
 170         e1000_1000t_rx_status_ok,
 171         e1000_1000t_rx_status_undefined = 0xFF
 172 } e1000_1000t_rx_status;
 173
 174 typedef enum {
 175         e1000_rev_polarity_normal = 0,
 176         e1000_rev_polarity_reversed,
 177         e1000_rev_polarity_undefined = 0xFF
 178 } e1000_rev_polarity;
 179
 180 typedef enum {
 181         e1000_fc_none = 0,
 182         e1000_fc_rx_pause,
 183         e1000_fc_tx_pause,
 184         e1000_fc_full,
 185         e1000_fc_default = 0xFF
 186 } e1000_fc_type;
 187
 188 typedef enum {
 189         e1000_ffe_config_enabled = 0,
 190         e1000_ffe_config_active,
 191         e1000_ffe_config_blocked
 192 } e1000_ffe_config;
 193
 194 typedef enum {
 195         e1000_dsp_config_disabled = 0,
 196         e1000_dsp_config_enabled,
 197         e1000_dsp_config_activated,
 198         e1000_dsp_config_undefined = 0xFF
 199 } e1000_dsp_config;
 200
 201 /* Receive Descriptor */
 202 struct e1000_rx_desc {
 203         u64 buffer_addr; /* Address of the descriptor's data buffer */
 204         u16 length;      /* Length of data DMAed into data buffer */
 205         u16 csum;        /* Packet checksum */
 206         u8  status;      /* Descriptor status */
 207         u8  errors;      /* Descriptor Errors */
 208         u16 special;
 209 };
 210
 211 /* Receive Descriptor - Extended */
 212 union e1000_rx_desc_extended {
 213         struct {
 214                 u64 buffer_addr;
 215                 u64 reserved;
 216         } read;
 217         struct {
 218                 struct {
 219                         u32 mrq;              /* Multiple Rx Queues */
 220                         union {
 221                                 u32 rss;            /* RSS Hash */
 222                                 struct {
 223                                         u16 ip_id;  /* IP id */
 224                                         u16 csum;   /* Packet Checksum */
 225                                 } csum_ip;
 226                         } hi_dword;
 227                 } lower;
 228                 struct {
 229                         u32 status_error;     /* ext status/error */
 230                         u16 length;
 231                         u16 vlan;             /* VLAN tag */
 232                 } upper;
 233         } wb;  /* writeback */
 234 };
 235
 236 #define MAX_PS_BUFFERS 4
 237 /* Receive Descriptor - Packet Split */
 238 union e1000_rx_desc_packet_split {
 239         struct {
 240                 /* one buffer for protocol header(s), three data buffers */
 241                 u64 buffer_addr[MAX_PS_BUFFERS];
 242         } read;
 243         struct {
 244                 struct {
 245                         u32 mrq;              /* Multiple Rx Queues */
 246                         union {
 247                                 u32 rss;              /* RSS Hash */
 248                                 struct {
 249                                         u16 ip_id;    /* IP id */
 250                                         u16 csum;     /* Packet Checksum */
 251                                 } csum_ip;
 252                         } hi_dword;
 253                 } lower;
 254                 struct {
 255                         u32 status_error;     /* ext status/error */
 256                         u16 length0;          /* length of buffer 0 */
 257                         u16 vlan;             /* VLAN tag */
 258                 } middle;
 259                 struct {
 260                         u16 header_status;
 261                         u16 length[3];        /* length of buffers 1-3 */
 262                 } upper;
 263                 u64 reserved;
 264         } wb; /* writeback */
 265 };
 266
 267 /* Transmit Descriptor */
 268 struct e1000_tx_desc {
 269         u64 buffer_addr;      /* Address of the descriptor's data buffer */
 270         union {
 271                 u32 data;
 272                 struct {
 273                         u16 length;    /* Data buffer length */
 274                         u8 cso;        /* Checksum offset */
 275                         u8 cmd;        /* Descriptor control */
 276                 } flags;
 277         } lower;
 278         union {
 279                 u32 data;
 280                 struct {
 281                         u8 status;     /* Descriptor status */
 282                         u8 css;        /* Checksum start */
 283                         u16 special;
 284                 } fields;
 285         } upper;
 286 };
 287
 288 /* Offload Context Descriptor */
 289 struct e1000_context_desc {
 290         union {
 291                 u32 ip_config;
 292                 struct {
 293                         u8 ipcss;      /* IP checksum start */
 294                         u8 ipcso;      /* IP checksum offset */
 295                         u16 ipcse;     /* IP checksum end */
 296                 } ip_fields;
 297         } lower_setup;
 298         union {
 299                 u32 tcp_config;
 300                 struct {
 301                         u8 tucss;      /* TCP checksum start */
 302                         u8 tucso;      /* TCP checksum offset */
 303                         u16 tucse;     /* TCP checksum end */
 304                 } tcp_fields;
 305         } upper_setup;
 306         u32 cmd_and_length;
 307         union {
 308                 u32 data;
 309                 struct {
 310                         u8 status;     /* Descriptor status */
 311                         u8 hdr_len;    /* Header length */
 312                         u16 mss;       /* Maximum segment size */
 313                 } fields;
 314         } tcp_seg_setup;
 315 };
 316
 317 /* Offload data descriptor */
 318 struct e1000_data_desc {
 319         u64 buffer_addr;   /* Address of the descriptor's buffer address */
 320         union {
 321                 u32 data;
 322                 struct {
 323                         u16 length;    /* Data buffer length */
 324                         u8 typ_len_ext;
 325                         u8 cmd;
 326                 } flags;
 327         } lower;
 328         union {
 329                 u32 data;
 330                 struct {
 331                         u8 status;     /* Descriptor status */
 332                         u8 popts;      /* Packet Options */
 333                         u16 special;
 334                 } fields;
 335         } upper;
 336 };
 337
 338 /* Statistics counters collected by the MAC */
 339 struct e1000_hw_stats {
 340         u64 crcerrs;
 341         u64 algnerrc;
 342         u64 symerrs;
 343         u64 rxerrc;
 344         u64 mpc;
 345         u64 scc;
 346         u64 ecol;
 347         u64 mcc;
 348         u64 latecol;
 349         u64 colc;
 350         u64 dc;
 351         u64 tncrs;
 352         u64 sec;
 353         u64 cexterr;
 354         u64 rlec;
 355         u64 xonrxc;
 356         u64 xontxc;
 357         u64 xoffrxc;
 358         u64 xofftxc;
 359         u64 fcruc;
 360         u64 prc64;
 361         u64 prc127;
 362         u64 prc255;
 363         u64 prc511;
 364         u64 prc1023;
 365         u64 prc1522;
 366         u64 gprc;
 367         u64 bprc;
 368         u64 mprc;
 369         u64 gptc;
 370         u64 gorc;
 371         u64 gotc;
 372         u64 rnbc;
 373         u64 ruc;
 374         u64 rfc;
 375         u64 roc;
 376         u64 rjc;
 377         u64 mgprc;
 378         u64 mgpdc;
 379         u64 mgptc;
 380         u64 tor;
 381         u64 tot;
 382         u64 tpr;
 383         u64 tpt;
 384         u64 ptc64;
 385         u64 ptc127;
 386         u64 ptc255;
 387         u64 ptc511;
 388         u64 ptc1023;
 389         u64 ptc1522;
 390         u64 mptc;
 391         u64 bptc;
 392         u64 tsctc;
 393         u64 tsctfc;
 394         u64 iac;
 395         u64 icrxptc;
 396         u64 icrxatc;
 397         u64 ictxptc;
 398         u64 ictxatc;
 399         u64 ictxqec;
 400         u64 ictxqmtc;
 401         u64 icrxdmtc;
 402         u64 icrxoc;
 403         u64 cbtmpc;
 404         u64 htdpmc;
 405         u64 cbrdpc;
 406         u64 cbrmpc;
 407         u64 rpthc;
 408         u64 hgptc;
 409         u64 htcbdpc;
 410         u64 hgorc;
 411         u64 hgotc;
 412         u64 lenerrs;
 413         u64 scvpc;
 414         u64 hrmpc;
 415 };
 416
 417 struct e1000_phy_stats {
 418         u32 idle_errors;
 419         u32 receive_errors;
 420 };
 421
 422 struct e1000_host_mng_dhcp_cookie {
 423         u32 signature;
 424         u8  status;
 425         u8  reserved0;
 426         u16 vlan_id;
 427         u32 reserved1;
 428         u16 reserved2;
 429         u8  reserved3;
 430         u8  checksum;
 431 };
 432
 433 /* Host Interface "Rev 1" */
 434 struct e1000_host_command_header {
 435         u8 command_id;
 436         u8 command_length;
 437         u8 command_options;
 438         u8 checksum;
 439 };
 440
 441 #define E1000_HI_MAX_DATA_LENGTH     252
 442 struct e1000_host_command_info {
 443         struct e1000_host_command_header command_header;
 444         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 445 };
 446
 447 /* Host Interface "Rev 2" */
 448 struct e1000_host_mng_command_header {
 449         u8  command_id;
 450         u8  checksum;
 451         u16 reserved1;
 452         u16 reserved2;
 453         u16 command_length;
 454 };
 455
 456 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
 457 struct e1000_host_mng_command_info {
 458         struct e1000_host_mng_command_header command_header;
 459         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 460 };
 461
 462 #include "e1000_mac.h"
 463 #include "e1000_phy.h"
 464 #include "e1000_nvm.h"
 465 #include "e1000_manage.h"
 466
 467 struct e1000_mac_operations {
 468         /* Function pointers for the MAC. */
 469         s32  (*init_params)(struct e1000_hw *);
 470         s32  (*blink_led)(struct e1000_hw *);
 471         s32  (*check_for_link)(struct e1000_hw *);
 472         bool (*check_mng_mode)(struct e1000_hw *hw);
 473         s32  (*cleanup_led)(struct e1000_hw *);
 474         void (*clear_hw_cntrs)(struct e1000_hw *);
 475         void (*clear_vfta)(struct e1000_hw *);
 476         s32  (*get_bus_info)(struct e1000_hw *);
 477         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 478         s32  (*led_on)(struct e1000_hw *);
 479         s32  (*led_off)(struct e1000_hw *);
 480         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32, u32,
 481                                     u32);
 482         void (*remove_device)(struct e1000_hw *);
 483         s32  (*reset_hw)(struct e1000_hw *);
 484         s32  (*init_hw)(struct e1000_hw *);
 485         s32  (*setup_link)(struct e1000_hw *);
 486         s32  (*setup_physical_interface)(struct e1000_hw *);
 487         s32  (*setup_led)(struct e1000_hw *);
 488         void (*write_vfta)(struct e1000_hw *, u32, u32);
 489         void (*mta_set)(struct e1000_hw *, u32);
 490         void (*config_collision_dist)(struct e1000_hw*);
 491         void (*rar_set)(struct e1000_hw*, u8*, u32);
 492         s32  (*read_mac_addr)(struct e1000_hw*);
 493         s32  (*validate_mdi_setting)(struct e1000_hw*);
 494         s32  (*mng_host_if_write)(struct e1000_hw*, u8*, u16, u16, u8*);
 495         s32  (*mng_write_cmd_header)(struct e1000_hw *hw,
 496                       struct e1000_host_mng_command_header*);
 497         s32  (*mng_enable_host_if)(struct e1000_hw*);
 498         s32  (*wait_autoneg)(struct e1000_hw*);
 499 };
 500
 501 struct e1000_phy_operations {
 502         s32  (*init_params)(struct e1000_hw *);
 503         s32  (*acquire)(struct e1000_hw *);
 504         s32  (*check_polarity)(struct e1000_hw *);
 505         s32  (*check_reset_block)(struct e1000_hw *);
 506         s32  (*commit)(struct e1000_hw *);
 507         s32  (*force_speed_duplex)(struct e1000_hw *);
 508         s32  (*get_cfg_done)(struct e1000_hw *hw);
 509         s32  (*get_cable_length)(struct e1000_hw *);
 510         s32  (*get_info)(struct e1000_hw *);
 511         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 512         void (*release)(struct e1000_hw *);
 513         s32  (*reset)(struct e1000_hw *);
 514         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 515         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 516         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 517         void (*power_up)(struct e1000_hw *);
 518         void (*power_down)(struct e1000_hw *);
 519 };
 520
 521 struct e1000_nvm_operations {
 522         s32  (*init_params)(struct e1000_hw *);
 523         s32  (*acquire)(struct e1000_hw *);
 524         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 525         void (*release)(struct e1000_hw *);
 526         void (*reload)(struct e1000_hw *);
 527         s32  (*update)(struct e1000_hw *);
 528         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 529         s32  (*validate)(struct e1000_hw *);
 530         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 531 };
 532
 533 struct e1000_mac_info {
 534         struct e1000_mac_operations ops;
 535         u8 addr[6];
 536         u8 perm_addr[6];
 537
 538         e1000_mac_type type;
 539
 540         u32 collision_delta;
 541         u32 ledctl_default;
 542         u32 ledctl_mode1;
 543         u32 ledctl_mode2;
 544         u32 mc_filter_type;
 545         u32 tx_packet_delta;
 546         u32 txcw;
 547
 548         u16 current_ifs_val;
 549         u16 ifs_max_val;
 550         u16 ifs_min_val;
 551         u16 ifs_ratio;
 552         u16 ifs_step_size;
 553         u16 mta_reg_count;
 554         u16 rar_entry_count;
 555
 556         u8  forced_speed_duplex;
 557
 558         bool adaptive_ifs;
 559         bool arc_subsystem_valid;
 560         bool asf_firmware_present;
 561         bool autoneg;
 562         bool autoneg_failed;
 563         bool disable_av;
 564         bool disable_hw_init_bits;
 565         bool get_link_status;
 566         bool ifs_params_forced;
 567         bool in_ifs_mode;
 568         bool report_tx_early;
 569         bool serdes_has_link;
 570         bool tx_pkt_filtering;
 571 };
 572
 573 struct e1000_phy_info {
 574         struct e1000_phy_operations ops;
 575         e1000_phy_type type;
 576
 577         e1000_1000t_rx_status local_rx;
 578         e1000_1000t_rx_status remote_rx;
 579         e1000_ms_type ms_type;
 580         e1000_ms_type original_ms_type;
 581         e1000_rev_polarity cable_polarity;
 582         e1000_smart_speed smart_speed;
 583
 584         u32 addr;
 585         u32 id;
 586         u32 reset_delay_us; /* in usec */
 587         u32 revision;
 588
 589         e1000_media_type media_type;
 590
 591         u16 autoneg_advertised;
 592         u16 autoneg_mask;
 593         u16 cable_length;
 594         u16 max_cable_length;
 595         u16 min_cable_length;
 596
 597         u8 mdix;
 598
 599         bool disable_polarity_correction;
 600         bool is_mdix;
 601         bool polarity_correction;
 602         bool reset_disable;
 603         bool speed_downgraded;
 604         bool autoneg_wait_to_complete;
 605 };
 606
 607 struct e1000_nvm_info {
 608         struct e1000_nvm_operations ops;
 609         e1000_nvm_type type;
 610         e1000_nvm_override override;
 611
 612         u32 flash_bank_size;
 613         u32 flash_base_addr;
 614
 615         u16 word_size;
 616         u16 delay_usec;
 617         u16 address_bits;
 618         u16 opcode_bits;
 619         u16 page_size;
 620 };
 621
 622 struct e1000_bus_info {
 623         e1000_bus_type type;
 624         e1000_bus_speed speed;
 625         e1000_bus_width width;
 626
 627         u32 snoop;
 628
 629         u16 func;
 630         u16 pci_cmd_word;
 631 };
 632
 633 struct e1000_fc_info {
 634         u32 high_water;     /* Flow control high-water mark */
 635         u32 low_water;      /* Flow control low-water mark */
 636         u16 pause_time;     /* Flow control pause timer */
 637         bool send_xon;      /* Flow control send XON */
 638         bool strict_ieee;   /* Strict IEEE mode */
 639         e1000_fc_type type; /* Type of flow control */
 640         e1000_fc_type original_type;
 641 };
 642
 643 struct e1000_hw {
 644         void *back;
 645         void *dev_spec;
 646
 647         u8 __iomem *hw_addr;
 648         u8 __iomem *flash_address;
 649         unsigned long io_base;
 650
 651         struct e1000_mac_info  mac;
 652         struct e1000_fc_info   fc;
 653         struct e1000_phy_info  phy;
 654         struct e1000_nvm_info  nvm;
 655         struct e1000_bus_info  bus;
 656         struct e1000_host_mng_dhcp_cookie mng_cookie;
 657
 658         u32 dev_spec_size;
 659
 660         u16 device_id;
 661         u16 subsystem_vendor_id;
 662         u16 subsystem_device_id;
 663         u16 vendor_id;
 664
 665         u8  revision_id;
 666 };
 667
 668 /* These functions must be implemented by drivers */
 669 void e1000_pci_clear_mwi(struct e1000_hw *hw);
 670 void e1000_pci_set_mwi(struct e1000_hw *hw);
 671 s32  e1000_alloc_zeroed_dev_spec_struct(struct e1000_hw *hw, u32 size);
 672 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 673 void e1000_free_dev_spec_struct(struct e1000_hw *hw);
 674 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 675 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 676
 677 #endif