workbench/devs/networks/rtl8139/rtl8139.h

   1 #ifndef _RTL8139_H
   2 #define _RTL8139_H
   3
   4 /*
   5  * $Id$
   6  */
   7
   8 /*
   9         This program is free software; you can redistribute it and/or modify
  10         it under the terms of the GNU General Public License as published by
  11         the Free Software Foundation; either version 2 of the License, or
  12         (at your option) any later version.
  13
  14         This program is distributed in the hope that it will be useful, but
  15         WITHOUT ANY WARRANTY; without even the implied warranty of
  16         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  17         General Public License for more details.
  18
  19         You should have received a copy of the GNU General Public License
  20         along with this program; if not, write to the Free Software
  21         Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  22         MA 02111-1307, USA.
  23 */
  24
  25 #include <aros/debug.h>
  26
  27 #if DEBUG > 0
  28 #define RTL_DEBUG
  29 #endif
  30
  31 #define RTLD(d) \
  32         if (unit->rtl8139u_flags & IFF_DEBUG) \
  33         { \
  34                 d; \
  35         }
  36
  37 #include <exec/types.h>
  38 #include <exec/libraries.h>
  39 #include <exec/semaphores.h>
  40 #include <exec/devices.h>
  41 #include <exec/interrupts.h>
  42 #include <dos/bptr.h>
  43
  44 #include <oop/oop.h>
  45
  46 #include <hidd/pci.h>
  47 #include <hidd/irq.h>
  48
  49 #include <devices/timer.h>
  50 #include <devices/sana2.h>
  51 #include <devices/sana2specialstats.h>
  52
  53 #include <proto/exec.h>
  54
  55 #include LC_LIBDEFS_FILE
  56
  57 #define net_device RTL8139Unit
  58
  59 #define RTL8139_TASK_NAME       "%s.task"
  60 #define RTL8139_PORT_NAME       "%s.port"
  61
  62 /** Operational parameters that are set at compile time **/
  63 #define ETH_ZLEN  60 // Min. octets in frame sans FCS
  64
  65 // Maximum size of the in-memory receive ring (smaller if no memory)
  66 #define RX_BUF_LEN_IDX  2     // 0=8K, 1=16K, 2=32K, 3=64K
  67 #define RX_FIFO_THRESH  4    // Rx buffer level before first PCI xfer
  68 #define RX_DMA_BURST    4   // Maximum PCI burst, '4' is 256 bytes
  69
  70 // Size of the Tx bounce buffers -- must be at least (mtu+14+4)
  71 #define TX_BUF_SIZE 1536
  72 #define NUM_TX_DESC 4         // Number of Tx descriptor registers
  73 #define TX_FIFO_THRESH 256  // In bytes, rounded down to 32 byte units
  74 #define TX_DMA_BURST    4   // Calculate as 16 << val
  75
  76 /** Device Driver Structures **/
  77
  78 extern struct Library *OOPBase;
  79
  80 struct RTL8139Base {
  81     struct Device       rtl8139b_Device;
  82
  83     OOP_Object          *rtl8139b_PCI;
  84     OOP_AttrBase        rtl8139b_PCIDeviceAttrBase;
  85
  86     ULONG               rtl8139b_UnitCount;
  87     struct List         rtl8139b_Units;
  88 };
  89
  90 #undef HiddPCIDeviceAttrBase
  91 #define HiddPCIDeviceAttrBase   (LIBBASE->rtl8139b_PCIDeviceAttrBase)
  92
  93 struct RTL8139Startup
  94 {
  95     struct MsgPort           *rtl8139sm_SyncPort;
  96     struct RTL8139Unit       *rtl8139sm_Unit;
  97 };
  98
  99 enum {
 100         WRITE_QUEUE,
 101         ADOPT_QUEUE,
 102         EVENT_QUEUE,
 103         GENERAL_QUEUE,
 104         REQUEST_QUEUE_COUNT
 105 };
 106
 107 struct Opener
 108 {
 109         struct MinNode  node;
 110         struct MsgPort  read_port;
 111         BOOL            (*rx_function)(APTR, APTR, ULONG);
 112         BOOL            (*tx_function)(APTR, APTR, ULONG);
 113         struct Hook     *filter_hook;
 114         struct MinList  initial_stats;
 115 };
 116
 117 struct TypeStats
 118 {
 119         struct MinNode node;
 120         ULONG packet_type;
 121         struct Sana2PacketTypeStats stats;
 122 };
 123
 124
 125 struct TypeTracker
 126 {
 127         struct MinNode node;
 128         ULONG packet_type;
 129         struct Sana2PacketTypeStats stats;
 130         ULONG user_count;
 131 };
 132
 133
 134 struct AddressRange
 135 {
 136         struct MinNode node;
 137         ULONG add_count;
 138         ULONG lower_bound_left;
 139         ULONG upper_bound_left;
 140         UWORD lower_bound_right;
 141         UWORD upper_bound_right;
 142 };
 143
 144 /* Big endian: should work, but is untested */
 145
 146 struct rx_ring_desc
 147 {
 148         IPTR    PacketBuffer;
 149         UWORD   BufferLength;
 150         UWORD   BufferStatus;
 151         ULONG   BufferMsgLength;
 152         ULONG   Reserved;
 153 };
 154
 155 struct tx_ring_desc
 156 {
 157         IPTR    PacketBuffer;
 158         UWORD   BufferLength;
 159         UWORD   BufferStatus;
 160         ULONG   Misc;
 161         ULONG   Reserved;
 162 };
 163
 164 #define STAT_COUNT 3
 165
 166 struct RTL8139Unit {
 167         struct MinNode          rtl8139u_Node;
 168
 169         struct RTL8139Base    *rtl8139u_device;
 170
 171         STRPTR                  rtl8139u_name;
 172
 173         ULONG                   rtl8139u_UnitNum;
 174         IPTR                    rtl8139u_DriverFlags;
 175
 176         OOP_Object              *rtl8139u_PCIDevice;
 177         OOP_Object              *rtl8139u_PCIDriver;
 178         IPTR                    rtl8139u_IRQ;
 179
 180         int                     rtl8139u_open_count;
 181         struct SignalSemaphore  rtl8139u_unit_lock;
 182
 183         LONG                    rtl8139u_range_count;
 184         struct MinList          rtl8139u_Openers;
 185         struct MinList          rtl8139u_multicast_ranges;
 186         struct MinList          rtl8139u_type_trackers;
 187
 188         struct timeval          rtl8139u_toutPOLL;
 189         BOOL                    rtl8139u_toutNEED;
 190
 191         struct MsgPort          *rtl8139u_TimerSlowPort;
 192         struct timerequest      *rtl8139u_TimerSlowReq;
 193
 194         struct MsgPort          *rtl8139u_TimerFastPort;
 195         struct timerequest      *rtl8139u_TimerFastReq;
 196
 197         ULONG                   rtl8139u_mtu;
 198         ULONG                   rtl8139u_flags;
 199         struct Sana2DeviceQuery  rtl8139u_Sana2Info;
 200         struct Sana2DeviceStats rtl8139u_stats;
 201         ULONG                   rtl8139u_special_stats[STAT_COUNT];
 202
 203         char                    *rtl8139u_rtl_cardname;
 204         char                    *rtl8139u_rtl_chipname;
 205         ULONG                  rtl8139u_rtl_chipcapabilities;
 206
 207         ULONG                  rtl8139u_rtl_LinkSpeed;
 208 #define support_fdx     (1 << 0) // Supports Full Duplex
 209 #define support_mii     (1 << 1)
 210 #define support_fset    (1 << 2)
 211 #define support_ltint   (1 << 3)
 212 #define support_dxsuflo (1 << 4)
 213 /* Card Funcs */
 214         void                    (*initialize)(struct RTL8139Unit *);
 215         void                    (*deinitialize)(struct RTL8139Unit *);
 216         int                     (*start)(struct RTL8139Unit *);
 217         int                     (*stop)(struct RTL8139Unit *);
 218         int                     (*alloc_rx)(struct RTL8139Unit *);
 219         void                    (*set_mac_address)(struct RTL8139Unit *);
 220         void                    (*linkchange)(struct RTL8139Unit *);
 221         void                    (*linkirq)(struct RTL8139Unit *);
 222 //    ULONG                   (*descr_getlength)(struct ring_desc *prd, ULONG v);
 223         void                    (*set_multicast)(struct RTL8139Unit *);
 224
 225         struct Process          *rtl8139u_Process;
 226
 227         HIDDT_IRQ_Handler       *rtl8139u_irqhandler;
 228         HIDDT_IRQ_Handler       *rtl8139u_touthandler;
 229         IPTR                      rtl8139u_DeviceID;
 230         IPTR                    rtl8139u_BaseMem;
 231         IPTR                    rtl8139u_SizeMem;
 232         IPTR                      rtl8139u_BaseIO;
 233
 234         BYTE                    rtl8139u_signal_0;
 235         BYTE                    rtl8139u_signal_1;
 236         BYTE                    rtl8139u_signal_2;
 237         BYTE                    rtl8139u_signal_3;
 238
 239         struct MsgPort          *rtl8139u_input_port;
 240
 241         struct MsgPort          *rtl8139u_request_ports[REQUEST_QUEUE_COUNT];
 242
 243         struct Interrupt        rtl8139u_rx_int;
 244         struct Interrupt        rtl8139u_tx_int;
 245
 246         ULONG                   rtl8139u_state;
 247         APTR                    rtl8139u_mc_list;
 248         UBYTE                   rtl8139u_dev_addr[6];
 249         UBYTE                   rtl8139u_org_addr[6];
 250         struct fe_priv          *rtl8139u_fe_priv;
 251 };
 252
 253 void handle_request(LIBBASETYPEPTR, struct IOSana2Req *);
 254
 255 /* Media selection options. */
 256 enum {
 257                 IF_PORT_UNKNOWN = 0,
 258                 IF_PORT_10BASE2,
 259                 IF_PORT_10BASET,
 260                 IF_PORT_AUI,
 261                 IF_PORT_100BASET,
 262                 IF_PORT_100BASETX,
 263                 IF_PORT_100BASEFX
 264 };
 265
 266 /* These flag bits are private to the generic network queueing
 267  * layer, they may not be explicitly referenced by any other
 268  * code.
 269  */
 270
 271 enum netdev_state_t
 272 {
 273                 __LINK_STATE_XOFF=0,
 274                 __LINK_STATE_START,
 275                 __LINK_STATE_PRESENT,
 276                 __LINK_STATE_SCHED,
 277                 __LINK_STATE_NOCARRIER,
 278                 __LINK_STATE_RX_SCHED,
 279                 __LINK_STATE_LINKWATCH_PENDING
 280 };
 281
 282 static inline int test_bit(int nr, const volatile unsigned long *addr)
 283 {
 284         return ((1UL << (nr & 31)) & (addr[nr >> 5])) != 0;
 285 }
 286
 287 static inline void set_bit(int nr, volatile unsigned long *addr)
 288 {
 289         addr[nr >> 5] |= 1UL << (nr & 31);
 290 }
 291
 292 static inline void clear_bit(int nr, volatile unsigned long *addr)
 293 {
 294         addr[nr >> 5] &= ~(1UL << (nr & 31));
 295 }
 296
 297 static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
 298 {
 299         int oldbit = test_bit(nr, addr);
 300         set_bit(nr, addr);
 301         return oldbit;
 302 }
 303
 304 static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
 305 {
 306         int oldbit = test_bit(nr, addr);
 307         clear_bit(nr, addr);
 308         return oldbit;
 309 }
 310
 311 static inline void netif_schedule(struct RTL8139Unit *dev)
 312 {
 313         if (!test_bit(__LINK_STATE_XOFF, &dev->rtl8139u_state)) {
 314                 Cause(&dev->rtl8139u_tx_int);
 315         }
 316 }
 317
 318
 319 static inline void netif_start_queue(struct RTL8139Unit *dev)
 320 {
 321         clear_bit(__LINK_STATE_XOFF, &dev->rtl8139u_state);
 322 }
 323
 324 static inline void netif_wake_queue(struct RTL8139Unit *dev)
 325 {
 326         if (test_and_clear_bit(__LINK_STATE_XOFF, &dev->rtl8139u_state)) {
 327                 Cause(&dev->rtl8139u_tx_int);
 328         }
 329 }
 330
 331 static inline void netif_stop_queue(struct RTL8139Unit *dev)
 332 {
 333         set_bit(__LINK_STATE_XOFF, &dev->rtl8139u_state);
 334 }
 335
 336 static inline int netif_queue_stopped(const struct RTL8139Unit *dev)
 337 {
 338         return test_bit(__LINK_STATE_XOFF, &dev->rtl8139u_state);
 339 }
 340
 341 static inline int netif_running(const struct RTL8139Unit *dev)
 342 {
 343         return test_bit(__LINK_STATE_START, &dev->rtl8139u_state);
 344 }
 345
 346 static inline int netif_carrier_ok(const struct RTL8139Unit *dev)
 347 {
 348         return !test_bit(__LINK_STATE_NOCARRIER, &dev->rtl8139u_state);
 349 }
 350
 351 extern void __netdev_watchdog_up(struct RTL8139Unit *dev);
 352
 353 static inline void netif_carrier_on(struct RTL8139Unit *dev)
 354 {
 355         if (test_and_clear_bit(__LINK_STATE_NOCARRIER, &dev->rtl8139u_state)) {
 356 //                linkwatch_fire_event(dev);
 357         }
 358         if (netif_running(dev)) {
 359 //                __netdev_watchdog_up(dev);
 360         }
 361 }
 362
 363 static inline void netif_carrier_off(struct RTL8139Unit *dev)
 364 {
 365         if (!test_and_set_bit(__LINK_STATE_NOCARRIER, &dev->rtl8139u_state)) {
 366 //                linkwatch_fire_event(dev);
 367         }
 368 }
 369
 370 /* Standard interface flags (netdevice->flags). */
 371 #define IFF_UP          0x1             /* interface is up              */
 372 #define IFF_BROADCAST   0x2             /* broadcast address valid      */
 373 #define IFF_DEBUG       0x4             /* turn on debugging            */
 374 #define IFF_LOOPBACK    0x8             /* is a loopback net            */
 375 #define IFF_POINTOPOINT 0x10            /* interface is has p-p link    */
 376 #define IFF_NOTRAILERS  0x20            /* avoid use of trailers        */
 377 #define IFF_RUNNING     0x40            /* resources allocated          */
 378 #define IFF_NOARP       0x80            /* no ARP protocol              */
 379 #define IFF_PROMISC     0x100           /* receive all packets          */
 380 #define IFF_ALLMULTI    0x200           /* receive all multicast packets*/
 381
 382 #define IFF_MASTER      0x400           /* master of a load balancer    */
 383 #define IFF_SLAVE       0x800           /* slave of a load balancer     */
 384
 385 #define IFF_MULTICAST   0x1000          /* Supports multicast           */
 386
 387 #define IFF_VOLATILE    (IFF_LOOPBACK|IFF_POINTOPOINT|IFF_BROADCAST|IFF_MASTER|IFF_SLAVE|IFF_RUNNING)
 388
 389 #define IFF_PORTSEL     0x2000          /* can set media type           */
 390 #define IFF_AUTOMEDIA   0x4000          /* auto media select active     */
 391 #define IFF_DYNAMIC     0x8000          /* dialup device with changing addresses*/
 392 #define IFF_SHARED      0x10000         /* interface may be shared */
 393 #define IFF_CONFIGURED  0x20000         /* interface already configured */
 394
 395 /*
 396  *      We tag multicasts with these structures.
 397  */
 398
 399 #define MAX_ADDR_LEN    32
 400
 401 struct dev_mc_list
 402 {
 403         struct dev_mc_list      *next;
 404         UBYTE                   dmi_addr[MAX_ADDR_LEN];
 405         unsigned char           dmi_addrlen;
 406         int                     dmi_users;
 407         int                     dmi_gusers;
 408 };
 409
 410 struct fe_priv {
 411         struct RTL8139Unit      *pci_dev;
 412         int                     in_shutdown;
 413         ULONG                   linkspeed;
 414         int                     duplex;
 415         int                     autoneg;
 416         int                     fixed_mode;
 417         int                     phyaddr;
 418         int                     wolenabled;
 419         unsigned int            phy_oui;
 420         UWORD                   gigabit;
 421         ULONG                   desc_ver;
 422         struct SignalSemaphore  lock;
 423
 424         IPTR                    ring_addr;
 425
 426 /* Start - rtl new */
 427         int                     full_duplex;
 428
 429         char                    mii_phys[4]; //MII device address
 430         unsigned short          advertising;  //NWay media advertising
 431
 432         unsigned int            rx_config;
 433         UBYTE                   *rx_buffer;
 434         unsigned int            rx_buf_len;
 435         unsigned int            rx_current;
 436
 437         ULONG                   tx_flag;
 438         UBYTE                   *tx_buffer;
 439         unsigned char           *tx_pbuf[NUM_TX_DESC];
 440         unsigned char           *tx_buf[NUM_TX_DESC];
 441         unsigned int            tx_dirty;
 442         unsigned int            tx_current;
 443 /* End - rtl new */
 444
 445         unsigned short          cur_rx;
 446         ULONG                   refill_rx;
 447
 448         ULONG                   next_tx, nic_tx;
 449         ULONG                   tx_flags;
 450
 451         ULONG                   irqmask;
 452         ULONG                   need_linktimer;
 453         struct  timeval         link_timeout;
 454         UBYTE                   orig_mac[6];
 455 };
 456
 457 #define pci_name(unit)  (unit->rtl8139u_name)
 458
 459 /* ENET defines */
 460
 461 #define HZ                  1000000
 462 #define ETH_DATA_LEN        1500
 463
 464 #define ETH_ADDRESSSIZE     6
 465 #define ETH_HEADERSIZE      14
 466 #define ETH_CRCSIZE         4
 467 #define ETH_MTU             (ETH_DATA_LEN)
 468 #define ETH_MAXPACKETSIZE   ((ETH_HEADERSIZE) + (ETH_MTU) + (ETH_CRCSIZE))
 469
 470 #define ETH_PACKET_DEST     0
 471 #define ETH_PACKET_SOURCE   6
 472 #define ETH_PACKET_TYPE     12
 473 #define ETH_PACKET_IEEELEN  12
 474 #define ETH_PACKET_SNAPTYPE 20
 475 #define ETH_PACKET_DATA     14
 476 #define ETH_PACKET_CRC      (ETH_PACKET_DATA + ETH_MTU)
 477
 478 #define RXTX_ALLOC_BUFSIZE  (ETH_MAXPACKETSIZE + 26)
 479
 480 #define TX_LIMIT_STOP   63
 481 #define TX_LIMIT_START  62
 482
 483 struct eth_frame {
 484         UBYTE eth_packet_dest[6];
 485         UBYTE eth_packet_source[6];
 486         UWORD eth_packet_type;
 487         UBYTE eth_packet_data[ETH_MTU];
 488         UBYTE eth_packet_crc[4];
 489         UBYTE eth_pad[RXTX_ALLOC_BUFSIZE - ETH_MAXPACKETSIZE];
 490 } __attribute__((packed));
 491 #define eth_packet_ieeelen eth_packet_type
 492
 493 void rtl8139nic_get_functions(struct RTL8139Unit *Unit);
 494
 495 /* ***************************** */
 496 /*       RTL8139 DEFINES         */
 497 /* ***************************** */
 498
 499 enum rtl_boardcapabilities
 500 {
 501   RTLc_HAS_MII_XCVR    = 0x01,
 502   RTLc_HAS_CHIP_XCVR   = 0x02,
 503   RTLc_HAS_LNK_CHNG    = 0x04,
 504   RTLc_HAS_DESC        = 0x08
 505 };
 506
 507 // Symbolic offsets to registers
 508
 509 enum rtl_registers
 510 {
 511   RTLr_MAC0             = 0x00,       // Ethernet hardware address
 512   RTLr_MAR0             = 0x08,       // Multicast filter
 513   RTLr_TxStatus0        = 0x10,       // Transmit status (Four 32bit registers)
 514   RTLr_TxAddr0          = 0x20,       // Tx descriptors (also four 32bit)
 515   RTLr_RxBuf            = 0x30,
 516   RTLr_RxEarlyCnt       = 0x34,
 517   RTLr_RxEarlyStatus    = 0x36,
 518   RTLr_ChipCmd          = 0x37,
 519   RTLr_RxBufPtr         = 0x38,
 520   RTLr_RxBufAddr        = 0x3A,
 521   RTLr_IntrMask         = 0x3C,
 522   RTLr_IntrStatus       = 0x3E,
 523   RTLr_TxConfig         = 0x40,
 524   RTLr_RxConfig         = 0x44,
 525   RTLr_Timer            = 0x48,        // A general-purpose counter
 526   RTLr_RxMissed         = 0x4C,        // 24 bits valid, write clears
 527   RTLr_Cfg9346          = 0x50,
 528   RTLr_Config0          = 0x51,
 529   RTLr_Config1          = 0x52,
 530   RTLr_FlashReg         = 0x54,
 531   RTLr_GPPinData        = 0x58,
 532   RTLr_GPPinDir         = 0x59,
 533   RTLr_MII_SMI          = 0x5A,
 534   RTLr_HltClk           = 0x5B,
 535   RTLr_MultiIntr        = 0x5C,
 536   RTLr_TxSummary        = 0x60,
 537   RTLr_MII_BMCR         = 0x62,
 538   RTLr_MII_BMSR         = 0x64,
 539   RTLr_NWayAdvert       = 0x66,
 540   RTLr_NWayLPAR         = 0x68,
 541   RTLr_NWayExpansion    = 0x6A,
 542
 543   // Undocumented registers, but required for proper operation
 544   RTLr_FIFOTMS          = 0x70,        // FIFO Control and test
 545   RTLr_CSCR             = 0x74,        // Chip Status and Configuration Register
 546   RTLr_PARA78           = 0x78,
 547   RTLr_PARA7c           = 0x7c,        // Magic transceiver parameter register
 548 };
 549
 550 enum rtl_chipcmdbits
 551 {
 552   RxBufEmpty = 0x01,
 553   CmdTxEnb   = 0x04,
 554   CmdRxEnb   = 0x08,
 555   CmdReset   = 0x10,
 556 };
 557
 558 // Interrupt register bits
 559
 560 enum rtl_intrstatusbits
 561 {
 562   RxOK       = 0x0001,
 563   RxErr      = 0x0002,
 564   TxOK       = 0x0004,
 565   TxErr      = 0x0008,
 566   RxOverflow = 0x0010,
 567   RxUnderrun = 0x0020,
 568   RxFIFOOver = 0x0040,
 569   PCSTimeout = 0x4000,
 570   PCIErr     = 0x8000,
 571 };
 572
 573 #define RxAckBits (RxFIFOOver | RxOverflow | RxOK)
 574
 575 enum rtl_txstatusbits
 576 {
 577   TxHostOwns    = 0x00002000,
 578   TxUnderrun    = 0x00004000,
 579   TxStatOK      = 0x00008000,
 580   TxOutOfWindow = 0x20000000,
 581   TxAborted     = 0x40000000,
 582   TxCarrierLost = 0x80000000,
 583 };
 584
 585 enum rtl_rxstatusbits
 586 {
 587   RxStatusOK  = 0x0001,
 588   RxBadAlign  = 0x0002,
 589   RxCRCErr    = 0x0004,
 590   RxTooLong   = 0x0008,
 591   RxRunt      = 0x0010,
 592   RxBadSymbol = 0x0020,
 593   RxBroadcast = 0x2000,
 594   RxPhysical  = 0x4000,
 595   RxMulticast = 0x8000,
 596 };
 597
 598 // Bits in RxConfig
 599
 600 enum rtl_rxconfigbits
 601 {
 602   AcceptAllPhys   = 0x01,
 603   AcceptMyPhys    = 0x02,
 604   AcceptMulticast = 0x04,
 605   AcceptRunt      = 0x10,
 606   AcceptErr       = 0x20,
 607   AcceptBroadcast = 0x08,
 608 };
 609
 610 enum rtl_txconfigbits
 611 {
 612         /* Interframe Gap Time. Only TxIFG96 doesnt violate IEEE 802.3 */
 613         TxIFGShift = 24,
 614         TxIFG84 = (0<<TxIFGShift), /* 8.4us / 840ns */
 615         TxIFG88 = (1<<TxIFGShift), /* 8.8us / 880ns */
 616         TxIFG92 = (2<<TxIFGShift), /* 9.2us / 920ns */
 617         TxIFG96 = (3<<TxIFGShift), /* 9.6us / 960ns */
 618
 619         TxLoopBack = (1<<18) | (1<<17),  /* Enable loopback test mode */
 620         TxCRC          = (1<<16),                  /* Disable appending CRC to end of Tx Packet */
 621         TxClearAbt   = (1<<0),                    /* Clear abort (WO) */
 622         TxDMAShift = 8,                               /* DMA burst value (0-7) is shifted this many bits */
 623         TxRetryShift = 4,                              /* TXRR value (0-15) is shifted this many bits */
 624
 625         TxVersionMask = 0x7c800000        /* Mask out version bits 30-26, 23 */
 626 };
 627
 628
 629 enum rtl_config1bits
 630 {
 631         Cfg1_PM_Enable    = 0x01,
 632         Cfg1_VPD_Enable  = 0x02,
 633         Cfg1_PIO               = 0x04,
 634         Cfg1_MMIO           = 0x08,
 635         LWAKE                  = 0x10,               /* Not on 8139/8139A */
 636         Cfg1_Driver_Load = 0x20,
 637         Cfg1_LED0            = 0x40,
 638         Cfg1_LED1            = 0x80
 639 };
 640
 641 enum rtl_cscrbits
 642 {
 643   CSCR_LinkOKBit      = 0x00400,
 644   CSCR_LinkDownOffCmd = 0x003c0,
 645   CSCR_LinkChangeBit  = 0x00800,
 646   CSCR_LinkStatusBits = 0x0f000,
 647   CSCR_LinkDownCmd    = 0x0f3c0,
 648 };
 649
 650 /** Serial EEPROM section **/
 651
 652 //  EEPROM_Ctrl bits
 653
 654 #define EE_SHIFT_CLK      0x04  // EEPROM shift clock
 655 #define EE_CS                  0x08  // EEPROM chip select
 656 #define EE_DATA_WRITE   0x02  // EEPROM chip data in
 657 #define EE_WRITE_0         0x00
 658 #define EE_WRITE_1         0x02
 659 #define EE_DATA_READ    0x01  // EEPROM chip data out
 660 #define EE_ENB               (0x80 | EE_CS)
 661
 662 // Delay between EEPROM clock transitions.
 663 // No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
 664
 665 #define eeprom_delay(ee_addr)  LONGIN(ee_addr)
 666
 667 // The EEPROM commands include the alway-set leading bit
 668
 669 #define EE_WRITE_CMD  (5)
 670 #define EE_READ_CMD   (6)
 671 #define EE_ERASE_CMD  (7)
 672
 673 /** MII serial management **/
 674
 675 // Read and write the MII management registers using software-generated
 676 // serial MDIO protocol.
 677 // The maximum data clock rate is 2.5 Mhz.  The minimum timing is usually
 678 // met by back-to-back PCI I/O cycles, but we insert a delay to avoid
 679 // "overclocking" issues
 680
 681 #define MDIO_DIR              0x80
 682 #define MDIO_DATA_OUT  0x04
 683 #define MDIO_DATA_IN      0x02
 684 #define MDIO_CLK             0x01
 685 #define MDIO_WRITE0       (MDIO_DIR)
 686 #define MDIO_WRITE1       (MDIO_DIR | MDIO_DATA_OUT)
 687
 688 #define mdio_delay(mdio_addr) LONGIN(mdio_addr)
 689
 690 int rtl8139nic_set_rxmode(struct net_device *dev);
 691
 692 #endif