workbench/devs/networks/via-rhine/via-rhine.c

   1 /*
   2  * $Id$
   3  */
   4
   5 /*
   6     This program is free software; you can redistribute it and/or modify
   7     it under the terms of the GNU General Public License as published by
   8     the Free Software Foundation; either version 2 of the License, or
   9     (at your option) any later version.
  10
  11     This program is distributed in the hope that it will be useful, but
  12     WITHOUT ANY WARRANTY; without even the implied warranty of
  13     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14     General Public License for more details.
  15
  16     You should have received a copy of the GNU General Public License
  17     along with this program; if not, write to the Free Software
  18     Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  19     MA 02111-1307, USA.
  20 */
  21
  22 #include <exec/types.h>
  23 #include <exec/resident.h>
  24 #include <exec/io.h>
  25 #include <exec/ports.h>
  26
  27 #include <aros/libcall.h>
  28 #include <aros/macros.h>
  29 #include <aros/io.h>
  30
  31 #include <oop/oop.h>
  32
  33 #include <devices/sana2.h>
  34 #include <devices/sana2specialstats.h>
  35
  36 #include <utility/utility.h>
  37 #include <utility/tagitem.h>
  38 #include <utility/hooks.h>
  39
  40 #include <hidd/pci.h>
  41 #include <hidd/irq.h>
  42
  43 #include <proto/oop.h>
  44 #include <proto/exec.h>
  45 #include <proto/dos.h>
  46 #include <proto/battclock.h>
  47
  48 #include <stdlib.h>
  49
  50 #include "via-rhine.h"
  51 #include "unit.h"
  52 #include LC_LIBDEFS_FILE
  53
  54 /* A bit fixed linux stuff here :) */
  55
  56 #undef LIBBASE
  57 #define LIBBASE (dev->rhineu_device)
  58
  59 #define net_device VIARHINEUnit
  60
  61 #define TIMER_RPROK 3599597124UL
  62
  63 static ULONG usec2tick(ULONG usec)
  64 {
  65     ULONG ret, timer_rpr = TIMER_RPROK;
  66     asm volatile("movl $0,%%eax; divl %2":"=a"(ret):"d"(usec),"m"(timer_rpr));
  67     return ret;
  68 }
  69
  70 void udelay(LONG usec)
  71 {
  72     int oldtick, tick;
  73     usec = usec2tick(usec);
  74
  75     BYTEOUT(0x43, 0x80);
  76     oldtick = BYTEIN(0x42);
  77     oldtick += BYTEIN(0x42) << 8;
  78
  79     while (usec > 0)
  80     {
  81         BYTEOUT(0x43, 0x80);
  82         tick = BYTEIN(0x42);
  83         tick += BYTEIN(0x42) << 8;
  84
  85         usec -= (oldtick - tick);
  86         if (tick > oldtick) usec -= 0x10000;
  87         oldtick = tick;
  88     }
  89 }
  90
  91 static inline struct fe_priv *get_pcnpriv(struct net_device *dev)
  92 {
  93     return dev->rhineu_fe_priv;
  94 }
  95
  96 static inline UBYTE *get_hwbase(struct net_device *dev)
  97 {
  98     return (UBYTE*)dev->rhineu_BaseMem;
  99 }
 100
 101 static int mdio_read(struct net_device *dev, int phy_id, int location)
 102 {
 103         UBYTE *base = get_hwbase(dev);
 104
 105         int i = 1024;
 106
 107         while ((BYTEIN(base + VIAR_MIICmd) & 0x60) && --i > 0)
 108         {
 109         }
 110
 111         BYTEOUT(base + VIAR_MIICmd, 0x00);
 112         BYTEOUT(base + VIAR_MIIPhyAddr, phy_id);
 113         BYTEOUT(base + VIAR_MIIRegAddr, location);
 114         BYTEOUT(base + VIAR_MIICmd, 0x40);             //Trigger the read
 115
 116         i = 1024;
 117
 118         while ((BYTEIN(base + VIAR_MIICmd) & 0x40) && --i > 0)
 119         {
 120         }
 121
 122         return WORDIN(base + VIAR_MIIData);
 123 }
 124
 125 static void viarhinenic_start_rx(struct net_device *dev)
 126 {
 127     struct fe_priv *np = get_pcnpriv(dev);
 128     UBYTE *base = get_hwbase(dev);
 129
 130 D(bug("%s: viarhinenic_start_rx\n", dev->rhineu_name));
 131     // Already running? Stop it.
 132 #warning "TODO: Handle starting/stopping Rx"
 133 }
 134
 135 static void viarhinenic_stop_rx(struct net_device *dev)
 136 {
 137     UBYTE *base = get_hwbase(dev);
 138
 139 D(bug("%s: viarhinenic_stop_rx\n", dev->rhineu_name));
 140 #warning "TODO: Handle starting/stopping Rx"
 141 }
 142
 143 static void viarhinenic_start_tx(struct net_device *dev)
 144 {
 145     UBYTE *base = get_hwbase(dev);
 146
 147 D(bug("%s: viarhinenic_start_tx()\n", dev->rhineu_name));
 148 #warning "TODO: Handle starting/stopping Tx"
 149 }
 150
 151 static void viarhinenic_stop_tx(struct net_device *dev)
 152 {
 153     UBYTE *base = get_hwbase(dev);
 154
 155 D(bug("%s: viarhinenic_stop_tx()\n", dev->rhineu_name));
 156 #warning "TODO: Handle starting/stopping Tx"
 157 }
 158
 159 static void viarhinenic_txrx_reset(struct net_device *dev)
 160 {
 161     struct fe_priv *np = get_pcnpriv(dev);
 162     UBYTE *base = get_hwbase(dev);
 163
 164 D(bug("%s: viarhinenic_txrx_reset()\n", dev->rhineu_name));
 165 }
 166
 167 /*
 168  * viarhinenic_set_multicast: dev->set_multicast function
 169  * Called with dev->xmit_lock held.
 170  */
 171 static void viarhinenic_set_multicast(struct net_device *dev)
 172 {
 173     struct fe_priv *np = get_pcnpriv(dev);
 174     UBYTE *base = get_hwbase(dev);
 175     ULONG addr[2];
 176     ULONG mask[2];
 177     ULONG pff;
 178
 179 D(bug("%s: viarhinenic_set_multicast()\n", dev->rhineu_name));
 180
 181     memset(addr, 0, sizeof(addr));
 182     memset(mask, 0, sizeof(mask));
 183 }
 184
 185 static void viarhinenic_deinitialize(struct net_device *dev)
 186 {
 187 //    dev->write_csr(dev->rhineu_BaseMem, 0, (1 << 2)); /* Stop the PCnet32 by setting the stop bit.. */
 188 D(bug("%s: PCnet32 chipset STOPPED\n", dev->rhineu_name));
 189
 190 //    dev->write_bcr(dev->rhineu_BaseMem, 20, 4); /* Set pcnet32 into 16bit mode */
 191 D(bug("%s: Chipset put into 16bit mode\n", dev->rhineu_name));
 192 }
 193
 194 static void viarhinenic_initialize(struct net_device *dev)
 195 {
 196     struct fe_priv *np = dev->rhineu_fe_priv;
 197     UBYTE *base = get_hwbase(dev);
 198     int i, config1;
 199
 200         WORDOUT(base + VIAR_ChipCmd, CmdReset);
 201         udelay(20000);
 202 D(bug("%s: VIA Rhine Reset.\n", dev->rhineu_name));
 203
 204         for (i = 0; i < 6; i++)
 205         {
 206                 np->orig_mac[i] = BYTEIN(base + VIAR_StationAddr + i);
 207         }
 208
 209         int phy, phy_idx = 0;
 210         if (dev->rhineu_chipcapabilities & RTLc_CanHaveMII)
 211         {
 212                 np->mii_phys[0] = 1;
 213                 for (phy = 0; (phy < 32) && (phy_idx < 4); phy++)
 214                 {
 215                         int mii_status = mdio_read(dev, phy, 1);
 216                         if (mii_status != 0xffff && mii_status != 0x0000)
 217                         {
 218                                 np->mii_phys[phy_idx++] = phy;
 219                                 np->mii_advertising = mdio_read(dev, phy, 4);
 220 D(bug("%s: MII transceiver %d status 0x%4.4x advertising %4.4x\n", dev->rhineu_name,
 221                                                                                                                                                                                                                   phy, mii_status, np->mii_advertising));
 222
 223                         }
 224                 }
 225         }
 226
 227     dev->rhineu_dev_addr[0] = dev->rhineu_org_addr[0] = np->orig_mac[0];
 228     dev->rhineu_dev_addr[1] = dev->rhineu_org_addr[1] = np->orig_mac[1];
 229     dev->rhineu_dev_addr[2] = dev->rhineu_org_addr[2] = np->orig_mac[2];
 230     dev->rhineu_dev_addr[3] = dev->rhineu_org_addr[3] = np->orig_mac[3];
 231
 232     dev->rhineu_dev_addr[4] = dev->rhineu_org_addr[4] = np->orig_mac[4];
 233     dev->rhineu_dev_addr[5] = dev->rhineu_org_addr[5] = np->orig_mac[5];
 234
 235 D(bug("%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", dev->rhineu_name,
 236             dev->rhineu_dev_addr[0], dev->rhineu_dev_addr[1], dev->rhineu_dev_addr[2],
 237             dev->rhineu_dev_addr[3], dev->rhineu_dev_addr[4], dev->rhineu_dev_addr[5]));
 238 }
 239
 240 static void viarhinenic_drain_tx(struct net_device *dev)
 241 {
 242     struct fe_priv *np = get_pcnpriv(dev);
 243     int i;
 244     for (i = 0; i < TX_BUFFERS; i++) {
 245 #warning "TODO: viarhinenic_drain_tx does nothing atm."
 246     }
 247 }
 248
 249 static void viarhinenic_drain_rx(struct net_device *dev)
 250 {
 251     struct fe_priv *np = get_pcnpriv(dev);
 252     int i;
 253     for (i = 0; i < RX_BUFFERS; i++) {
 254 #warning "TODO: viarhinenic_drain_rx does nothing atm."
 255     }
 256 }
 257
 258
 259 static void drain_ring(struct net_device *dev)
 260 {
 261     viarhinenic_drain_tx(dev);
 262     viarhinenic_drain_rx(dev);
 263 }
 264
 265 static int request_irq(struct net_device *dev)
 266 {
 267     OOP_Object *irq = OOP_NewObject(NULL, CLID_Hidd_IRQ, NULL);
 268     BOOL ret;
 269
 270 D(bug("%s: request_irq()\n", dev->rhineu_name));
 271
 272     if (irq)
 273     {
 274         ret = HIDD_IRQ_AddHandler(irq, dev->rhineu_irqhandler, dev->rhineu_IRQ);
 275         HIDD_IRQ_AddHandler(irq, dev->rhineu_touthandler, vHidd_IRQ_Timer);
 276
 277 D(bug("%s: request_irq: IRQ Handlers configured\n", dev->rhineu_name));
 278
 279         OOP_DisposeObject(irq);
 280
 281         if (ret)
 282         {
 283             return 0;
 284         }
 285     }
 286     return 1;
 287 }
 288
 289 static void free_irq(struct net_device *dev)
 290 {
 291     OOP_Object *irq = OOP_NewObject(NULL, CLID_Hidd_IRQ, NULL);
 292     if (irq)
 293     {
 294         HIDD_IRQ_RemHandler(irq, dev->rhineu_irqhandler);
 295         HIDD_IRQ_RemHandler(irq, dev->rhineu_touthandler);
 296         OOP_DisposeObject(irq);
 297     }
 298 }
 299
 300 int viarhinenic_rx_setmode(struct net_device *dev)
 301 {
 302         struct fe_priv *np = get_pcnpriv(dev);
 303         UBYTE *base = get_hwbase(dev);
 304         unsigned long mc_filter[2];         //Multicast hash filter.
 305         unsigned int rx_mode;
 306
 307         mc_filter[1] = mc_filter[0] = 0x0;
 308
 309         if (dev->rhineu_flags & IFF_PROMISC)
 310         {
 311 D(bug("%s: viarhinenic_rx_setmode: PROMISCUOUS Mode\n", dev->rhineu_name));
 312                 rx_mode = 0x1c;
 313         }
 314         else if (dev->rhineu_flags & IFF_ALLMULTI)
 315         {
 316 D(bug("%s: viarhinenic_rx_setmode: ALL MULTICAST Enabled\n", dev->rhineu_name));
 317                 rx_mode = 0x0c;
 318                 mc_filter[1] = mc_filter[0] = 0xffffffff;
 319         }
 320         else
 321         {
 322 D(bug("%s: viarhinenic_rx_setmode: Default Rx Mode (no Multi or Promisc)\n", dev->rhineu_name));
 323                 rx_mode = 0x1a;
 324         }
 325
 326         LONGOUT(base + VIAR_MulticastFilter0, mc_filter[0]);
 327         LONGOUT(base + VIAR_MulticastFilter1, mc_filter[1]);
 328         BYTEOUT(base + VIAR_RxConfig, np->rx_thresh | rx_mode);
 329
 330         return 0;
 331 }
 332
 333 static void viarhinenic_set_mac(struct net_device *dev)
 334 {
 335    UBYTE *base = get_hwbase(dev);
 336    int i;
 337
 338         for (i = 0; i < 6; i++)
 339         {
 340                 BYTEOUT(base + VIAR_StationAddr + i, dev->rhineu_dev_addr[i]);
 341         }
 342 }
 343
 344 static int viarhinenic_open(struct net_device *dev)
 345 {
 346    struct fe_priv *np = get_pcnpriv(dev);
 347    UBYTE *base = get_hwbase(dev);
 348    int ret, oom, i;
 349    ULONG txb_size, rxb_size;
 350
 351    txb_size = BUFFER_SIZE * TX_BUFFERS;
 352    rxb_size = BUFFER_SIZE * RX_BUFFERS;
 353
 354    oom = 0;
 355
 356         ret = request_irq(dev);
 357         if (ret)
 358                 goto out_drain;
 359
 360     np->tx_buffer = HIDD_PCIDriver_AllocPCIMem(
 361                         dev->rhineu_PCIDriver,
 362                         txb_size);
 363
 364     if (np->tx_buffer == NULL)
 365     {
 366       oom = 1;
 367     }
 368     else
 369     {
 370 D(bug("%s: viarhinenic_open: Tx Ring buffers allocated @ %x\n", dev->rhineu_name, np->tx_buffer));
 371                 for (i=0; i< TX_BUFFERS; i++)
 372                 {
 373                         np->tx_desc[i].tx_status = 0;
 374                         np->tx_desc[i].desc_length = 0;
 375                         np->tx_desc[i].addr = (IPTR)(np->tx_buffer + (i * BUFFER_SIZE));
 376                         np->tx_desc[i].next = &np->tx_desc[i + 1];
 377 D(bug("%s: viarhinenic_open: Tx Ring %d @ %x, Buffer = %x\n",dev->rhineu_name,
 378                         i, &np->tx_desc[i], np->tx_desc[i].addr));
 379                 }
 380                 np->tx_desc[i-1].next = &np->tx_desc[0];
 381         }
 382
 383     np->rx_buffer = HIDD_PCIDriver_AllocPCIMem(
 384                         dev->rhineu_PCIDriver,
 385                         rxb_size);
 386
 387         if (np->rx_buffer == NULL)
 388         {
 389                 oom = 1;
 390         }
 391         else
 392         {
 393 D(bug("%s: viarhinenic_open: Rx Ring buffers allocated @ %x\n", dev->rhineu_name, np->rx_buffer));
 394                 for (i=0; i< RX_BUFFERS; i++)
 395                 {
 396                         np->rx_desc[i].rx_status = DescOwn;
 397                         np->rx_desc[i].desc_length = MAX_FRAME_SIZE;
 398                         np->rx_desc[i].addr = (IPTR)( np->rx_buffer + (i * BUFFER_SIZE));
 399                         np->rx_desc[i].next = &np->rx_desc[i + 1];
 400 D(bug("%s: viarhinenic_open: Rx Ring %d @ %x, Buffer = %x\n",dev->rhineu_name,
 401                         i, &np->rx_desc[i], np->rx_desc[i].addr));
 402                 }
 403                 np->rx_desc[i-1].next = &np->rx_desc[0];
 404         }
 405
 406    if (oom == 0)
 407    {
 408 D(bug("%s: viarhinenic_open: Allocated IO Buffers [ %d x Tx @ %x] [ %d x Rx @ %x]\n",dev->rhineu_name,
 409                         TX_BUFFERS, np->tx_buffer,
 410                         RX_BUFFERS, np->rx_buffer));
 411
 412         viarhinenic_set_mac(dev);
 413 D(bug("%s: viarhinenic_open: copied MAC address\n",dev->rhineu_name));
 414
 415                 //Set up Frame Buffer Ring Descriptors
 416                 LONGOUT(base + VIAR_TxRingPtr, &np->tx_desc[0]);
 417                 LONGOUT(base + VIAR_RxRingPtr, &np->rx_desc[0]);
 418
 419 D(bug("%s: viarhinenic_open: Frame Buffer Ring Descriptors set\n",dev->rhineu_name));
 420
 421                 //Initialise other registers
 422                 WORDOUT(base + VIAR_PCIBusConfig, 0x0006);
 423
 424                 np->tx_thresh = 0x20;
 425                 np->rx_thresh = 0x60;
 426
 427                 BYTEOUT(base + VIAR_TxConfig, np->tx_thresh);
 428                 viarhinenic_rx_setmode(dev);
 429
 430 D(bug("%s: viarhinenic_open: Tx/Rx Configuration set\n",dev->rhineu_name));
 431
 432                 /* check_duplex *//*
 433                 if (np->mii_phys[0] >= 0 || (dev->rhineu_rtl_chipcapabilities & RTLc_HAS_MII_XCVR))
 434                 {
 435                         unsigned short mii_reg5 = mdio_read(dev, np->mii_phys[0], 5);
 436                         if (mii_reg5 != 0xffff)
 437                         {
 438                                 if (((mii_reg5 & 0x0100) == 0x0100) || ((mii_reg5 & 0x00c0) == 0x0040))
 439                                 {
 440                                         np->full_duplex = 1;
 441                                 }
 442                         }
 443
 444                         if ((mii_reg5 == 0 ) || !(mii_reg5 & 0x0180))
 445                         {
 446                            dev->rhineu_rtl_LinkSpeed = 10000000;
 447                         }
 448                         else
 449                         {
 450                            dev->rhineu_rtl_LinkSpeed = 100000000;
 451                         }
 452
 453 D(bug("%s: viarhinenic_open: Setting %s%s-duplex based on auto-neg partner ability %4.4x\n",dev->rhineu_name,
 454                                                                                                                                                              mii_reg5 == 0 ? "" : (mii_reg5 & 0x0180) ? "100mbps " : "10mbps ",
 455                                                                                                                                                              np->full_duplex ? "full" : "half", mii_reg5));
 456                 }*/
 457
 458                 //Enable all known interrupts by setting the interrupt mask ..
 459                 WORDOUT(base + VIAR_IntrEnable, (IntrRxDone | IntrRxErr | IntrRxEmpty | IntrRxOverflow| IntrRxDropped | IntrTxDone | IntrTxAbort | IntrTxUnderrun | IntrPCIErr | IntrStatsMax | IntrLinkChange | IntrMIIChange));
 460
 461                 np->cmd = CmdStart | CmdTxOn | CmdRxOn | CmdRxDemand;
 462
 463                 WORDOUT(base + VIAR_ChipCmd, np->cmd);
 464
 465            dev->rhineu_flags |= IFF_UP;
 466            ReportEvents(LIBBASE, dev, S2EVENT_ONLINE);
 467 D(bug("%s: viarhinenic_open: Device set as ONLINE\n",dev->rhineu_name));
 468    }
 469    return 0;
 470
 471 out_drain:
 472     drain_ring(dev);
 473     return ret;
 474 }
 475
 476 static int viarhinenic_close(struct net_device *dev)
 477 {
 478     struct fe_priv *np = get_pcnpriv(dev);
 479     UBYTE *base;
 480
 481     dev->rhineu_flags &= ~IFF_UP;
 482
 483     ObtainSemaphore(&np->lock);
 484     np->in_shutdown = 1;
 485     ReleaseSemaphore(&np->lock);
 486
 487     dev->rhineu_toutNEED = FALSE;
 488
 489     netif_stop_queue(dev);
 490     ObtainSemaphore(&np->lock);
 491
 492     viarhinenic_deinitialize(dev);    // Stop the chipset and set it in 16bit-mode
 493
 494     base = get_hwbase(dev);
 495
 496     ReleaseSemaphore(&np->lock);
 497
 498     free_irq(dev);
 499
 500     drain_ring(dev);
 501
 502     HIDD_PCIDriver_FreePCIMem(dev->rhineu_PCIDriver, np->rx_buffer);
 503     HIDD_PCIDriver_FreePCIMem(dev->rhineu_PCIDriver, np->tx_buffer);
 504
 505     ReportEvents(LIBBASE, dev, S2EVENT_OFFLINE);
 506
 507     return 0;
 508 }
 509
 510
 511 void viarhinenic_get_functions(struct net_device *Unit)
 512 {
 513     Unit->initialize = viarhinenic_initialize;
 514     Unit->deinitialize = viarhinenic_deinitialize;
 515     Unit->start = viarhinenic_open;
 516     Unit->stop = viarhinenic_close;
 517     Unit->set_mac_address = viarhinenic_set_mac;
 518     Unit->set_multicast = viarhinenic_set_multicast;
 519 }