arch/.unmaintained/m68k-native/exec/cachepostdma.s

   1 /*
   2     Copyright © 1995-2001, The AROS Development Team. All rights reserved.
   3     $Id$
   4 */
   5
   6 /******************************************************************************
   7
   8     NAME
   9
  10         AROS_LH3(void, CachePostDMA,
  11
  12     SYNOPSIS
  13         AROS_LHA(APTR,    address, A0),
  14         AROS_LHA(ULONG *, length,  A1),
  15         AROS_LHA(ULONG,   flags,  D0),
  16
  17     LOCATION
  18         struct ExecBase *, SysBase, 128, Exec)
  19
  20     FUNCTION
  21         Do everything necessary to make CPU caches aware that a DMA has
  22         happened.
  23
  24     INPUTS
  25         address - Virtual address of memory affected by the DMA
  26         *length - Number of bytes affected
  27         flags   - DMA_NoModify    - Indicate that the memory did not change.
  28                   DMA_ReadFromRAM - Indicate that the DMA goes from RAM
  29                                     to the device. Set this bit in bot calls.
  30
  31     RESULT
  32
  33     NOTES
  34         DMA must follow a call to CachePreDMA() and must be followed
  35         by a call to CachePostDMA().
  36
  37     EXAMPLE
  38
  39     BUGS
  40
  41     SEE ALSO
  42         CachePreDMA()
  43
  44     INTERNALS
  45
  46     HISTORY
  47
  48 ******************************************************************************/
  49
  50 /*
  51    XDEF AROS_SLIB_ENTRY(CachePostDMA,Exec)      ; for 68000/10/20
  52    XDEF AROS_SLIB_ENTRY(CachePostDMA_30,Exec)   ; for 68030+
  53    XDEF AROS_SLIB_ENTRY(CachePostDMA_40,Exec)   ; for 68040/68060
  54 */
  55
  56         #include "machine.i"
  57
  58         .text
  59         .balign 4
  60         .globl  AROS_SLIB_ENTRY(CachePostDMA,Exec)
  61         .type   AROS_SLIB_ENTRY(CachePostDMA,Exec),@function
  62 AROS_SLIB_ENTRY(CachePostDMA,Exec):
  63         rts
  64
  65         .text
  66         .balign 4
  67         .globl  AROS_SLIB_ENTRY(CachePostDMA_30,Exec)
  68         .type   AROS_SLIB_ENTRY(CachePostDMA_30,Exec),@function
  69 AROS_SLIB_ENTRY(CachePostDMA_30,Exec):
  70         btst.l  #DMAB_NoModify,d0       /* Has DMA modified data in mem? */
  71         bne.s   cpd_30_end              /* nope, just exit */
  72         move.l  a5,a1                   /* save a5 */
  73         lea.l   cachepostdmasup_30(pc),a5
  74         jmp     Supervisor(a6)
  75
  76 cpd_30_end:
  77         rts
  78
  79 cachepostdmasup_30:
  80         /* A DMA device has changed data in main memory. We have to clear
  81            the data cache, so we get the chance to see this new data. */
  82         or.w    #0x0700,sr      /* Disable interrupts */
  83         movec   cacr,d0
  84         bset.l  #11,d0          /* Set CD Clear Data cache bit */
  85         movec   d0,cacr
  86         rte
  87
  88         .text
  89         .balign 4
  90         .globl  AROS_SLIB_ENTRY(CachePostDMA_40,Exec)
  91         .type   AROS_SLIB_ENTRY(CachePostDMA_40,Exec),@function
  92 AROS_SLIB_ENTRY(CachePostDMA_40,Exec):
  93         btst.l  #DMAB_NoModify,d0       /* Has DMA modified data in mem? */
  94         bne.s   cpd_40_end              /* nope, just exit */
  95         move.l  a5,a1                   /* save a5 */
  96         lea.l   cachepostdmasup_40(pc),a5
  97         jmp     Supervisor(a6)
  98
  99 cpd_40_end:
 100         rts
 101
 102 cachepostdmasup_40:
 103         /* A DMA device has changed data in main memory. We have to invalidate
 104            the data cache, so we get the chance to see this new data. */
 105         cinva   dc
 106         rte