Fixed a few warnings.
[tangerine.git] / arch / ppc-chrp / efika / include / asm / io.h
blob5fba5fc17ca3e75906a09ee0f15753be36b66664
1 #ifndef ASM_IO_H
2 #define ASM_IO_H
4 #include <inttypes.h>
6 static inline eieio() {
7 asm volatile("eieio":::"memory");
10 static inline sync() {
11 asm volatile("sync":::"memory");
14 static inline isync() {
15 asm volatile("isync":::"memory");
18 static inline uint8_t inb(uint8_t *port) {
19 uint8_t ret; asm volatile("sync; lbz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*port)); return ret;
22 static inline void outb(uint8_t val, char *port) {
23 asm volatile("stb%U0%X0 %1,%0; eieio; sync"::"m"(*port),"r"(val));
26 static inline uint16_t inw(uint16_t *port) {
27 uint16_t ret; asm volatile("sync; lhz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*port)); return ret;
30 static inline void outw(uint16_t val, uint16_t *port) {
31 asm volatile("sth%U0%X0 %1,%0; eieio; sync"::"m"(*port),"r"(val));
34 static inline uint16_t inw_be(uint16_t *port) {
35 return inw(port);
39 static inline void outw_be(uint16_t val, uint16_t *port) {
40 outw(val, port);
43 static inline uint16_t inw_le(uint16_t *port) {
44 uint16_t ret; asm volatile("sync; lhbrx %0,0,%1; eieio":"=r"(ret):"r"(port),"m"(*port)); return ret;
47 static inline void outw_le(uint16_t val, uint16_t *port) {
48 asm volatile("sthbrx %1,0,%2; eieio; sync":"=m"(*port):"r"(val),"r"(port));
52 static inline uint32_t inl(uint32_t *port) {
53 uint32_t ret; asm volatile("sync; lwz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*port)); return ret;
56 static inline void outl(uint32_t val, uint32_t *port) {
57 asm volatile("stw%U0%X0 %1,%0; eieio; sync"::"m"(*port),"r"(val));
60 static inline uint32_t inl_be(uint32_t *port) {
61 return inl(port);
64 static inline void outl_be(uint32_t val, uint32_t *port) {
65 outl(val, port);
68 static inline uint32_t inl_le(uint32_t *port) {
69 uint32_t ret; asm volatile("sync; lwbrx %0,0,%1; eieio":"=r"(ret):"r"(port),"m"(*port)); return ret;
72 static inline void outl_le(uint32_t val, uint32_t *port) {
73 asm volatile("stwbrx %1,0,%2; eieio; sync":"=m"(*port):"r"(val),"r"(port));
76 //static inline void pci_outb(uint8_t val, uint16_t port)
77 //{
78 // outb(val, (uint8_t *)(port + PCIC0_IO));
79 //}
81 //static inline void pci_outw(uint16_t val, uint16_t port)
82 //{
83 // outw(val, (uint16_t *)(port + PCIC0_IO));
84 //}
86 //static inline void pci_outw_be(uint16_t val, uint16_t port)
87 //{
88 // outw_be(val, (uint16_t *)(port + PCIC0_IO));
89 //}
91 //static inline void pci_outw_le(uint16_t val, uint16_t port)
92 //{
93 // outw_le(val, (uint16_t *)(port + PCIC0_IO));
94 //}
96 //static inline void pci_outl(uint32_t val, uint16_t port)
97 //{
98 // outl(val, (uint32_t *)(port + PCIC0_IO));
99 //}
101 //static inline void pci_outl_be(uint32_t val, uint16_t port)
103 // outl_be(val, (uint32_t *)(port + PCIC0_IO));
106 //static inline void pci_outl_le(uint32_t val, uint16_t port)
108 // outl_le(val, (uint32_t *)(port + PCIC0_IO));
111 //static inline uint8_t pci_inb(uint16_t port)
113 // return inb((uint8_t *)(port + PCIC0_IO));
116 //static inline uint16_t pci_inw(uint16_t port)
118 // return inw((uint16_t *)(port + PCIC0_IO));
121 //static inline uint16_t pci_inw_be(uint16_t port)
123 // return inw_be((uint16_t *)(port + PCIC0_IO));
126 //static inline uint16_t pci_inw_le(uint16_t port)
128 // return inw_le((uint16_t *)(port + PCIC0_IO));
131 //static inline uint32_t pci_inl(uint16_t port)
133 // return inl((uint32_t *)(port + PCIC0_IO));
136 //static inline uint32_t pci_inl_be(uint16_t port)
138 // return inl_be((uint32_t *)(port + PCIC0_IO));
141 //static inline uint32_t pci_inl_le(uint16_t port)
143 // return inl_le((uint32_t *)(port + PCIC0_IO));
147 #endif /*ASM_IO_H*/